A blade-scrapped diode chip with simplified process and its manufacturing method

Abstract

The application relates to a manufacturing method of a simple process knife-scratching diode chip, which is characterized in that N+ is made by phosphorus source diffusion at the bottom, P+ is made by boron source diffusion at the upper part, the N+ bottom and the P+ upper part are provided with a nickel / gold metal layer, and the chip periphery and edge beak are wrapped in a glass passivation protective layer; the manufacturing process comprises the following steps: substrate cleaning, phosphorus diffusion, first sand blowing cleaning, boron diffusion, second sand blowing cleaning, oxidation annealing, first photoetching, groove etching, beak etching, cleaning, scratching and coating glass powder (including wiping powder), glass passivation, deoxidation, nickel / gold plating, electrical property testing, laser cutting and the like. The beak is directly etched to move downward, at this time, the beak is under the glass protection which is flush with the table top, is not easy to strike fire, has high voltage resistance, and has good reliability; after the glass is scratched and coated, the wiping powder which is easy to operate is adopted, the solderable area is increased, VF is reduced, the production cycle is shortened, and the photoresist of the yellow light process and the corresponding labor cost are saved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor wafer manufacturing, specifically relating to a simplified process for manufacturing a die-cut diode chip and its manufacturing method. Background Technology

[0002] With the development of semiconductor process technology, the performance requirements for semiconductor devices are becoming increasingly stringent. After wafers are diced into individual dies through chemical etching, the isotropic nature of the etching acid on silicon causes the die tips to protrude significantly when viewed from the side. During use, the electric field at these tips can cause breakdown discharges if the chips are cleaned using conventional scraping methods. If the surface powder is simply wiped clean, the sharp corners are almost entirely unprotected by glass, which amplifies leakage current issues and increases the failure rate. Figure 1 .

[0003] Currently, there are two directions for improvement: one method is to reserve a certain thickness of glass on the worktable, and then remove the glass on the welding surface by adding a photolithography process, such as... Figure 2 Method two involves adding a photolithography pass before trench etching to pre-etch the edge areas, such as... Figure 3 All of these involve adding a photolithography process, which lengthens the production cycle and increases costs. Furthermore, it reduces the area to be soldered later, thus affecting the product's VF parameters. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a simplified manufacturing process for a die-cut diode chip and its fabrication method.

[0005] To achieve the above objectives, the technical solution used in this invention is as follows: A simplified process for a blade-scraped diode chip is disclosed. The diode chip uses an N-type silicon substrate, with phosphorus source diffusion at the bottom to create N+ and boron source diffusion at the top to create P+. Nickel / gold metal layers are provided at the bottom of N+ and the top of P+. The "bird's beak" around the chip and at the edge are all wrapped in a glass passivation protective layer.

[0006] The preferred design involves moving the beak section downwards from its original flush position with the tabletop, thereby increasing the thickness of the glass protection around the sharp corners and improving the product's stability.

[0007] The preferred bird beak is protected by glass flush with the countertop, and the entire countertop is weldable.

[0008] A simplified fabrication method for die-cut diode chips includes the following steps: 1) Substrate selection: N-type monocrystalline silicon wafers are used.

[0009] 2) Substrate cleaning: The silicon wafer is rinsed with mixed acid to remove the surface damage layer generated after silicon wafer cutting and grinding. Then it is ultrasonically cleaned with surface cleaning agent to remove residual particles on the surface. Then it is ultrasonically cleaned with deionized water and finally spun dry.

[0010] 3) Phosphorus diffusion: A quantitative amount of liquid phosphorus source is coated on one side of the silicon wafer. After baking, curing and cooling, the wafer is collected and pressed into a boat. It is then diffused into a 3-point temperature-controlled high-temperature furnace in a vertical diffusion manner to form an N+ layer with a certain concentration and junction depth.

[0011] 4) First-pass sandblasting cleaning: Remove the phosphosilicate glass layer formed on the surface of the silicon wafer through phosphorus diffusion, then perform diamond abrasive blasting treatment, followed by ultrasonic cleaning with surface cleaning agent and then spin drying.

[0012] 5) Boron diffusion: The side of the silicon wafer that has not been diffused by sandblasting is coated with a quantitative liquid boron source, baked, cured and cooled, then the wafer is collected and pressed into a boat, and diffused in a 3-point temperature-controlled high-temperature furnace to form a P+ layer with a certain concentration and junction depth.

[0013] 6) Secondary sandblasting cleaning: Remove the borosilicate glass layer formed on the surface of the silicon wafer through boron diffusion, then perform diamond sand blasting treatment, followed by ultrasonic cleaning with surface cleaning agent and then spin drying.

[0014] 7) Oxidation annealing: In a three-point temperature-controlled high-temperature furnace with a fixed amount of oxygen introduced, the stress of the silicon wafer is removed, and the oxide layer on the surface has a gettering effect.

[0015] 8) Single photolithography: A uniform layer of negative photoresist is coated on the boron-expanded surface of the silicon wafer. After soft baking, exposure, development, fixing, and hard baking are performed to copy the pattern on the designed photomask to the surface.

[0016] 9) Trench etching: After photolithography, the silicon wafer is subjected to trench etching in a certain proportion of mixed acid (nitric acid / hydrofluoric acid / glacial acetic acid / sulfuric acid) to expose the PN junction. The area with photoresist is protected and does not participate in the reaction.

[0017] 10) Bird beak etching: After trench etching, the bird beak has been formed on the edge of the segmented chip. Then, a certain proportion of mixed acid (nitric acid / hydrofluoric acid / glacial acetic acid / phosphoric acid) is used for etching treatment.

[0018] 11) Cleaning: For the PN junction exposed after corrosion, rinse with mixed acid, deoxidize with hydrofluoric acid, clean with RCA and ultrasonic cleaning.

[0019] 12) Applying glass powder (including wiping): Apply glass powder to the PN junction trenches of the silicon wafer after cleaning. After baking and curing, wipe the surface to remove the powder, leaving only the glass in the trenches.

[0020] 13) Glass passivation: In the high-temperature furnace tube, the glass in the groove undergoes softening, melting, cooling and solidification to form a dense and stable protective layer.

[0021] 14) Deoxidation: Immersion in buffer oxide etching solution BOE (ammonium fluoride: hydrofluoric acid = 6-8:1) to remove the silicon dioxide oxide layer formed on the surface of the silicon wafer after high temperature, so as to facilitate subsequent metallization.

[0022] 15) Nickel / Gold Plating: A layer of nickel metal is plated onto the surface of the silicon wafer by chemical plating. The nickel is then sintered in a low-temperature furnace to form a nickel-silicon alloy. A second nickel plating is then applied to increase weldability. A gold plating layer can also be added to increase its oxidation resistance.

[0023] 16) Electrical testing: According to the product design requirements, the separated chips are 100% tested, and defective chips are marked with ink dots by a dotting device.

[0024] 17) Laser cutting: Using an infrared laser, the chips on the silicon wafer are cut according to the laser design layout to form independent semiconductor diode chips.

[0025] As a preferred embodiment, step 3) uses a mixture of ammonium dihydrogen phosphate and anhydrous ethanol as the liquid phosphorus source. The phosphorus diffusion temperature is 1200-1270℃, and the diffusion time is 2-5 hours. During this time, high-purity nitrogen and oxygen are introduced in a ratio of 5-8:1-2. After high-temperature phosphorus diffusion, an N+ layer of a certain concentration and depth is formed. The sheet resistance of the N+ layer is required to be 0.25-0.35 Ω / hole, and the depth is 10-20 μm.

[0026] As a preferred embodiment, step 5) uses a liquid boron source consisting of a mixture of boron oxide and aluminum nitrate dissolved in ethylene glycol ethyl ether. The diffusion temperature is 1260-1270℃, and the diffusion time is 22-30 hours. During this time, high-purity nitrogen and oxygen are introduced in a ratio of 3-6:1-2. After high-temperature boron diffusion, a P+ layer of a certain concentration and depth is formed. The sheet resistance of the P+ layer is required to be 0.1-0.2Ω / Ω, and the depth is 95-115µm.

[0027] As a preferred embodiment, step 9) involves etching the silicon wafer using a low-temperature mixed acid mixture of nitric acid: hydrofluoric acid: sulfuric acid: glacial acetic acid = 9:9:12:4-8, at an operating temperature of -10 to -3 degrees Celsius, for a time of 900-1500 seconds, to achieve an etching depth of 135-160 μm.

[0028] As a preferred step, step 10) is the core process of the present invention. After trench etching, the silicon wafer is etched with a mixed acid of nitric acid: hydrofluoric acid: phosphoric acid: glacial acetic acid = 3-6:1-2:1:1-2. The working temperature is -3 to 3°C and the time is 180-420 seconds. The etching rate is accelerated in the high-concentration sharp corner area, forming a chain reaction. The gas bubbles generated by the reaction cause the acid to react more with the surface sharp corners than in the trench.

[0029] Compared with the prior art, the advantages of the present invention are as follows: 1. Removing the bird beak by mixing acid lowers the beak part to 5-20um below the tabletop, where it is flush with the glass, providing excellent protection. This makes the product less prone to sparking and ensures stable electrical performance.

[0030] 2. Due to the downward shift of the sharp corners, a simple direct powder removal process can be used, and the glass powder on and above the tabletop can be directly removed, leaving only the glass in the groove under the tabletop surface, thus eliminating the need for glass removal and the required photolithography and etching before nickel plating.

[0031] 3. The effective welding surface is large, and the entire piece can be immersed in BOE to remove oxidation after glass passivation. The entire exposed table surface can be used as a nickel / gold plating surface. When using photolithography, the welding surface needs to be smaller than the table surface for easy operation and to leave corrosion allowance (taking a 44mil product as an example, the photolithography table surface is about 26mil, while the table surface of this process can reach about 30mil).

[0032] 4. Under the premise of meeting all electrical performance parameters, this method reduces one pre-glass coating process (coating / soft baking / exposure / development / hard baking) compared to Method 1, totaling 2 working days; and reduces one pre-beak etching process (coating / soft baking / exposure / development / hard baking) compared to Method 2, totaling 2 working days. The production cycle and material costs (the coating process accounts for a relatively high proportion of the production cost) are significantly reduced. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the traditional method of making wafers by wiping off the surface powder normally.

[0034] Figure 2 This is a diagram illustrating the traditional photolithography method for manufacturing wafers. Figure 1 .

[0035] Figure 3 This is a diagram illustrating the traditional photolithography method for manufacturing wafers. Figure 2 .

[0036] Figure 4-10 This is a schematic diagram of the wafer fabrication process of the present invention.

[0037] In the figure, (1) is an N-type silicon substrate, (2) is a phosphorus diffusion layer, (3) is a boron diffusion layer, (4) is a bird's beak after conventional etching, (5) is a trench, (6) is a bird's beak that has been etched and moved downwards, (7) is a glass passivation layer, and (8) is a nickel / gold layer. Detailed Implementation

[0038] The following is in conjunction with the appendix Figure 4-10 The present invention will be further illustrated by the following examples: Example 1: As shown in the structural diagram, the simplified process die-cutting diode chip and its manufacturing method according to the present invention include the following steps: 1) Substrate selection: This product uses N-type crystal orientation. <111> The silicon wafers produced have a resistivity of 25-35 Ω·cm and a thickness of 280-295 μm.

[0039] 2) Substrate cleaning: The silicon wafer is rinsed with mixed acid to remove the surface damage layer generated after silicon wafer cutting and grinding. Then, it is ultrasonically cleaned with surface cleaning agent to remove residual particles on the surface. Finally, it is ultrasonically cleaned with deionized water with a resistance >16MΩ.

[0040] 3) Phosphorus diffusion: A quantitative amount of liquid phosphorus is coated onto one side of the silicon wafer. After baking, curing, and cooling, the wafer is collected, pressed into a boat, and vertically diffused into a 3-point temperature-controlled high-temperature furnace. The phosphorus diffusion temperature is 1200-1270℃, and the diffusion time is 2-5 hours. During this process, high-purity nitrogen and oxygen are introduced in a ratio of 5-8:1-2. After high-temperature phosphorus diffusion, an N+ layer of a certain concentration and depth is formed. The sheet resistance of the N+ layer is required to be 0.25-0.35Ω / hole, and the depth is 10-20um.

[0041] 4) First-pass sandblasting cleaning: Remove the phosphosilicate glass layer formed on the surface of the silicon wafer through phosphorus diffusion, then perform diamond abrasive blasting treatment, followed by ultrasonic cleaning with surface cleaning agent and then spin drying.

[0042] 5) Boron diffusion: The side of the silicon wafer that has not undergone phosphorus diffusion after sandblasting is coated with a quantitative liquid boron source, baked, cured, and cooled. The wafer is then collected, pressed into a boat, and vertically diffused into a 3-point temperature-controlled high-temperature furnace. The boron diffusion temperature is 1260-1270℃, and the diffusion time is 22-30 hours. During this time, high-purity nitrogen and oxygen are introduced in a ratio of 3-6:1-2. After high-temperature boron diffusion, a P+ layer of a certain concentration and depth is formed. The sheet resistance of the P+ layer is required to be 0.1-0.2Ω / hole, and the depth is 95-115um.

[0043] 6) Secondary sandblasting cleaning: Remove the borosilicate glass layer formed on the surface of the silicon wafer through boron diffusion, then perform diamond sand blasting treatment, followed by ultrasonic cleaning with surface cleaning agent and then spin drying.

[0044] 7) Oxidation annealing: In a three-point temperature-controlled high-temperature furnace with a fixed amount of oxygen introduced, the stress on the silicon wafer is removed, and the oxide layer on the surface has a gettering effect. The temperature is 1150-1260℃, the time is 2-4 hours, and the process is carried out with 2-6 liters of high-purity oxygen per minute.

[0045] 8) Single photolithography: A uniform layer of negative photoresist is coated on the boron-expanded surface of the silicon wafer. After soft baking, exposure, development, fixing, and hard baking are performed to copy the pattern on the designed photomask to the surface.

[0046] 9) Trench etching: The silicon wafer after photolithography is etched in a low-temperature mixed acid of nitric acid: hydrofluoric acid: sulfuric acid: glacial acetic acid = 9:9:12:4-8. The working temperature is -10 to -3 degrees Celsius, the time is 900-1500 seconds, and the etching depth is 135-160um.

[0047] 10) Bird beak etching: After the groove etching of the silicon wafer, add a mixed acid of nitric acid: hydrofluoric acid: phosphoric acid: glacial acetic acid = 3-6:1-2:1:1-2 for etching. The working temperature is -3 to 3℃ and the time is 180-420 seconds, so that the bird beak moves down 5-20um from the table surface.

[0048] 11) Cleaning: For the exposed PN junction after corrosion, rinse with mixed acid, deoxidize with hydrofluoric acid, clean with RCA, clean with ultrasonic, and finally rinse with deionized water to remove water resistance. The resistance value must be >12MΩ.

[0049] 12) Applying glass powder (including wiping): Apply glass powder to the PN junction trenches of the silicon wafer after cleaning. After baking and curing, wipe the surface to remove the powder, leaving only the glass in the trenches.

[0050] 13) Glass passivation: First, organic matter is burned out at a low temperature of 500℃, and then the glass undergoes softening, melting (820-860℃), cooling and solidification to form a dense and stable protective layer.

[0051] 14) Deoxidation: Soaking in BOE (ammonium fluoride: hydrofluoric acid = 6-8:1) removes the silicon dioxide oxide layer formed on the surface of the silicon wafer after high temperature, in order to facilitate subsequent metallization.

[0052] 15) Nickel / Gold Plating: A layer of nickel metal is plated onto the surface of the silicon wafer by chemical plating. The nickel is then sintered in a low-temperature furnace to form a nickel-silicon alloy. A second nickel plating is then applied to increase weldability. A gold plating layer can also be added to increase its oxidation resistance.

[0053] 16) Electrical testing: According to the product design requirements, the separated chips are 100% tested, and defective chips are marked with ink dots by a dotting device.

[0054] 17) Laser cutting: Using an infrared laser, the chips on the silicon wafer are cut according to the laser design layout to form independent semiconductor diode chips.

[0055] 18) After cleaning and dehydration, the die-scraped diode chip fabrication is complete.

[0056] This invention's diode chip uses an N-type silicon substrate. Phosphorus source diffusion is used to create N+ at the bottom, and boron source diffusion is used to create P+ at the top. Nickel / gold metal layers are formed at the bottom of the N+ layer and above the P+ layer. The chip's perimeter and edge "bird's beak" are encased in a glass passivation protective layer. The manufacturing process includes: substrate cleaning --- phosphorus diffusion --- first sandblasting cleaning --- boron diffusion --- second sandblasting cleaning --- oxidation annealing --- first photolithography --- trench etching --- bird's beak etching --- cleaning --- glass powder coating (including powder wiping) --- glass passivation --- oxidation removal --- nickel / gold plating --- electrical testing --- laser cutting, etc. This invention directly etches the beak area to move it downwards (at this point, the beak is protected by glass flush with the tabletop, making it less prone to sparking, with high pressure resistance and good reliability), without adding photolithography processing; and after scraping the glass, the easier-to-operate powder wiping replaces the subsequent secondary photolithography for tabletop glass removal (increasing the solderable area, which helps reduce VF). Without affecting quality, these two improvements directly shorten the production cycle and save photoresist and corresponding labor costs in the photolithography process.

Claims

1. A simplified manufacturing process for a die-cut diode chip, characterized in that, The manufacturing method includes the following steps: 1) Substrate selection: N-type monocrystalline silicon wafers are used for fabrication; 2) Substrate cleaning: The silicon wafer is rinsed with mixed acid to remove the surface damage layer generated after silicon wafer cutting and grinding. Then it is ultrasonically cleaned with surface cleaning agent to remove residual particles on the surface. Then it is ultrasonically cleaned with deionized water and finally spun dry. 3) Phosphorus diffusion: A quantitative amount of liquid phosphorus source is coated on one side of the silicon wafer. After baking, curing and cooling, the wafer is collected and pressed into a boat. It is then diffused in a three-point temperature-controlled high-temperature furnace in a vertical diffusion manner to form an N+ layer with a certain concentration and junction depth. 4) First-pass sandblasting cleaning: Remove the phosphosilicate glass layer formed on the surface of the silicon wafer after phosphorus diffusion, then perform diamond abrasive blasting, followed by ultrasonic cleaning with surface cleaning agent and then spin drying. 5) Boron diffusion: The side of the silicon wafer that has not been diffused by sandblasting is coated with a quantitative liquid boron source, baked, cured and cooled, then the wafer is collected and pressed into a boat, and diffused in a three-point temperature-controlled high-temperature furnace in a vertical diffusion manner to form a P+ layer with a certain concentration and junction depth. 6) Secondary sandblasting cleaning: Remove the borosilicate glass layer formed on the surface of the silicon wafer through boron diffusion, then perform diamond sand blasting treatment, followed by ultrasonic cleaning with surface cleaning agent and then spin drying. 7) Oxidation annealing: In a three-point temperature-controlled high-temperature furnace with a fixed amount of oxygen introduced, the stress of the silicon wafer is removed, and the oxide layer on the surface has a gettering effect. 8) One-time photolithography: A uniform layer of negative photoresist is coated on the boron-expanded surface of the silicon wafer. After soft baking, exposure, development, fixing and hard baking are performed to copy the pattern on the designed photomask to the surface. 9) Trench etching: After photolithography, the silicon wafer is subjected to trench etching in a certain proportion of mixed acid to expose the PN junction. The area with photoresist is protected and does not participate in the reaction. 10) Bird beak etching: After trench etching, the bird beak shape is formed on the edge of the segmented chip. Then, a certain proportion of mixed acid is used for etching treatment. 11) Cleaning: For the PN junction exposed after corrosion, the process is carried out by mixed acid rinsing, hydrofluoric acid deoxidation, RCA cleaning, and ultrasonic cleaning. 12) Apply glass powder and wipe powder: Apply glass powder to the PN junction trench of the silicon wafer after cleaning. After baking and curing, wipe the surface to remove the glass powder, leaving only the glass in the trench. 13) Glass passivation: In the high-temperature furnace tube, the glass in the groove undergoes softening, melting, cooling and solidification to form a dense and stable protective layer; 14) Deoxidation: Immersion in buffer oxide etching solution (BOE) removes the silicon dioxide oxide layer formed on the surface of the silicon wafer after high temperature to facilitate subsequent metallization; 15) Nickel / Gold Plating: A layer of nickel metal is plated onto the surface of the silicon wafer by chemical plating. The nickel is sintered in a low-temperature furnace to form a nickel-silicon alloy. Nickel is then plated again to increase weldability, and then a layer of gold is plated to increase its oxidation resistance. 16) Electrical testing: According to the product design requirements, the separated chips are 100% tested, and defective chips are marked with ink dots by a dotting device; 17) Laser cutting: Using an infrared laser, the chips on the silicon wafer are cut according to the laser design layout to form independent semiconductor diode chips.

2. The method for manufacturing a simplified die-cut diode chip according to claim 1, characterized in that, In step 3), the liquid phosphorus source is a mixture of ammonium dihydrogen phosphate and anhydrous ethanol. The phosphorus diffusion temperature is 1200-1270℃, and the diffusion time is 2-5 hours. During this period, high-purity nitrogen and oxygen are introduced in a ratio of 5-8:1-2. After high-temperature phosphorus diffusion, an N+ layer of a certain concentration and depth is formed. The sheet resistance of the N+ layer is required to be 0.25-0.35Ω / hole, and the depth is 10-20μm.

3. The method for manufacturing a simplified die-cut diode chip according to claim 1, characterized in that, In step 5), the liquid boron source is a mixture of boron oxide and aluminum nitrate dissolved in ethylene glycol ethyl ether. The boron diffusion temperature is 1260-1270℃, and the diffusion time is 22-30 hours. During this period, high-purity nitrogen and oxygen are introduced in a ratio of 3-6:1-2. After high-temperature boron diffusion, a P+ layer of a certain concentration and depth is formed. The sheet resistance of the P+ layer is required to be 0.1-0.2Ω / Ω, and the depth is 95-115μm.

4. The method for manufacturing a simplified die-cut diode chip according to claim 1, characterized in that, In step 9), the silicon wafer is etched using a low-temperature mixture of nitric acid, hydrofluoric acid, sulfuric acid, and glacial acetic acid in a volume ratio of 9:9:12:4-8. The working temperature is -10 to -3 degrees Celsius, the time is 900-1500 seconds, and the etching depth is 135-160 μm.

5. The method for manufacturing a simplified die-cut diode chip according to claim 1, characterized in that, In step 10), the silicon wafer after trench etching is subjected to mixed acid etching with a volume ratio of nitric acid: hydrofluoric acid: phosphoric acid: glacial acetic acid of 3-6:1-2:1:1-2. The working temperature is -3 to 3℃ and the time is 180-420 seconds, so that the bird beak moves down 5-20μm from the table surface.

6. The method for manufacturing a simplified die-cut diode chip according to claim 1, characterized in that, The volume ratio of ammonium fluoride to hydrofluoric acid in the buffer oxide etching solution BOE is 6-8:

1.

7. The method for manufacturing a simplified die-cut diode chip according to claim 1, characterized in that, The simplified process of the scraper diode chip uses an N-type silicon substrate. Phosphorus source diffusion is performed at the bottom to create N+, and boron source diffusion is performed at the top to create P+. Nickel / gold metal layers are provided at the bottom of N+ and the top of P+. The "bird's beak" around the chip and at the edge is wrapped in a glass passivation protective layer. The "bird's beak" is below the mesa plane, and the entire mesa is a solderable surface.

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