Substrate via and method of manufacturing a substrate via

Abstract

An open substrate through hole (1) TSV comprises an insulating layer (20) arranged adjacent to at least part of a side wall (15) of a trench (14) and to a surface (13) of a substrate body (10). The TSV further comprises a metallization layer (30) arranged adjacent to at least part of the insulating layer (20) and to at least part of a bottom wall (16) of the trench (14), a redistribution layer (40) arranged adjacent to at least part of the metallization layer (30) and to the part of the insulating layer (20) arranged adjacent to the surface (13), and a capping layer (50) arranged adjacent to at least part of the metallization layer (30) and to at least part of the redistribution layer (40). The insulating layer (20) and / or the capping layer (50) comprise sub-layers (21, 22, 51, 52) that differ from each other in material properties. A first one (21, 51) of the sub-layers is arranged adjacent to at least part of the side wall (15) and to at least part of the surface (13), and a second one (22, 52) of the sub-layers is arranged adjacent to at least part of the surface (13).

Description

[0001] The present invention relates to an open substrate via and a method of manufacturing an open substrate via.

[0002] For electrically contacting an integrated circuit of a semiconductor device or another part of a semiconductor device, it is a common approach to form a substrate via TSV through the substrate of the device. Thus, a trench is formed in the substrate. The trench is at least partially filled with an electrically conductive contact material and the contact material is electrically insulated from the substrate. An integrated circuit which can be arranged on the circuit side of the substrate can be electrically contacted through the TSV. The TSV can be electrically contacted at a contact side of the substrate which faces away from the circuit side of the substrate by means of a solder bump. In this way, the device or the integrated circuit can be electrically contacted from the contact side of the substrate.

[0003] For realizing the above described TSV structure, different material layers are employed. The electrical insulation between the electrically conductive contact material, which is typically a metal, and the substrate, which is typically a silicon substrate, is realized by means of an insulating layer such as a silicon dioxide layer. Furthermore, a capping layer can be employed to protect certain parts of the TSV and / or the rest of the semiconductor device.

[0004] However, the different materials employed can have significantly different material properties such as different values of Young's modulus. This can in turn lead to a large stress gradient between the different layers, which can lead to undesired strain in the final device, increasing the probability of cracking. Conventional approaches employ a high stress insulating layer to compensate for any stress formed in the remaining layers. However, this approach can lead to an increased probability of cracking within the trench of the TSV.

[0005] It is an object of the present invention to provide an improved concept for a TSV structure with increased stress compensation. This object is achieved by the subject matter of the independent claims. Further refinements and embodiments are described in the dependent claims.

[0006] The improved concept is based on the idea of depositing the insulating layer and / or the capping layer as sub-layers during the TSV manufacturing process. These sub-layers have different internal stresses, preventing any undesired significant strain of the final device while maintaining an insignificant probability of cracking, particularly in the TSV region of the final device.

[0007] An open TSV according to the improved concept comprises a substantially planar substrate body comprising a semiconductor portion and an interlayer dielectric portion arranged adjacent to the semiconductor portion, wherein the semiconductor portion has a surface. The TSV further comprises a trench extending at least through the semiconductor portion from the surface, wherein the trench is characterized by a sidewall and a bottom wall. The TSV further comprises an insulating layer arranged adjacent to at least a portion of the sidewall and the surface, a metallization layer arranged adjacent to at least a portion of the insulating layer and at least a portion of the bottom wall, and a redistribution layer arranged adjacent to at least a portion of the metallization layer and a portion of the insulating layer arranged adjacent to the surface. The TSV further comprises a cap layer arranged adjacent to at least a portion of the metallization layer and at least a portion of the redistribution layer.

[0008] The insulating layer and / or the cap layer comprise sub-layers which differ from each other in terms of material properties. A first one of the sub-layers is arranged adjacent to at least a portion of the sidewall and at least a portion of the surface. A second one of the sub-layers is arranged adjacent to at least a portion of the surface.

[0009] The substrate body comprises, for example, a semiconductor substrate as the semiconductor portion. The semiconductor substrate is, for example, a silicon substrate. The interlayer dielectric portion comprises, for example, metal layers which are insulated from each other by an interlayer dielectric such as an oxide and form, for example, an active circuit of an integrated circuit. The interlayer dielectric portion is arranged on a substrate surface of the semiconductor portion. For example, the interlayer dielectric portion is arranged on a treated surface of the semiconductor portion, which can be referred to as a top side of the silicon substrate. The TSV is realized by first forming a trench which extends from a surface of the substrate body facing away from the interlayer dielectric portion at least through the semiconductor portion and, optionally, partially through the interlayer dielectric portion in a vertical or substantially vertical direction. The surface of the semiconductor portion can be referred to as a bottom surface of the substrate. In this context, "vertical" refers to a direction perpendicular to the surface of the substrate body. The trench is characterized by a sidewall oriented perpendicular or substantially perpendicular to the surface and a bottom wall parallel or substantially parallel to the surface.

[0010] The insulating layer is arranged adjacent to at least a portion of the sidewall and the surface. For example, the insulating layer is a conformal type layer which covers at least a portion or, optionally, the entire sidewall of the trench. The insulating layer can be arranged in immediate proximity to the sidewall, i.e. in direct contact with the sidewall. Alternatively, an additional layer can be arranged between the sidewall of the trench and the portion of the insulating layer covering the sidewall. Furthermore, the insulating layer covers at least a portion of the surface. Similarly to the portion of the insulating layer covering the sidewall, the portion of the insulating layer covering the surface can be arranged in immediate proximity to the surface, i.e. in direct contact with the surface, or an additional layer can be arranged between the surface and the portion of the insulating layer.

[0011] The metallization layer is arranged adjacent to the bottom wall and to the portion of the insulating layer arranged adjacent to the side wall. This means that the metallization layer is arranged within the trench. Similar to the arrangement of the insulating layer described above, adjacent can mean an immediate arrangement or, alternatively, an arrangement with additional layers between the insulating layer and the metallization layer. The metallization layer is made of an electrically conductive material, such as a metal.

[0012] Like the metallization layer, the redistribution layer is also made of an electrically conductive material. For example, the material of the metallization layer and the material of the redistribution layer are the same. The redistribution layer is arranged immediately adjacent to at least a portion of the metallization layer and to the portion of the insulating layer adjacent to the surface. In particular, the metallization layer is in electrical contact with said portion of the metallization layer and can thus extend partially into the trench. In some embodiments, the metallization layer and the redistribution layer are arranged as a single layer, such as a conformal metal layer.

[0013] For example, the cover layer is arranged such that in the region of the trench, the metallization layer and the redistribution layer are covered by said cover layer. The cover layer can be made of the same material as the material of the insulating layer. The cover layer can serve as a protective layer and / or as a stress compensation layer that compensates for stresses formed within and / or across the remaining layers.

[0014] The insulating layer and / or the cover layer comprises sub-layers. This means that the insulating layer and / or the cover layer is formed by depositing at least two sub-layers. For example, the insulating layer and / or the cover layer comprises a first layer and a second layer of sub-layers, wherein the first layer can be a conformal layer arranged adjacent to the portion of the side wall and to the portion of the surface, and the second layer can be a non-conformal layer arranged adjacent to the portion of the first sub-layer arranged adjacent to said portion of the surface.

[0015] The sub-layers differ from each other in terms of material properties. For example, the sub-layers are made of different materials, or they are made of the same material but have different material properties resulting from, for example, different compositions and / or deposition methods. For example, the first layer and the second layer of sub-layers differ from each other in terms of internal stress, material composition, and / or microstructure.

[0016] Since a high amount of internal stress within the trench is undesirable because it can lead to an increased probability of cracking, the second layer of sub-layers can be a non-conformal layer as described above and can have a higher internal stress than the first layer of sub-layers, which can be a conformal layer. In this way, the internal stress formed by the other layers of the TSV, i.e. within or across the other layers of the TSV, can be compensated for such that significant strain in the final TSV is prevented while avoiding significant internal stress within the trench of the TSV.

[0017] In some embodiments, the insulating layer comprises a first insulating sublayer and a second insulating sublayer, wherein the first insulating layer is arranged adjacent to at least part of the sidewall and to at least part of the surface. Further, the second insulating sublayer is arranged immediately adjacent to the first insulating sublayer and to at least part of the surface.

[0018] In these embodiments, the first insulating sublayer corresponds to a first layer of the sublayers, and the second insulating sublayer corresponds to a second layer of the sublayers.

[0019] In some embodiments, the cover layer comprises a first cover sublayer and a second cover sublayer, wherein the first cover sublayer is arranged adjacent to at least part of the sidewall and to at least part of the surface. Further, the second cover sublayer is arranged immediately adjacent to the first cover sublayer and to at least part of the surface.

[0020] In these embodiments, the first cover sublayer corresponds to a first layer of the sublayers, and the second cover sublayer corresponds to a second layer of the sublayers.

[0021] Depending on the manufacturing process, the insulating layer or the cover layer can be formed by depositing the sublayers as described above. Alternatively, both the insulating layer and the cover layer can be formed by depositing the respective sublayers.

[0022] In some embodiments, the first layer of the sublayers is arranged between the surface and the second layer of the sublayers. In some alternative embodiments, the second layer of the sublayers is arranged between the surface and the first layer of the sublayers.

[0023] Depending on the manufacturing process, the second layer of the sublayers can be deposited before or after the first layer of the sublayers. This means that the second layer of the sublayers, which can be a non-conformal layer, is arranged at a larger or smaller distance from the surface of the substrate body compared to the first layer of the sublayers, which can be a conformal layer.

[0024] In some embodiments, the first layer of the sublayers has an internal stress of tensile or compressive type, and the second layer of the sublayers has an internal stress of the respective other type.

[0025] In some alternative embodiments, the first layer of the sublayers is characterized by an internal stress of tensile or compressive type, and the second layer of the sublayers is characterized by an internal stress of the same type as the internal stress of the first layer of the sublayers but of different magnitude.

[0026] Depending on the type of internal stress exhibited by the remaining layers, the sub-layers can be both of the compressive or tensile type, or they have different types of stress. For example, a first one of the sub-layers is a conformal layer that extends into the trench and has an internal stress of the compressive type. However, the stress can be chosen to be less than the required stress to compensate for the internal stress generated by the remaining layers, thereby reducing the probability of cracking within the trench. In this example, a second one of the sub-layers, which can be a non-conformal layer, can have a greater internal stress of the compressive type than the first one of the sub-layers to compensate for the internal stress generated by the remaining layers. If the internal stress generated by the remaining layers is of the compressive type, the first one of the sub-layers can still be chosen to have an internal stress of the compressive type, while the second one of the sub-layers has an internal stress of the tensile type to compensate for the stress formed within or across the first one of the sub-layers and the remaining layers. This case applies to situations where a global smaller compressive stress is required within the trench of the TSV to further reduce the probability of cracking.

[0027] In some embodiments, the trench extends at least partially into the dielectric portion.

[0028] The contact layers can be buried within the dielectric portion. In order for the TSV to electrically contact these contact layers, the trench in these embodiments needs to extend partially into the dielectric portion.

[0029] In some embodiments, the insulating layer and / or the capping layer are made of a dielectric material such as an oxide.

[0030] A dielectric material such as silicon dioxide or silicon nitride is a suitable material for keeping the overall manufacturing process simple while achieving electrical insulation. Furthermore, the insulating layer and the capping layer can be made of the same material.

[0031] In some embodiments, a first one of the sub-layers is made of a material based on a tetraethoxysilane (TEOS) precursor and a second one of the sub-layers is made of a material based on a silane precursor different from TEOS.

[0032] In order to obtain sub-layers with different types and / or values of internal stress, the sub-layers can be formed from different precursors. For example, a first one of the sub-layers is formed from a TEOS precursor and a second one of the sub-layers is formed from a different silane precursor.

[0033] In some embodiments, a metallization layer and a redistribution layer are arranged between the insulating layer and the capping layer.

[0034] This object is also solved by a semiconductor device comprising an open TSV according to one of the above embodiments. The semiconductor device can be any type of device that employs an open TSV to provide electrical connections through a substrate of an integrated circuit. Examples of such devices include ASICs that are commonly used in sensors, such as environmental sensors and image sensors.

[0035] The object is also solved by a method of manufacturing an open substrate through via TSV, wherein the method comprises providing a substantially planar substrate body comprising a semiconductor portion and an interlayer dielectric portion arranged adjacent to the semiconductor portion, wherein the semiconductor portion has a surface. The method further comprises forming a trench extending at least through the semiconductor portion from the surface and characterized by a sidewall and a bottom wall, depositing an insulating layer onto at least a portion of the sidewall and onto at least a portion of the surface, and depositing a metallization layer onto at least a portion of the insulating layer arranged adjacent to the sidewall and onto at least a portion of the bottom wall. The method further comprises depositing a redistribution layer onto at least a portion of the metallization layer and onto at least a portion of the insulating layer arranged adjacent to the surface. The method further comprises depositing a capping layer onto at least a portion of the metallization layer and onto at least a portion of the redistribution layer. The insulating layer and / or the capping layer are deposited as sub-layers differing from each other in material properties. A first one of the sub-layers is deposited adjacent to at least a portion of the sidewall and to at least a portion of the surface. A second one of the sub-layers is deposited adjacent to at least a portion of the surface.

[0036] Further embodiments of the method according to the above described embodiments of the open substrate through via become apparent to the skilled person.

[0037] The following description of the drawings of the exemplary embodiments can further illustrate and explain aspects of the improved concept. Components and parts of the open TSV having the same structure and the same effect are denoted by equivalent reference signs, respectively. As far as components and parts of the open TSV in different figures correspond to each other in their function, their description is not repeated for each of the following figures.

[0038] Figures 1 to 3 A cross-sectional view of an exemplary embodiment of an open TSV according to the improved concept is shown.

[0039] Figure 1 An exemplary embodiment of an open TSV 1 according to the improved concept is shown. In the present embodiment, the insulating layer 20 comprises a first sub-layer 21 and a second sub-layer 22.

[0040] In detail, the shown embodiment comprises a substrate body 10 having a semiconductor portion 11 and an interlayer dielectric portion 12. For example, the semiconductor portion 11 is a silicon substrate. The semiconductor portion 11 comprises a surface 13 arranged at a side of the semiconductor portion 11 facing away from the interlayer dielectric portion 12. For example, the surface 13 is a processed surface such as a polished surface. Generally, this surface 13 is referred to as backside of the semiconductor portion 11.

[0041] The interlayer dielectric portion 12 is arranged adjacent to another surface of the semiconductor portion 11 facing away from the surface 13, which is typically a processed surface referred to as the top surface of the semiconductor portion 11. For example, the interlayer dielectric portion 12 is arranged in close proximity to the semiconductor portion 11, i.e. the interlayer dielectric portion 12 is in direct contact with the semiconductor portion 11. For example, the interlayer dielectric portion 12 comprises metal contact layers 60 which are insulated from each other by an interlayer dielectric such as an oxide and form active circuitry of an integrated circuit. For illustration purposes, Figure 1 Only a single contact layer 60 is shown.

[0042] The TSV 1 further comprises a trench 14 which extends at least through the semiconductor portion 11 from the surface 13 and, optionally, as shown here, partially through the interlayer dielectric portion 12. The trench 14 is characterized by a vertically, i.e. in a direction perpendicular to the surface 13, extending sidewall 15 and a horizontally, i.e. in a direction parallel to the surface 13, extending bottom wall 16. The trench 14 can be configured to expose a contact surface of a contact layer 60 arranged within the interlayer dielectric layer 12.

[0043] The surface 13 and the sidewall 15 are covered by an insulating layer 20. To this end, in the present embodiment, the insulating layer 20 comprises sub-layers 21, 22 which can be referred to as a first insulating sub-layer and a second insulating sub-layer. The first one 21 of the sub-layers in the present embodiment is a conformal layer extending into the trench 14, i.e. it covers at least portions of the surface 13 and the sidewall 15 with substantially uniform thickness. The thickness is measured in a direction perpendicular to the surface 13 and the sidewall 15. The second one 22 of the sub-layers in the present embodiment is a non-conformal layer, i.e. it covers at least portions of the surface 13 without extending into the trench 14.

[0044] The first one 21 of the sub-layers and the second one 22 of the sub-layers differ from each other in material properties such as internal stress. For example, the first one 21 of the sub-layers is based on a tetraethoxysilane (TEOS) precursor while the second one 22 of the sub-layers is based on a different silane precursor. In this way, the first one 21 of the sub-layers can be characterized by a certain internal stress while the internal stress of the second one 22 of the sub-layers is greater than the internal stress of the first one 21 of the sub-layers. Thus, the overall internal stress within the trench 14 is limited to a level at which cracking probability is not significant. Outside the trench 14, the second one 22 of the sub-layers in the present embodiment serves to compensate for internal stress formed within or across the substrate body 10 and the remaining layers 30, 40, 50. As the sub-layers 21, 22 have significantly different etch rates, they can be distinguished and / or identified by short hydrofluoric acid etching.

[0045] The insulating layer 20 in this embodiment is arranged immediately adjacent to the substrate body 10. In alternative embodiments, an additional layer can be arranged between the insulating layer 20 and the substrate body 10. Examples of such additional layers include an adhesion promoting layer. Furthermore, in alternative embodiments, the first layer 21 of the sub-layers can be a non-conformal layer, while the second layer 22 of the sub-layers can be a conformal layer extending into the trench 14.

[0046] The insulating layer 20 is covered by a metallization layer 30 and a redistribution layer 40. The metallization layer 30 is configured to cover at least parts of the insulating layer 20 arranged adjacent to the side wall 15 and to the bottom wall 16. Optionally, the metallization layer 30 is arranged immediately adjacent to, i.e. in contact with, the contact layer 60. The redistribution layer 40 is configured to cover at least parts of the metallization layer 30 and at least parts of the insulating layer 20 arranged adjacent to the surface 13. In this embodiment, the metallization layer 30 is arranged immediately adjacent to the bottom wall 16 and the insulating layer 20, i.e. the first layer 21 of the sub-layers. In alternative embodiments not shown, an additional layer can be arranged between the insulating layer 20 and the metallization layer 30.

[0047] The redistribution layer 40 is arranged immediately adjacent to the metallization layer 30, i.e. the layers are in direct contact with each other. To this end, the redistribution layer extends at least partially into the trench 14. The metallization layer 30 and the redistribution layer 40 are electrically conductive materials, such as metals. For example, the metallization layer 30 and the redistribution layer 40 are the same material, such as tungsten. Likewise, the contact layer 60 is an electrically conductive material, such that the metallization layer 30 provides an electrically conductive connection between the contact layer 60 and the redistribution layer 40, which can be in electrical contact with the contact pad. Alternatively, the redistribution layer 40 can be at least partially exposed to form the contact pad.

[0048] A cover layer 50 is arranged adjacent to at least parts of the metallization layer 30 and to at least parts of the redistribution layer 40. The cover layer 50 can serve as a protective layer and / or for stress compensation and can be a semiconductor material, such as an oxide. For example, the material of the cover layer 50 corresponds to the material of the insulating layer 20. In this embodiment, the cover layer 50 is arranged immediately adjacent to the metallization layer 30 and to the redistribution layer 40. In alternative embodiments not shown, an additional layer can be arranged between the cover layer 50 and the metallization layer 30 and the redistribution layer 40.

[0049] The internal stresses in the first layer 21 and the second layer 22 of the sublayer are selected to prevent overall strain in TSV 1. For example, the internal stress of the first layer 21 is selected such that the total stress generated by all layers 20, 30, 40, and 50 within the substrate body 10 and trench 14 is substantially zero. The metallization layer 30, for example, has tensile stress (typical for tungsten), such that the material of the first layer 21 of the sublayer is selected to have internal stresses of substantially the same magnitude but compressive. To compensate for the overall compressive or tensile stress, the second layer 22 of the sublayer is therefore selected to have the stress required for the desired compensation. For example, the internal stress of the second layer 22 of the sublayer is compressive or tensile, and its magnitude is greater than that of the internal stress of the first layer 21 of the sublayer. For example, the internal stress is controlled during the deposition of the respective sublayer.

[0050] Figure 2 An alternative exemplary embodiment of the open TSV 1 is shown. In this embodiment, the insulating layer 20 is a single layer extending into the trench 14 to cover both the surface 13 and the sidewall 15. For example, the insulating layer 20 in this embodiment is a conformal layer. However, the thickness of the portion of the insulating layer 20 disposed adjacent to the surface 13 may differ from the thickness of the portion of the insulating layer 20 disposed adjacent to the sidewall 15. For example, the latter may be less thick than the former, so that the total stress within the trench 14 remains at a low level.

[0051] and Figure 1 Compared to the illustrated embodiment, in this embodiment, the cover layer 50 includes sublayers 51 and 52. Figure 1 Similar to other embodiments, in this embodiment, the first layer 51 of the sublayer, which may be referred to as the first cover sublayer, is a conformal layer that covers the surface 13 and extends into the trench 14 to cover the sidewalls 15 and the bottom wall 16. In this embodiment, the first layer 51 of the sublayer is disposed adjacent to the redistribution layer 40 and the metallization layer 30. In an alternative embodiment not shown, additional layers may be arranged between the layers.

[0052] In this embodiment, the second layer 52, which may be referred to as the second cover sublayer, is a non-conformal layer that covers the surface 13 but does not extend into the trench 14. In this embodiment, the second layer 52 is disposed adjacent to the first layer 51 in the sublayer. In an alternative embodiment not shown, the second layer 52 may be arranged between the redistribution layer 40 and the first layer 51 in the sublayer. In other words, in the alternative embodiment, the layer closest to the surface 13 in the sublayer may be a non-conformal layer, while the corresponding other sublayer in the sublayer is a conformal layer.

[0053] In this embodiment, similar to Figure 1 In the illustrated embodiment, sublayers 21 and 22, and sublayers 51 and 52 of the cover layer 50, serve the purpose of stress compensation. For example, similar to... Figure 1In the illustrated embodiment, the first layer 51 in the sub-layers is based on a TEOS precursor, while the second layer 52 in the sub-layers is based on a different silane precursor. In this embodiment, the material of the cap layer 50 corresponds for example to the material of the insulating layer 20.

[0054] Figure 3 An alternative exemplary embodiment of the open TSV 1 is shown. This embodiment combines Figure 1 and Figure 2 the sub-layer options of the embodiments shown in Figs. 1 to 6. In detail, both the insulating layer 20 and the cap layer 50 comprise sub-layers 21, 22, 51, 52 according to the embodiments described above. Forming both the insulating layer 20 and the cap layer 50 from the sub-layers 21, 22, 51, 52 can serve the purpose of compensating for the considerable overall stress formed by the substrate body 10 and the remaining layers 30, 40.

[0055] For example, the material of the first cap sub-layer 51 corresponds to the material of the first insulating sub-layer 21, while the material of the second cap sub-layer 52 corresponds to the material of the second insulating sub-layer 22. Alternatively, all sub-layers 21, 22, 51, 52 are different materials based for example on different precursors.

[0056] As described above, Figures 1 to 3 The embodiments shown in Figs. 1 to 6 represent exemplary embodiments of the TSV 1, and thus they do not constitute a complete list of all embodiments according to the improved concept. For example, actual TSV constructions can differ in shape, size and material from the illustrated embodiments.

[0057] The TSV 1 according to one of the illustrated embodiments can be conveniently used in semiconductor devices that require a low level of overall stress to prevent cracking caused by the strain formed by said stress. Possible applications include semiconductor devices in which a TSV according to the improved concept is employed to provide an electrical connection of an integrated circuit through a substrate. Examples of such devices include ASICs that are commonly used in sensors such as environmental sensors and image sensors.

[0058] Reference signs

[0059] 1 TSV

[0060] 10 Substrate body

[0061] 11 Semiconductor portion

[0062] 12 Interlayer dielectric portion

[0063] 13 Surface

[0064] 14 Trench

[0065] 15 Side wall

[0066] 16 Bottom wall

[0067] 20 insulating layer

[0068] 21 first insulating sublayer

[0069] 22 second insulating sublayer

[0070] 30 metallization layer

[0071] 40 redistribution layer

[0072] 50 capping layer

[0073] 51 first capping sublayer

[0074] 52 second capping sublayer

[0075] 60 contact layer

Claims

1. An open substrate via (1) TSV, the substrate via (1) comprising - a substantially planar substrate body (10) comprising a semiconductor portion (11) having a surface (13) and an interlayer dielectric portion (12) arranged adjacent to the semiconductor portion (11); - a trench (14) extending at least through the semiconductor portion (11) from the surface (13), the trench (14) being characterized by a side wall (15) and a bottom wall (16); - an insulating layer (20) arranged adjacent to at least a portion of the side wall (15) and to the surface (13); - a metallization layer (30) arranged adjacent to at least a portion of the insulating layer (20) and to at least a portion of the bottom wall (16); - a redistribution layer (40) arranged adjacent to at least a portion of the metallization layer (30) and to a portion of the insulating layer (20) arranged adjacent to the surface (13); and - a capping layer (50) arranged adjacent to at least a portion of the metallization layer (30) and to at least a portion of the redistribution layer (40); wherein - the capping layer (50) comprises a first capping sublayer (51) and a second capping sublayer (52) which differ from each other in terms of material properties; - the first capping sublayer (51) is arranged adjacent to at least a portion of the side wall (15) and to at least a portion of the surface (13); - the second capping sublayer (52) is arranged adjacent to at least a portion of the surface (13); - the first capping sublayer (51) has an internal stress of tensile or compressive type; and - the second capping sublayer (52) has an internal stress of the other type or of the same type but different size with respect to the first capping sublayer (51).

2. The open TSV (1) according to claim 1, wherein the insulating layer (20) comprises a first and a second insulating sublayer (21, 22), wherein - the first insulating sublayer (21) is arranged adjacent to at least a portion of the side wall (15) and to at least a portion of the surface (13); and - the second insulating sublayer (22) is arranged immediately adjacent to the first insulating sublayer (21) and to at least a portion of the surface (13).

3. The open TSV (1) according to claim 2, wherein the first insulating sublayer (21) and / or the first capping sublayer (51) is a conformal layer, while the second insulating sublayer (22) and / or the second capping sublayer (52) is a non-conformal layer.

4. The open TSV (1) according to claim 1 or 2, wherein the second capping sublayer (52) is arranged immediately adjacent to the first capping sublayer (51).

5. The open TSV (1) according to claim 2, wherein the first insulating sublayer (21) is arranged between the surface (13) and the second insulating sublayer (22), and / or the first capping sublayer (51) is arranged between the surface (13) and the second capping sublayer (52).

6. The open TSV (1) according to claim 2, wherein the second insulating sublayer (22) is arranged between the surface (13) and the first insulating sublayer (21), and / or the second capping sublayer (52) is arranged between the surface (13) and the first capping sublayer (51).

7. The open TSV (1) according to claim 2, wherein - the first and second insulating sub-layers (21, 22) differ from each other in terms of internal stress, material composition and / or microstructure, and / or the first and second cover sub-layers (51, 52) differ from each other in terms of material composition and / or microstructure.

8. The open TSV (1) according to claim 1 or 2, wherein - the trench (14) extends at least partially into the dielectric portion (12).

9. The open TSV (1) according to claim 1 or 2, wherein - the insulating layer (20) and / or the cover layer (50) are made of a dielectric material.

10. Open TSV (1) according to claim 2, wherein - the first insulating sub-layer (21) and / or the first cover sub-layer (51) are made of a material based on a tetraethoxysilane, TEOS, precursor; and - the second insulating sub-layer (22) and / or the second cover sub-layer (52) are made of a material based on a silane precursor different from TEOS.

11. The open TSV (1) according to claim 1 or 2, wherein - the metallization layer (30) and the redistribution layer (40) are arranged between the insulating layer (20) and the cover layer (50).

12. The open TSV (1) according to claim 2, wherein - the second insulating sub-layer (22) and / or the second cover sub-layer (52) do not extend into the trench (14).

13. The open TSV (1) according to claim 2, wherein, - the second insulating sub-layer (22) is arranged on the first insulating sub-layer (21), and / or the second cover sub-layer (52) is arranged on the first cover sub-layer (51).

14. The open TSV (1) according to claim 2, wherein, - the first insulating sub-layer (21) is arranged on the second insulating sub-layer (22), and / or the first cover sub-layer (51) is arranged on the second cover sub-layer (52).

15. Open TSV (1) according to claim 1 or 2, wherein - the insulating layer (20) is arranged on at least part of the side wall (15) and on the surface (13); - the metallization layer (30) is arranged on the bottom wall (16) and on the insulating layer (20) within the trench (14); - the redistribution layer (40) is arranged on the insulating layer (20) outside the trench (14); and - the cover layer (50) is arranged on the metallization layer (30) and the redistribution layer (40).

16. A semiconductor device comprising an open TSV (1) according to claim 1 or 2.

17. A method for manufacturing an open substrate via (1) TSV, the method comprising - providing a substantially planar substrate body (10) comprising a semiconductor portion (11) having a surface (13) and an interlayer dielectric portion (12) arranged adjacent to the semiconductor portion (11); - forming a trench (14) extending at least through the semiconductor portion (11) from the surface (13) and characterized by a side wall (15) and a bottom wall (16); - depositing an insulating layer (20) on at least part of the side wall (15) and on at least part of the surface (13); - depositing a metallization layer (30) on at least part of the insulating layer (20) arranged adjacent to the side wall (15) and on at least part of the bottom wall (16); - depositing a redistribution layer (40) on at least part of the metallization layer (30) and on at least part of the insulating layer (20) arranged adjacent to the surface (13); and - depositing a cover layer (50) on at least part of the metallization layer (30) and on at least part of the redistribution layer (40); wherein - the cover layer (50) is deposited as a first cover sublayer (51) and a second cover sublayer (52) which differ from each other in terms of material properties; - the first cover sublayer (51) is deposited adjacent to at least part of the sidewall (15) and to at least part of the surface (13); - the second cover sublayer (52) is deposited adjacent to at least part of the surface (13); - the first cover sublayer (51) has an internal stress of tensile or compressive type; - the second cover sublayer (52) has an internal stress of the other corresponding type or of the same type but of different magnitude than the first cover sublayer (51).

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