Device and method for simulating chip thermal resistance

Abstract

The present application discloses a device and method for simulating the thermal resistance of a chip. The simulation device includes: a plurality of heaters and a heating integrated block, wherein the plurality of heaters are distributed in different areas of the heating integrated block and are used to adjust the thermal resistance value of the simulated chip; the heating integrated block is used to gather the heat generated by the plurality of heaters and conduct the heat generated by the plurality of heaters to the first heat conduction module. The present application solves the technical problem that the same device cannot be used to simulate the thermal resistance of different chips during the test system.

Description

Technical Field

[0001] The present application relates to the field of hardware system design, and in particular, to a device and method for simulating chip thermal resistance. Background Art

[0002] The core temperature (die temperature / junction temperature) of the chip can only be obtained through the chip's internal registers or proprietary circuits when the chip is working normally. If the chip is not working properly / not powered, or there is no chip (in the early stages of product development, there are no physical boards, or the project is large and the system heat dissipation needs to be evaluated in advance), only the chip's case temperature (case temperature) can be obtained. After obtaining the case temperature, the core temperature can be calculated using the thermal resistance formula provided by the chip manufacturer. Whether the chip can work normally is based on the core temperature. Because the thermal resistance of each chip is fixed after it is taped out, and it is difficult for the analog material to be completely consistent with the chip itself, it is difficult to obtain the core temperature of the chip using ordinary methods.

[0003] Since the thermal resistance of each chip is different, even if a large amount of manpower and material resources are spent to produce a simulated heat dissipation device, it cannot be reused and has a low cost-effectiveness.

[0004] Currently, no effective solution has been proposed to solve the problem that the same device cannot be used to simulate the thermal resistance of different chips during the system testing process. Summary of the invention

[0005] The embodiments of the present application provide a device and method for simulating the thermal resistance of a chip, so as to at least solve the technical problem that the same device cannot be used to simulate the thermal resistance of different chips during the test system.

[0006] According to one aspect of an embodiment of the present application, a device for simulating chip thermal resistance is provided, comprising: a plurality of heaters and a heating integrated block, wherein the plurality of heaters are distributed in different areas of the heating integrated block and are used to adjust the thermal resistance value of the simulated chip; the heating integrated block is used to gather the heat generated by the plurality of heaters and conduct the heat generated by the plurality of heaters to a first thermal conduction module.

[0007] Optionally, the device also includes: a first temperature sensor and a second temperature sensor, wherein the first temperature sensor is used to measure a first temperature of the simulated chip, wherein the first temperature is the core temperature of the simulated chip; and the second temperature sensor is used to measure a second temperature of the simulated chip, wherein the second temperature is the shell temperature of the simulated chip.

[0008] Optionally, the device also includes: a first heat conduction module and a second heat conduction module, wherein the first heat conduction module has the same size and material as the simulated chip and is used to simulate the heat conduction to the chip shell; the second heat conduction module is used to simulate the heat conduction to the circuit board where the chip is located.

[0009] Optionally, the plurality of heaters and the first temperature sensor are arranged between the first heat conducting module and the second heat conducting module; and the second temperature sensor is arranged outside the first heat conducting module.

[0010] Optionally, the device further includes: a heating integrated block, wherein the plurality of heaters are distributed in different areas of the heating integrated block, and the heating integrated block is used to gather the heat generated by the plurality of heaters and conduct the heat generated by the plurality of heaters to the first heat conduction module.

[0011] Optionally, the device further includes: a controller connected to the plurality of heaters, and configured to control the plurality of heaters to operate at different powers according to the model of the simulated chip.

[0012] Optionally, the total power of the plurality of heaters is the same as the power of the simulated chip.

[0013] Optionally, the device further comprises: an opening fixture for fixing a plurality of heaters, a heating integrated block, a first temperature sensor and a second temperature sensor.

[0014] According to another aspect of an embodiment of the present application, a method for simulating chip thermal resistance is also provided, including: determining the thermal resistance value of the chip; and controlling multiple heaters to operate at different powers according to the thermal resistance value.

[0015] According to another aspect of an embodiment of the present invention, a storage medium is further provided. The storage medium includes a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute the above chip thermal resistance simulation method.

[0016] According to another aspect of an embodiment of the present invention, a processor is further provided. The processor is used to run a program, wherein the above chip thermal resistance simulation method is executed when the program is run.

[0017] In an embodiment of the present application, a chip thermal resistance simulation device is used, including: multiple heaters and a heating integrated block, wherein the multiple heaters are distributed in different areas of the heating integrated block, and are used to adjust the thermal resistance value of the simulated chip; the heating integrated block is used to gather the heat generated by the multiple heaters, and conduct the heat generated by the multiple heaters to the first thermal conduction module, and by changing the power distribution of the heater, the purpose of simulating the thermal resistance change of the chip is achieved, thereby achieving the technical effect of using the same set of products to simulate the heating conditions of different chips, thereby solving the technical problem of not being able to use the same device to simulate the thermal resistance of different chips during the test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 It is a structural block diagram of a chip thermal resistance simulation device according to the related art;

[0020] Figure 2 is a structural block diagram of another chip thermal resistance simulation device according to an embodiment of the present application;

[0021] Figure 3 is a structural block diagram of another chip thermal resistance simulation device according to an embodiment of the present application;

[0022] Figure 4 It is a flow chart of a method for simulating chip thermal resistance according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] According to an embodiment of the present application, an embodiment of a method for simulating chip thermal resistance is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0026] Figure 1 is a structural block diagram of a chip thermal resistance simulation device according to an embodiment of the present application, such as Figure 1 As shown, the simulation device includes:

[0027] A plurality of heaters 10 are distributed in different areas of the heating integrated block 11 and are used to adjust the thermal resistance value of the simulated chip;

[0028] The heater is a heat source, and the material used can be a cheap ceramic heater or a reduced integrated heating module. The heater is used to generate heat for the chip under different working conditions and can be controlled by a controller. If the accuracy requirement is not high, a cheap ceramic heater can be selected. Considering the labor and equipment costs, after using the method of this application, the cost can be reduced by more than 90% relative to the calculation simulation method. Using multiple heaters 10 to replace the actual chip heating conditions can verify the feasibility of system heat dissipation in advance at a low cost.

[0029] The heater has a simple structure, low cost, and fixed thermal resistance. By using multiple heaters 10, the thermal resistance can be adjusted as needed. Since the power consumption and thermal resistance of various chips are different, this application uses the same set of products to truly simulate the heating conditions of different chips. By using multiple heaters 10 to simulate the thermal resistance value of the chip to achieve a variable thermal resistance simulation solution, this application can be applied to the heat dissipation simulation of complex communication systems.

[0030] The heating integrated block 11 is used to gather the heat generated by the multiple heaters 10 and conduct the heat generated by the multiple heaters 10 to the first heat conduction module;

[0031] Multiple heaters 10 are distributed on the heating integrated block 11. The heating integrated block 11 can be made of materials with different thermal conductivity such as silver, copper, and aluminum, which are used to gather the heat generated by the multiple heaters 10 and conduct it to the first heat conduction module, that is, the outer shell surface of the simulated chip. Depending on the simulated chip, the thickness and material of the heating integrated block 11 are different. In order to keep the thickness of the simulated device the same as that of the final chip, it is necessary to select a suitable material and thickness. The replaceable and variable thickness heating integrated block 11 is convenient for simulating chips of various thicknesses.

[0032] Through the above-mentioned simulation device, by changing the power distribution of the heater, the purpose of simulating the change of thermal resistance of the chip is achieved, thereby realizing the technical effect of simulating the heating conditions of different chips using the same set of products.

[0033] Figure 2 is a structural block diagram of another chip thermal resistance simulation device according to an embodiment of the present application, such as Figure 2 As shown, the device also includes: a first temperature sensor 12 and a second temperature sensor 13, wherein the first temperature sensor 12 is used to measure a first temperature of the simulated chip, wherein the first temperature is the core temperature of the simulated chip; the second temperature sensor 13 is used to measure a second temperature of the simulated chip, wherein the second temperature is the shell temperature of the simulated chip.

[0034] The first temperature of the chip refers to the junction temperature of the chip, that is, the core temperature of the chip, so the first temperature sensor 12 reflects the core temperature of the chip. The second temperature refers to the shell temperature of the chip, that is, the shell temperature of the chip, so the second temperature sensor 13 reflects the shell temperature of the chip. The thermal resistance of the chip to be simulated is given by the manufacturer. The present application can accurately measure the core temperature of the chip by adjusting the thermal resistance.

[0035] Figure 3 is a structural block diagram of another chip thermal resistance simulation device according to an embodiment of the present application, such as Figure 3 As shown, the device also includes: a first heat conducting module 14 and a second heat conducting module 15, wherein the first heat conducting module 14 has the same size and material as the simulated chip and is used to simulate the heat conduction to the chip shell; the second heat conducting module 15 is used to simulate the heat conduction to the circuit board where the chip is located.

[0036] The first heat conduction module 14 has the same size and material as the simulated chip, and is used to simulate the heat conduction to the outer shell of the chip. The module is replaceable and can be changed in size, which can facilitate the simulation of chips of various sizes. The second heat conduction module 15 is used to simulate the heat conduction to the PCB board where the chip is located. If the cost is sensitive and the test accuracy requirements are not high, this module can be omitted. The module is also replaceable and the thickness can be changed to facilitate the simulation of chips of various thicknesses.

[0037] According to another optional embodiment of the present application, the plurality of heaters 10 and the first temperature sensor 12 are disposed between the first heat conducting module 14 and the second heat conducting module 15 ; and the second temperature sensor 13 is disposed outside the first heat conducting module 14 .

[0038] The plurality of heaters 10 and the first temperature sensor 12 are located between the first heat conducting module 14 and the second heat conducting module 15 , and the second temperature sensor 13 is located outside the first heat conducting module 14 , that is, the outer shell surface of the simulated chip.

[0039] In some other optional embodiments of the present application, the above-mentioned device also includes: a controller, connected to the multiple heaters 10, and used to control the multiple heaters 10 to operate at different powers according to the model of the simulated chip.

[0040] The heating power of the heaters is different and is controlled by the controller. The controller is connected to a plurality of heaters 10. By controlling the controller, the plurality of heaters 10 can be controlled to work at different powers. The power is determined by the model of the simulated chip. After the user selects the chip model, the thermal resistance value data of the chip will be sent to the controller. The controller dynamically configures the power distribution of the heater according to the received thermal resistance data. For example, when the power of the heater is reduced, the temperature of the first temperature sensor 12 will drop, which is equivalent to a smaller thermal resistance value, and vice versa. Thus, the power of the heater can be controlled by the difference in thermal resistance value, so that the heat generated by the heater can be dynamically changed and controllable, thereby simulating the thermal resistance value of the chip to measure the core temperature of the chip.

[0041] By changing the power distribution of the heater, the thermal resistance of the simulated chip can be changed. For a given chip, the thermal resistance is fixed. The main purpose of this application is to simulate different chips with the same set of products. Through this simulated chip, the temperature range that can be tolerated is wider, and system limit testing can be done more easily.

[0042] According to an optional embodiment of the present application, the total power of the plurality of heaters 10 is the same as the power of the simulated chip.

[0043] The total power of the plurality of heaters 10 is the same as the power of the analog chip.

[0044] According to another optional embodiment of the present application, the above-mentioned device also includes: an opening fixture for fixing the plurality of heaters 10 , the heating integrated block 11 , the first temperature sensor 12 and the second temperature sensor 13 .

[0045] When the cost is sensitive, fewer heaters are used, and the positions of the heating integrated block 11, the multiple heaters 10 and the first temperature sensor 12 are fixed by an open-hole fixture; when the cost is not sensitive, the heaters can be arranged in an array. By using array-controllable heaters, it is convenient and simple to simulate chips with more thermal resistance parameters.

[0046] This application uses the same set of products to simulate chips of different sizes, thicknesses, power consumption and thermal resistances, and can simulate the heating conditions of the chip under different working conditions (different chip loads). At the same time, this application uses template technology, so that users do not need to fully understand the working principle of the chip, but only need to clarify the chip model to complete the test task, which is convenient for users to adjust. The heat dissipation of existing system products needs to be precisely designed to ensure the normal operation of the system. Since the heat generation data of the chip cannot be obtained, a lot of system power will be wasted. Through this application, the heat dissipation control of the system can be more precise, and the heat dissipation system design can be more precise.

[0047] Figure 4 is a flow chart of a chip thermal resistance simulation method according to an embodiment of the present application, such as Figure 4 As shown, the method comprises the following steps:

[0048] Step S402, determining the thermal resistance value of the simulated chip;

[0049] In this step, by using template technology, users do not need to fully understand the working principle of the chip, but only need to clarify the chip model to complete the test task, which is convenient for users to adjust. Through the chip model, you can know the thermal resistance value of the simulated chip. For a given chip, the thermal resistance value is fixed. The main purpose of this application is to simulate different chips with the same set of products. Through this simulated chip, the temperature range that can be tolerated is wider, and system limit testing can be done more easily.

[0050] Step S404, controlling the plurality of heaters to operate at different powers according to the thermal resistance values;

[0051] In this step, the thermal resistance of the simulated chip is changed by changing the power distribution of the heater. By using the above products, chips of different sizes, thicknesses, power consumption and thermal resistance can be simulated, and the heating conditions of the chip under different working conditions (different chip loads) can be simulated.

[0052] This application uses a distributed controllable heat source to achieve adjustable thermal resistance from the chip core temperature to the chip shell temperature, which is used to simulate the heating condition of a real chip. Through this simulation device, the core temperature of the chip can be quickly and accurately obtained without complex calculations. Using this simulation device, the heating state of the chip when working can be fully simulated, and the final heat dissipation result of the system can be quickly obtained to ensure that the final system can meet the operating temperature requirements of the chip.

[0053] It should be noted that Figure 4 The preferred implementation of the illustrated embodiment can be found in Figure 1 The relevant description of the illustrated embodiment will not be repeated here.

[0054] According to another aspect of the embodiment of the present application, a non-volatile storage medium is provided, the non-volatile storage medium includes a stored program, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute the above chip thermal resistance simulation method.

[0055] The non-volatile storage medium is used to store a program for executing the following functions: determining the thermal resistance value of the simulated chip; and controlling a plurality of heaters to operate at different powers according to the thermal resistance value.

[0056] An embodiment of the present application further provides a processor, which is used to run a program stored in a memory, wherein the above chip thermal resistance simulation method is executed when the program is running.

[0057] The processor is used to run a program that performs the following functions: determining the thermal resistance value of the simulated chip; and controlling a plurality of heaters to operate at different powers according to the thermal resistance value.

[0058] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0059] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0060] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0061] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0062] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0063] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0064] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip thermal resistance simulation device, characterized in that: include: Multiple heaters and heating integrated blocks, among which, The plurality of heaters are distributed in different areas of the heating integrated block, and are used to adjust the thermal resistance value of the simulated chip, and control the plurality of heaters to work at different powers according to the thermal resistance value; The heating integrated block is used to gather the heat generated by the multiple heaters and conduct the heat generated by the multiple heaters to the first heat conduction module; The device further comprises: a first temperature sensor and a second temperature sensor, wherein: The first temperature sensor is used to measure a simulated first temperature of the chip, wherein the first temperature is a simulated core temperature of the chip; The second temperature sensor is used to measure a simulated second temperature of the chip, wherein the second temperature is a simulated temperature of a shell of the chip.

2. The device according to claim 1, characterized in that The device further comprises: the first heat conduction module and the second heat conduction module, wherein: The first heat conduction module has the same size and material as the simulated chip and is used to simulate the heat conduction to the shell of the chip; The second heat conduction module is used to simulate heat conduction to the circuit board where the chip is located.

3. The device according to claim 2, characterized in that The plurality of heaters and the first temperature sensor are arranged between the first heat conducting module and the second heat conducting module; The second temperature sensor is arranged outside the first heat conduction module.

4. The device according to any one of claims 1 to 3, characterized in that The device also includes: The controller is connected to the plurality of heaters and is used for controlling the plurality of heaters to operate at different powers according to the model of the simulated chip.

5. The device according to claim 1, characterized in that The total power of the plurality of heaters is the same as the power of the simulated chip.

6. The device according to claim 1, characterized in that The device also includes: The opening fixture is used to fix the multiple heaters, the heating integrated block, the first temperature sensor and the second temperature sensor.

7. A method for simulating chip thermal resistance, characterized in that: The method is applied to the chip thermal resistance simulation device according to any one of claims 1 to 6, comprising: Determine the thermal resistance value of the simulated chip; The plurality of heaters are controlled to operate at different powers according to the thermal resistance values.

8. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored program, wherein when the program is executed, the device where the non-volatile storage medium is located is controlled to execute the chip thermal resistance simulation method according to claim 7.

9. A processor, characterized in that: The processor is used to run a program stored in the memory, wherein the chip thermal resistance simulation method according to claim 7 is executed when the program is run.

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