Data Loading Method, Apparatus, Electronic Device, and Storage Medium

Abstract

An embodiment of the present invention provides a data loading method, apparatus, electronic device, and storage medium. In this method, based on the loadable information of the immediate number loading instruction under the target architecture, the data to be loaded is divided into n parts to obtain n sub-data to be loaded, and one sub-data to be loaded corresponds to one immediate number loading instruction. The target architecture is the instruction set architecture adopted by the electronic device. Based on the immediate number loading instruction corresponding to the sub-data to be loaded, the sub-data to be loaded is loaded into the corresponding bit field of the specified register; the length of the specified register is not less than the length of the data to be loaded. In the embodiment of the present invention, by dividing the data to be loaded into multiple sub-data to be loaded and using the corresponding multiple immediate number loading instructions to load the sub-data to be loaded respectively, the loading operation of the data to be loaded is realized. In this way, to a certain extent, when the data to be loaded is relatively long, it can be ensured that the data can be successfully loaded into the specified register.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a data loading method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, the instructions for implementing processing functions in an electronic device include the data to be processed, and the length of such instructions is often limited. Correspondingly, the number of bits available for representing the data value to be processed is also limited. For example, for data processing instructions such as data transfer instructions, data arithmetic and logical operation instructions, and data comparison instructions, in addition to including the data to be processed, these data processing instructions also need to include information such as the operation code and destination register of the instruction. Correspondingly, in data processing instructions, the number of bits available for representing the data to be processed is often limited.

[0003] In the related art, the data to be processed is often long. Therefore, how to load the data to be processed into a register has become a technical problem that urgently needs to be solved. Summary of the Invention

[0004] The present invention provides a data loading method, apparatus, electronic device, and storage medium for data loading.

[0005] In a first aspect, the present invention provides a data loading method, the method comprising:

[0006] Dividing the data to be loaded into n parts based on the loadable information of the immediate value load instruction under the target architecture, to obtain n sub-data to be loaded; one of the sub-data to be loaded corresponds to one of the immediate value load instructions, and the target architecture is the instruction set architecture adopted by the electronic device;

[0007] Loading the sub-data to be loaded into the corresponding bit field of the specified register based on the immediate value load instruction corresponding to the sub-data to be loaded; the length of the specified register is not less than the length of the data to be loaded.

[0008] In a second aspect, the present invention provides a data loading apparatus, the apparatus comprising:

[0009] A dividing module, configured to divide the data to be loaded into n parts based on the loadable information of the immediate value load instruction under the target architecture, to obtain n sub-data to be loaded; one of the sub-data to be loaded corresponds to one of the immediate value load instructions, and the target architecture is the instruction set architecture adopted by the electronic device;

[0010] A loading module, configured to load the sub-data to be loaded into the corresponding bit field of the specified register based on the immediate value load instruction corresponding to the sub-data to be loaded; the length of the specified register is not less than the length of the data to be loaded.

[0011] In a third aspect, the present invention provides an electronic device, including: a processor, a memory, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the above-mentioned method is implemented.

[0012] In a fourth aspect, the present invention provides a readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, enabling the electronic device to execute the above-mentioned method.

[0013] A data loading method provided by an embodiment of the present invention divides to-be-loaded data into n parts based on the loadable information of an immediate value load instruction under a target architecture, obtaining n to-be-loaded sub-data, where one to-be-loaded sub-data corresponds to one immediate value load instruction, and the target architecture is the instruction system architecture adopted by the electronic device. Based on the immediate value load instruction corresponding to the to-be-loaded sub-data, the to-be-loaded sub-data is loaded into a corresponding bit field of a specified register; the length of the specified register is not less than the length of the to-be-loaded data. In the embodiment of the present invention, by dividing the to-be-loaded data into multiple to-be-loaded sub-data and loading the to-be-loaded sub-data respectively with corresponding multiple immediate value load instructions, the loading operation of the to-be-loaded data is realized. In this way, to a certain extent, when the to-be-loaded data is relatively long, it can be ensured that the data can be successfully loaded into the specified register. Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0015] Figure 1 is a flowchart of the steps of a data loading method provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a loading process provided by an embodiment of the present invention;

[0017] Figure 3 is a block diagram of the structure of an embodiment of a data loading device of the present invention;

[0018] Figure 4 is a block diagram of the structure of an electronic device shown according to an exemplary embodiment. Detailed Embodiments

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] Figure 1 is a step flowchart of a data loading method provided by an embodiment of the present invention. This method can be applied to an electronic device, such as Figure 1 as shown, the method may include:

[0021] Step 101: Divide the data to be loaded into n parts based on the loadable information of the immediate number load instruction under the target architecture, to obtain n sub-data to be loaded; one of the sub-data to be loaded corresponds to one of the immediate number load instructions, and the target architecture is the instruction system architecture adopted by the electronic device.

[0022] In an embodiment of the present invention, the instruction set architecture adopted by the electronic device can be set based on actual requirements. For example, the instruction set architecture adopted by the electronic device can be a Reduced Instruction Set Computer (RISC) architecture (such as architectures like LoongArch). Instruction sets involved under different architectures may vary, that is, immediate value loading instructions available under different architectures are different. Further, immediate value loading instructions can be used to load data into registers, and the lengths of data that different immediate value loading instructions can load and the data bit fields that can be loaded may vary. Among them, the data bit fields that an immediate value loading instruction can load are used to represent which bit fields in the register the data can be loaded into. Further, immediate value loading instructions can be used to load the data in the to-be-loaded data corresponding to the data bit fields that can be loaded into the corresponding bit fields. The bit fields in the register represent the positions where relevant data is stored in the register, and this position can be identified by a single address or by an address segment. For example, assume that immediate value loading instruction A can be used to load 8-bit data into the lower 8 bits of the register, and immediate value loading instruction B can be used to load 8-bit data into the upper 8 bits of the register. That is to say, the lengths of data that immediate value loading instruction A and immediate value loading instruction B can load are 16. The data bit fields that immediate value loading instruction A can load are bits 0 to 7. Then, in an embodiment of the present invention, the data of bits 0 to 7 in the to-be-loaded data can be used as a to-be-loaded sub-data based on immediate value loading instruction A, and this to-be-loaded sub-data can be loaded into bits 0 to 7 of the specified register using immediate value loading instruction A. The data bit fields that immediate value loading instruction B can load are bits 8 to 15. Correspondingly, in an embodiment of the present invention, the data of bits 8 to 15 in the to-be-loaded data can be used as a to-be-loaded sub-data based on immediate value loading instruction B, and this to-be-loaded sub-data can be loaded into bits 8 to 15 of the specified register using immediate value loading instruction B.

[0023] Further, the to-be-loaded data can be the data to be processed that needs to be loaded into the specified register. The length of the to-be-loaded data may be relatively long. Therefore, in this step, dividing the to-be-loaded data into n to-be-loaded sub-data can reduce the length of the to-be-loaded sub-data, thus facilitating subsequent loading. Further, the lengths of each to-be-loaded sub-data and the data bit fields required to be loaded can match the lengths and the data bit fields that the corresponding immediate value loading instructions can load, so as to ensure normal subsequent loading.

[0024] Step 102: Based on the immediate value loading instruction corresponding to the to-be-loaded sub-data, load the to-be-loaded sub-data into the corresponding bit fields of the specified register; the length of the specified register is not less than the length of the to-be-loaded data.

[0025] In an embodiment of the present invention, the designated register may be a register for storing data to be processed. Further, the immediate number loading instruction corresponding to the sub-data to be loaded can be used to load each sub-data to be loaded into the corresponding bit field in the designated register, so as to load the data to be loaded into the designated register. Among them, the loading operation can also be regarded as a loading operation. The length of the designated register shall not be less than the length of the data to be loaded, so as to avoid overflow and ensure that the loading operation can proceed normally.

[0026] In summary, a data loading method provided by an embodiment of the present invention divides the data to be loaded into n parts based on the loadable information of the immediate number loading instruction under the target architecture, obtaining n sub-data to be loaded. One sub-data to be loaded corresponds to one immediate number loading instruction, and the target architecture is the instruction system architecture adopted by the electronic device. Based on the immediate number loading instruction corresponding to the sub-data to be loaded, the sub-data to be loaded is loaded into the corresponding bit field of the designated register; the length of the designated register is not less than the length of the data to be loaded. In an embodiment of the present invention, by dividing the data to be loaded into multiple sub-data to be loaded and using the corresponding multiple immediate number loading instructions to load the sub-data to be loaded respectively, the loading operation of the data to be loaded is realized. In this way, to a certain extent, when the data to be loaded is relatively long, it can be ensured that the data can be successfully loaded into the designated register.

[0027] Optionally, the loadable information in the embodiment of the present invention may include the data length and the loadable data bit field that can be loaded by the immediate number loading instruction. Correspondingly, the operation of dividing the data to be loaded into n parts based on the loadable information of the immediate number loading instruction under the target architecture may specifically include:

[0028] Step S21: Select n immediate number loading instructions from the immediate number loading instructions under the target architecture according to the data length and the loadable data bit field; the sum of the data lengths that can be loaded by the n immediate number loading instructions is equal to the length of the data to be loaded, and the loadable data bit fields corresponding to the n immediate number loading instructions are continuous.

[0029] In an embodiment of the present invention, the length of the data to be loaded can be regarded as the number of bits, and the type of the data to be loaded can be an integer. The data to be loaded can be composed of multiple 0s and 1s, and different compositions can represent different numerical values. Further, under the target architecture adopted by the electronic device, there can be sufficient available immediate number loading instructions. In this step, it is possible to perform permutations and combinations according to the data lengths and loadable data bit fields that can be loaded by the available immediate number loading instructions, and select a combination in which the sum of the data lengths that can be loaded by the included immediate number loading instructions is equal to the length of the data to be loaded and the corresponding loadable data bits are consecutive. The number of immediate number loading instructions included in this combination is the specific value of n, and the immediate number loading instructions included in this combination are the selected n immediate number loading instructions. Among them, the loadable data bit fields corresponding to the n immediate number loading instructions are consecutive and do not overlap.

[0030] For example, assuming that the data to be loaded is 32-bit data (bits 0 to 31), the selected n immediate number loading instructions may include: immediate number loading instruction C, immediate number loading instruction D, and immediate number loading instruction E. Among them, the data length that can be loaded by immediate number loading instruction C can be 16 bits, the data length that can be loaded by immediate number loading instruction D can be 7 bits, and the data length that can be loaded by immediate number loading instruction E can be 9 bits. In the order from the low bit to the high bit, the loadable data bit field of immediate number loading instruction C can be bits 0 to 15, the loadable data bit field of immediate number loading instruction D can be bits 16 to 22, and the loadable data bit field of immediate number loading instruction E can be bits 23 to 31.

[0031] Step S22: Divide the data to be loaded into n parts according to the selected n immediate number loading instructions.

[0032] In this step, for any one of the selected n immediate number loading instructions, the data in the bit field of the data to be loaded that matches the loadable data bit field corresponding to this immediate number loading instruction can be divided into one part to be used as the sub-data to be loaded corresponding to this immediate number loading instruction, so as to obtain n sub-data to be loaded.

[0033] For example, the data to be loaded can be represented as the following n parts:

[0034]

[0035] The specified register can be correspondingly represented as the following n bit fields:

[0036]

[0037] Further, based on these n immediate load instructions (li0, li1, …, lin-1), each part of the data to be loaded can be loaded into the corresponding bit field of the specified register. Wherein, each part of the data to be loaded can be used as a sub-data to be loaded, and the bit field occupied by the Xth part in the specified register can be the same as the bit field where the data in the Xth part of the data to be loaded is located. Assuming that the loadable data bit field corresponding to the immediate load instruction liX is the bit field occupied by the Xth part in the specified register, then the data in the Xth part of the data to be loaded is the data that matches the loadable data bit field corresponding to liX, and the Xth part of the data to be loaded is the sub-data to be loaded corresponding to liX. The value of X can be n-1, n-2, …, 0. For example, li0 can load the 0th part of the data to be loaded into the bit field occupied by the 0th part of the specified register, …, lin-1 can load the (n-1)th part of the data to be loaded into the bit field occupied by the (n-1)th part of the specified register. That is to say, by using n immediate load instructions to load the n parts of an integer into the corresponding bit fields of the register respectively, the loading operation can be completed.

[0038] Optionally, the operation of loading the sub-data to be loaded into the corresponding bit field of the specified register based on the immediate load instruction corresponding to the sub-data to be loaded may specifically include:

[0039] Step S31: Detect whether the sub-data to be loaded meets a preset ignoring condition; the ignoring condition includes: all the values in the sub-data to be loaded are the same and the value is the same as the sign bit value of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded.

[0040] In this step, the sub-data to be loaded can be a data string composed of 0 and / or 1, and all the values in the sub-data to be loaded being the same means that each bit of data in the sub-data to be loaded is the same.

[0041] Step S32: Use the sub-data to be loaded that does not meet the ignoring condition as the target sub-data, and based on the immediate load instruction corresponding to the target sub-data, load the target sub-data into the corresponding bit field of the specified register, and extend the current remaining high bits based on the sign bit value of the target sub-data.

[0042] In the embodiments of the present invention, since each sub-data to be loaded can determine the bit field corresponding to each sub-data to be loaded according to the immediate load instruction where it is located, and the bit fields corresponding to each sub-data to be loaded are continuous, therefore, the adjacent lower-order sub-data to be loaded can be understood as the next sub-data to be loaded adjacent to the sub-data to be loaded in the order from high to low. Specifically, the data arrangement can be that the number of bits decreases from high to low from left to right, or the number of bits decreases from high to low from right to left. The embodiments of the present invention do not limit this. The sign bit is the highest bit of the bit field where the sub-data to be loaded is located. As shown, the adjacent lower-order sub-data to be loaded represented by the (n - 1)th part can be the sub-data to be loaded represented by the (n - 2)th part, and the adjacent lower-order sub-data to be loaded represented by the (n - 2)th part can be the sub-data to be loaded represented by the (n - 3)th part. Since there is no adjacent lower-order sub-data for the lowest-order sub-data to be loaded, it can be directly determined that the lowest-order sub-data to be loaded does not meet the ignored condition.

[0043] Further, the immediate load instructions under the target architecture can all extend the immediate number, that is, perform sign extension. Correspondingly, when loading in the order from low to high, after loading any target sub-data, based on the value of the sign bit of the target sub-data, the current remaining high bits in the specified register can be sign-extended. It should be noted that in the case where the data arrangement is that the number of bits decreases from high to low from left to right, the current remaining high bits can be the idle bits on the left side of the target sub-data, and in the case where the data arrangement is that the number of bits decreases from high to low from right to left, the current remaining high bits can be the idle bits on the right side of the target sub-data. In one implementation, it can be loaded in the order from low to high in the data bit field. In this way, it can be ensured that after each target sub-data is loaded, the bits on the right / left side of the target sub-data are all idle and can be extended to the value of the sign bit, thereby increasing the probability that the sub-data to be loaded is the same as the extended value and minimizing the number of required load operations as much as possible.

[0044] Sign-extension is performed on the current remaining high bits in the specified register based on the value of the sign bit of the target sub-data. Specifically, the values of the current remaining high bits can be set to the value of the sign bit. That is, the remaining high bits in the specified register where data has not been loaded yet will be filled with the value of the sign bit. For example, when the value of the highest bit is 0, that is, this part of the sub-data to be loaded can be regarded as a positive number, the remaining high bits are all set to 0. On the contrary, when the value of the highest bit is 1, that is, this part of the sub-data to be loaded can be regarded as a negative number, the remaining high bits are all set to 1. It should be noted that the remaining high bits can also be default set to 0, that is, perform unsigned extension. Correspondingly, when all the values in the sub-data to be loaded are 0, it can be determined that the sub-data to be loaded meets the preset ignoring condition. When the values in the sub-data to be loaded are not all 0, it is determined that the sub-data to be loaded does not meet the preset ignoring condition. The embodiments of the present invention do not limit this.

[0045] Correspondingly, if the sub-data to be loaded meets the preset ignoring condition, it can be explained that the sub-data to be loaded is the same as the content after sign-extension in the specified register. Therefore, it can be considered that the immediate number load instructions corresponding to these sub-data to be loaded are not necessary to exist, and these sub-data to be loaded do not need to be loaded. These sub-data to be loaded can be ignored, and the load operation for these sub-data to be loaded is not performed. The immediate number load instructions corresponding to these sub-data to be loaded are omitted, and only the sub-data to be loaded that does not meet the ignoring condition is loaded and sign-extended at the same time. In this way, while ensuring that the content in the specified register is the same as the data to be loaded, unnecessary load operations can be avoided, thereby reducing the number of executed instructions, optimizing the load process, improving the load efficiency, and further improving the overall operation efficiency.

[0046] Exemplarily, assume that the data to be loaded is 1111111110000001, and the sub-data to be loaded from low to high are: 0001, 1000, 1111, and 1111. After 0001 is loaded into the specified register, the values of the remaining high bits will be set to 0. However, 1000 does not meet the ignore condition. Therefore, 1000 can be loaded into the specified register and sign-extended, and the values of the remaining high bits will be set to 1. Further, since the third part is 1111, which meets the ignore condition, this part can be not loaded. And due to the previous sign-extension, the corresponding bits of the third part in the specified register have been set to 1111. Therefore, it can ensure content consistency while omitting the loading operation. Similarly, the fourth part can also be not loaded. In this way, only two immediate load instructions are needed to implement the loading operation of the data to be loaded. In the embodiments of the present invention, according to the content of each part of the data to be loaded, the optimal integer loading scheme is correspondingly selected, that is, it is determined whether this part needs to be loaded, which can optimize the loading process and improve the loading efficiency.

[0047] Optionally, in one implementation, it is possible to detect whether the sub-data to be loaded meets a preset ignore condition in ascending order, and selectively perform the loading operation on the sub-data to be loaded based on the detection result. That is to say, in this implementation, the operation of detecting whether the sub-data to be loaded meets the preset ignore condition and the operation of loading and sign-extending the sub-data to be loaded can be alternated.

[0048] The operation of detecting whether the sub-data to be loaded meets the preset ignore condition specifically may include:

[0049] Step S41: Detect whether the sub-data to be loaded meets the preset ignore condition in ascending order.

[0050] Correspondingly, the operation of loading the target sub-data into the specified register based on the immediate load instruction corresponding to the target sub-data and extending the current remaining high bits based on the value of the sign bit of the target sub-data specifically may include:

[0051] Step S42: When it is detected that the sub-data to be loaded does not meet the ignore condition, determine the sub-data to be loaded as the target sub-data, and load the target sub-data into the corresponding bit field of the specified register based on the immediate load instruction corresponding to the target sub-data.

[0052] Specifically, it can be directly determined that the lowest-order sub-data to be loaded does not meet the ignoring condition. Accordingly, the operation of determining the lowest-order sub-data to be loaded as the target sub-data can be then performed, so that the lowest-order sub-data to be loaded is first loaded into the corresponding bit field of the specified register, and after the first sign extension, the values of the remaining high-order bits are all set to the highest bit value of the lowest-order sub-data to be loaded.

[0053] Further, subsequently, other sub-data to be loaded can be sequentially used as the current sub-data in ascending order. When the values in the current sub-data are not all the same, or when the values are all the same and the value is inconsistent with the highest bit value of the sub-data to be loaded that was most recently loaded into the corresponding bit field of the specified register, it is determined that the current sub-data does not meet the preset ignoring condition. When the values in the current sub-data are all the same and the value is consistent with the highest bit value of the sub-data to be loaded that was most recently loaded into the corresponding bit field of the specified register, it is determined that the current sub-data meets the preset ignoring condition.

[0054] Exemplarily, the previous sub-data to be loaded of the lowest-order sub-data to be loaded can be first used as the current sub-data and detected. If the current sub-data meets the ignoring condition, the current sub-data can be ignored. If not, the current sub-data can be loaded into the specified register and sign-extended based on the corresponding immediate load instruction. Then, the previous sub-data to be loaded of the current sub-data can be used as the new current sub-data to loop and execute the above operations.

[0055] Assume that the integer IMM is divided into n parts for loading, and IMM[i] represents the sub-data to be loaded. Define the variable i with its initial value set to 0. Figure 2 is a schematic diagram of a loading process provided by an embodiment of the present invention. As Figure 2 shown, IMM[i] can be first loaded into the corresponding position of the destination register. Then i is updated to i + 1. And when i is less than n, that is, when not all the data bits of the integer IMM have been traversed, it is detected whether the current IMM[i] is all 0, and when IMM[i] is all 0, it is detected whether the highest bit of IMM[i - 1] is 0. Here, IMM[i - 1] represents the adjacent lower-order sub-data to be loaded of IMM[i]. If the highest bit of IMM[i - 1] is not 0, it can be determined that the ignoring condition is not met, and further, the loading operation can be performed. On the contrary, it can be determined that the ignoring condition is met, and i is directly updated to continue detecting other sub-data to be loaded.

[0056] Further, when IMM[i] is not all 0, it is possible to detect whether the current IMM[i] is all 1, and when IMM[i] is all 1, detect whether the highest bit of IMM[i - 1] is 1. If the highest bit of IMM[i - 1] is not 1, it can be determined that the ignore condition is not met, and then the load operation can be performed. Conversely, it can be determined that the ignore condition is met, and i can be directly updated to continue detecting other sub-data to be loaded. It should be noted that the order of the operations of detecting whether the current IMM[i] is all 0 and detecting whether the current IMM[i] is all 1 is not unique. It is also possible to first detect whether IMM[i] is all 1, then detect whether the current IMM[i] is all 0, or perform them synchronously. The embodiments of the present invention do not limit this.

[0057] In the embodiments of the present invention, the sub-data to be loaded is detected one by one. After a detection is completed, and when the detection result indicates that the sub-data to be loaded does not meet the ignore condition, an operation is performed to use the sub-data to be loaded as the target sub-data, load the target sub-data into the corresponding bit field of the specified register based on the immediate instruction corresponding to the target sub-data, and extend the current remaining high bits based on the value of the sign bit of the target sub-data. In this way, through multiple loop detections, the loading can be achieved, and the loading efficiency can be ensured to a certain extent.

[0058] In another implementation, it is possible to first determine all the sub-data to be loaded that do not meet the ignore condition in the data to be loaded. Then, the load and sign extension operations are performed. That is to say, in this implementation, the operation of detecting whether the sub-data to be loaded meets the preset ignore condition and the operation of loading and sign extending the sub-data to be loaded may not be alternated.

[0059] Correspondingly, the operation of detecting whether the sub-data to be loaded meets the preset ignore condition may specifically include:

[0060] Step S61: Create a first array, a second array, and a third array; each element value in the first array is used to represent whether each value in the sub-data to be loaded is all 0, each element value in the second array is used to represent whether each value in the sub-data to be loaded is all 1, and each element value in the third array is used to represent whether the sign bit of the adjacent lower sub-data to be loaded in the sub-data to be loaded is a specified value, and one element value corresponds to one sub-data to be loaded.

[0061] In this step, one element value in the first array can be used to represent whether a sub-data to be loaded is all 0, and one element value in the second array can be used to represent whether a sub-data to be loaded is all 1.

[0062] Step S62: Detect according to the corresponding element values of each of the to-be-loaded sub-data in the first array, the corresponding element values in the second array, and the corresponding element values in the third array, so as to filter out all the to-be-loaded sub-data that meet the ignoring condition.

[0063] In the embodiment of the present invention, the to-be-loaded sub-data consists of 0 and / or 1. Accordingly, it may be all 0 or all 1. Specifically, a first array with a length of n can be created, where n represents the number of to-be-loaded sub-data, to ensure that the array is sufficient to accommodate the corresponding element values of the to-be-loaded sub-data. Then, when the to-be-loaded sub-data is all 0, the corresponding element value of the to-be-loaded sub-data is set to 1; otherwise, the corresponding element value of the to-be-loaded sub-data is set to 0, thus completing the creation. Among them, when the element value is 1, it indicates that the to-be-loaded sub-data can be symbol-expanded from the adjacent lower-order to-be-loaded sub-data; when the element value is 0, it indicates that the to-be-loaded word data cannot be symbol-expanded from the adjacent lower-order to-be-loaded sub-data. A second array with a length of n is created, and then when the to-be-loaded word data is all 1, the corresponding element value of the to-be-loaded word data is set to 1; otherwise, the corresponding element value of the to-be-loaded word data is set to 0, thus completing the creation. Among them, when the element value is 1, it indicates that the to-be-loaded sub-data can be symbol-expanded from the adjacent lower-order to-be-loaded sub-data; when the element value is 0, it indicates that the to-be-loaded word data cannot be symbol-expanded from the adjacent lower-order to-be-loaded sub-data. Further, the specified value can be 0 or 1. When the specified value is 1 and the element values in the third array are used to represent whether the sign bits of the adjacent lower-order to-be-loaded sub-data of the to-be-loaded sub-data are 1, a third array with a length of n can be created, and then when the sign bit of the adjacent lower-order to-be-loaded sub-data of the to-be-loaded sub-data is 1, the corresponding element value of the to-be-loaded sub-data is set to 1; otherwise, the corresponding element value of the to-be-loaded sub-data is set to 0, thus completing the creation. Among them, when the element value is 1, it indicates that the sign bit of the adjacent lower-order to-be-loaded sub-data of the to-be-loaded sub-data is 1, and after loading this to-be-loaded sub-data, the high-order bits are all symbol-expanded to 1; when the element value is 0, it indicates that the sign bit of the adjacent lower-order to-be-loaded sub-data is 0, and after loading this to-be-loaded sub-data, the high-order bits are all symbol-expanded to 0.

[0064] In the embodiment of the present invention, a truth table is pre-generated, and based on the corresponding element values of the to-be-loaded sub-data in the first array, the second array, and the third array, it is determined whether the to-be-loaded sub-data meets the ignoring condition by referring to the truth table.

[0065] For example, all0_bit indicates whether all element values in the sub-data to be loaded are 0, all1_bit indicates whether all element values in the sub-data to be loaded are 1, and sign1_bit indicates whether the sign bit of the adjacent lower-order sub-data to be loaded is 1. The following truth table can be generated:

[0066] is_sext_of_prev all0_bit all1_bit sign1_bit 1 1 0 0 0 0 1 0 0 0 0 1 Does not exist 1 1 0 1 0 1 1 0 1 0 1 Does not exist 1 1 1

[0067] Among them, when the value of "is_sext_of_prev" is 1, it indicates that the sub-data to be loaded meets the ignore condition; when the value of "is_sext_of_prev" is not 1, it indicates that the sub-data to be loaded does not meet the ignore condition. Based on this truth table, it can be concluded that when and only when (all0_bit^all1_bit)&(all0_bit^sign1_bit) is 1, it indicates that the sub-data to be loaded is extended by sign from the adjacent lower-order part. Therefore, this part does not need to be loaded, and the instruction to load this sub-data to be loaded can be omitted, thereby reducing the number of instructions, optimizing the loading process, and improving the program running efficiency.

[0068] Furthermore, when the specified value is 0 and the element values in the third array are used to represent whether the sign bit value of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded is 0, a third array with a length of n can be created. Then, when the sign bit of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded is 0, the element value corresponding to this sub-data to be loaded is set to 1; otherwise, the element value corresponding to this sub-data to be loaded is set to 0, thus completing the creation. Among them, when the element value is 1, it represents that the sign bit of the adjacent lower-order sub-data to be loaded is 0, and after loading this sub-data to be loaded, the high-order bits are all sign-extended to 0; when the element value is 0, it represents that the sign bit of the adjacent lower-order sub-data to be loaded is 1, and after loading this sub-data to be loaded, the high-order bits are all sign-extended to 1.

[0069] Correspondingly, the truth table generated in this case can be expressed as:

[0070] is_sext_of_prev all0_bit all1_bit sign1_bit 0 1 0 0 1 0 1 0 0 0 0 1 Does not exist 1 1 0 0 0 1 1 1 1 0 1 Does not exist 1 1 1

[0071] Among them, sign0_bit indicates whether the sign bit of the adjacent lower-order sub-data to be loaded is 0. Based on this truth table, it can be concluded that when and only when (all0_bit^all1_bit)&(all1_bit^sign0_bit) is 1, it indicates that the sub-data to be loaded is extended by sign from the adjacent lower-order part. Therefore, this part does not need to be loaded, and the instruction to load this sub-data to be loaded can be omitted, thereby reducing the number of instructions, optimizing the loading process, and improving the program running efficiency.

[0072] The following uses a specific application scenario for illustration. In the embodiments of the present invention, it can be specifically applied to compiler optimization to provide a method for loading integers during the compilation of assembly language. The data loading method provided in the embodiments of the present invention can be specifically applied to meet the following conditions under the target architecture adopted: the length of the specified register is not less than the length of the data to be loaded, there are at least n immediate number loading instructions that can load n parts into the corresponding areas of the register, and the immediate number loading instructions all perform sign extension on the immediate number. Correspondingly, the embodiments of the present invention divide an integer into multiple parts and jointly implement the loading based on multiple instructions. In this way, to a certain extent, without improving the hardware performance, the immediate number loading instructions can be fully utilized to improve the loading efficiency.

[0073] Figure 3 is a structural block diagram of an embodiment of a data loading device of the present invention, as Figure 3 shown. The device 30 may include the following modules:

[0074] A division module 301, configured to divide the data to be loaded into n parts based on the loadable information of the immediate number loading instruction under the target architecture, obtaining n sub-data to be loaded; one of the sub-data to be loaded corresponds to one of the immediate number loading instructions, and the target architecture is the instruction system architecture adopted by the electronic device;

[0075] A loading module 302, configured to load the sub-data to be loaded into the corresponding bit field of the specified register based on the immediate number loading instruction corresponding to the sub-data to be loaded; the length of the specified register is not less than the length of the data to be loaded.

[0076] In summary, a data loading device provided in the embodiments of the present invention divides the data to be loaded into n parts based on the loadable information of the immediate number loading instruction under the target architecture, obtaining n sub-data to be loaded. One sub-data to be loaded corresponds to one immediate number loading instruction, and the target architecture is the instruction system architecture adopted by the electronic device. Based on the immediate number loading instruction corresponding to the sub-data to be loaded, the sub-data to be loaded is loaded into the corresponding bit field of the specified register; the length of the specified register is not less than the length of the data to be loaded. In the embodiments of the present invention, by dividing the data to be loaded into multiple sub-data to be loaded and using the corresponding multiple immediate number loading instructions to load the sub-data to be loaded respectively, the loading operation of the data to be loaded is realized. In this way, to a certain extent, when the data to be loaded is relatively long, it can be ensured that the data can be successfully loaded into the specified register.

[0077] Optionally, the loading module 302 includes:

[0078] A detection sub-module, configured to detect whether the sub-data to be loaded meets a preset ignoring condition; the ignoring condition includes: all the values in the sub-data to be loaded are the same and the value is the same as the sign bit value of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded;

[0079] A loading sub-module, configured to use the sub-data to be loaded that does not meet the ignoring condition as target sub-data, and load the target sub-data into the corresponding bit field of a specified register based on the immediate load instruction corresponding to the target sub-data, and extend the current remaining higher bits based on the sign bit value of the target sub-data;

[0080] A cancellation module, configured not to perform a loading operation on the sub-data to be loaded that meets the ignoring condition.

[0081] Optionally, the detection sub-module is specifically configured to: sequentially detect whether the sub-data to be loaded meets the preset ignoring condition in ascending order;

[0082] The loading sub-module is specifically configured to:

[0083] When it is detected that the sub-data to be loaded does not meet the ignoring condition, determine the sub-data to be loaded as the target sub-data, and load the target sub-data into the corresponding bit field of a specified register based on the immediate load instruction corresponding to the target sub-data.

[0084] Optionally, the loading sub-module is further specifically configured to:

[0085] Set all the values of the current remaining higher bits to the sign bit value.

[0086] Optionally, the detection sub-module is specifically configured to:

[0087] Create a first array, a second array, and a third array; the values of the elements in the first array are used to represent whether all the values in the sub-data to be loaded are all 0, the values of the elements in the second array are used to represent whether all the values in the sub-data to be loaded are all 1, and the values of the elements in the third array are used to represent whether the sign bit of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded is a specified value, and one element value corresponds to one sub-data to be loaded;

[0088] Detect according to the element values corresponding to each sub-data to be loaded in the first array, the element values corresponding to the second array, and the element values corresponding to the third array, so as to filter out all the sub-data to be loaded that meet the ignoring condition.

[0089] Optionally, the loadable information includes the data length and loadable data bit field that can be loaded by the immediate load instruction; the partitioning module 301 is specifically configured to:

[0090] Select n immediate load instructions from the immediate load instructions under the target architecture according to the data length and the loadable data bit field; the sum of the data lengths that can be loaded by the n immediate load instructions is equal to the length of the data to be loaded, and the loadable data bit fields corresponding to the n immediate load instructions are consecutive;

[0091] Divide the data to be loaded into n parts according to the selected n immediate load instructions.

[0092] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the partial description of the method embodiment.

[0093] Figure 4 It is a block diagram of the structure of an electronic device shown according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0094] Refer to Figure 4 , the electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input / output (I / O) interface 412, a sensor component 414, and a communication component 416.

[0095] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, telephone call, data communication, camera operation, and recording operation. The processing element 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0096] The memory 404 is configured to store various types of data to support the operation of the device 400. Examples of these data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, videos, etc. The memory 404 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0097] The power supply component 406 provides power for various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 400.

[0098] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0099] The audio component 410 is configured to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 400 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, the audio component 410 further includes a speaker for outputting audio signals.

[0100] The I / O interface 412 provides an interface between the processing component 402 and a peripheral interface module, and the peripheral interface module can be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.

[0101] The sensor assembly 414 includes one or more sensors for providing an assessment of the status of various aspects of the electronic device 400. For example, the sensor assembly 414 can detect the on / off state of the device 400, the relative positioning of components, such as the display and keypad of the electronic device 400. The sensor assembly 414 can also detect a change in the position of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and a change in the temperature of the electronic device 400. The sensor assembly 414 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0102] The communication component 416 is configured to facilitate communication between the electronic device 400 and other devices in a wired or wireless manner. The electronic device 400 can access a wireless network based on communication standards, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 414 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 414 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0103] In an exemplary embodiment, the electronic device 400 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described methods.

[0104] Preferably, an embodiment of the present invention further provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, it implements each process of the above-described data loading method embodiment and can achieve the same technical effects. To avoid repetition, it will not be described in detail here.

[0105] An embodiment of the present invention also provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, it implements each process of the above-described embodiment of the data loading method and can achieve the same technical effects. To avoid repetition, it will not be elaborated here. Among them, the computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc, etc.

[0106] It should be noted that in this article, the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article, or device including that element.

[0107] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment method can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc) and includes several instructions for causing a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in various embodiments of the present invention.

[0108] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the purpose of the present invention and the scope protected by the claims, and all of them belong to the protection scope of the present invention.

Claims

1. A data loading method, characterized in that, Applied to an electronic device, the method includes: Based on the loadable information of the immediate load instruction under the target architecture, divide the data to be loaded into n parts to obtain n sub-data to be loaded; one of the sub-data to be loaded corresponds to one of the immediate load instructions, and the target architecture is the instruction set architecture adopted by the electronic device; Based on the immediate load instruction corresponding to the sub-data to be loaded, load the sub-data to be loaded into the corresponding bit field of the specified register; the length of the specified register is not less than the length of the data to be loaded; The step of loading the sub-data to be loaded into the corresponding bit field of the specified register based on the immediate load instruction corresponding to the sub-data to be loaded includes: detecting whether the sub-data to be loaded meets a preset ignoring condition; the ignoring condition includes: all the values in the sub-data to be loaded are the same and the value is the same as the sign bit value of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded; take the sub-data to be loaded that does not meet the ignoring condition as the target sub-data, and based on the immediate load instruction corresponding to the target sub-data, load the target sub-data into the corresponding bit field of the specified register, and extend the current remaining high bits based on the sign bit value of the target sub-data; do not perform the load operation on the sub-data to be loaded that meets the ignoring condition.

2. The method according to claim 1, wherein The step of detecting whether the sub-data to be loaded meets a preset ignoring condition includes: sequentially detecting whether the sub-data to be loaded meets a preset ignoring condition in ascending order; The step of taking the sub-data to be loaded that does not meet the ignoring condition as the target sub-data and loading the target sub-data into the corresponding bit field of the specified register based on the immediate load instruction corresponding to the target sub-data includes: When it is detected that the sub-data to be loaded does not meet the ignoring condition, determine the sub-data to be loaded as the target sub-data, and load the target sub-data into the corresponding bit field of the specified register based on the immediate load instruction corresponding to the target sub-data.

3. The method according to claim 1 or 2, characterized in that The step of extending the current remaining high bits based on the sign bit value of the target sub-data includes: Set all the values of the current remaining high bits to the value of the sign bit.

4. The method according to claim 1, wherein The step of detecting whether the sub-data to be loaded meets a preset ignoring condition includes: Create a first array, a second array, and a third array; the values of the elements in the first array are used to represent whether all the values in the sub-data to be loaded are all 0, the values of the elements in the second array are used to represent whether all the values in the sub-data to be loaded are all 1, and the values of the elements in the third array are used to represent whether the sign bit of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded is a specified value, and one element value corresponds to one sub-data to be loaded; Detect according to the element values corresponding to each sub-data to be loaded in the first array, the element values corresponding to the second array, and the element values corresponding to the third array, so as to filter out all the sub-data to be loaded that meet the ignoring condition.

5. The method according to claim 1, wherein The loadable information includes the data length and loadable data bit field that can be loaded by the immediate load instruction; dividing the data to be loaded into n parts based on the loadable information of the immediate load instruction under the target architecture, including: Selecting n immediate load instructions from the immediate load instruction under the target architecture according to the data length and the loadable data bit field; the sum of the data lengths that can be loaded by the n immediate load instructions is equal to the length of the data to be loaded, and the loadable data bit fields corresponding to the n immediate load instructions are consecutive; Dividing the data to be loaded into n parts according to the selected n immediate load instructions.

6. A data loading device, characterized in that, Applied to an electronic device, the apparatus includes: A dividing module, configured to divide the data to be loaded into n parts based on the loadable information of the immediate load instruction under the target architecture, to obtain n sub-data to be loaded; one sub-data to be loaded corresponds to one immediate load instruction, and the target architecture is the instruction system architecture adopted by the electronic device; A loading module, configured to load the sub-data to be loaded into a corresponding bit field of a specified register based on the immediate load instruction corresponding to the sub-data to be loaded; the length of the specified register is not less than the length of the data to be loaded; The loading module includes: a detection sub-module, configured to detect whether the sub-data to be loaded meets a preset ignoring condition; the ignoring condition includes: each value in the sub-data to be loaded is the same and the value is the same as the sign bit value of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded; A loading sub-module, configured to use the sub-data to be loaded that does not meet the ignoring condition as target sub-data, and load the target sub-data into a corresponding bit field of a specified register based on the immediate load instruction corresponding to the target sub-data, and extend the current remaining high bits based on the sign bit value of the target sub-data; a cancellation module, configured not to perform a loading operation on the sub-data to be loaded that meets the ignoring condition.

7. The device according to claim 6, characterized in that The detection sub-module is specifically configured to: sequentially detect whether the sub-data to be loaded meets a preset ignoring condition in ascending order; The loading sub-module is specifically configured to: When it is detected that the sub-data to be loaded does not meet the ignoring condition, determine the sub-data to be loaded as the target sub-data, and load the target sub-data into a corresponding bit field of a specified register based on the immediate load instruction corresponding to the target sub-data.

8. The device according to claim 6 or 7, characterized in that, The loading sub-module is further specifically configured to: Set the values of the current remaining high bits to the value of the sign bit.

9. The device according to claim 6, wherein The detection sub-module is specifically configured to: Create a first array, a second array, and a third array; each element value in the first array is used to represent whether each value in the sub-data to be loaded is all 0, each element value in the second array is used to represent whether each value in the sub-data to be loaded is all 1, and each element value in the third array is used to represent whether the sign bit of the adjacent lower-order sub-data to be loaded of the sub-data to be loaded is a specified value, and one element value corresponds to one sub-data to be loaded; Detect according to the corresponding element values of each to-be-loaded sub-data in the first array, the corresponding element values in the second array, and the corresponding element values in the third array, so as to filter out all to-be-loaded sub-data that meet the ignore condition.

10. The device according to claim 6, characterized in that, The loadable information includes the data length and loadable data bit field that can be loaded by the immediate load instruction; the partitioning module is specifically configured to: Select n immediate load instructions from the immediate load instructions under the target architecture according to the data length and the loadable data bit field; the sum of the data lengths that can be loaded by the n immediate load instructions is equal to the length of the to-be-loaded data, and the loadable data bit fields corresponding to the n immediate load instructions are continuous; Partition the to-be-loaded data into n parts according to the selected n immediate load instructions.

11. An electronic device, characterized in that, Includes: A processor, a memory, and a computer program stored on the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1-5 when executing the program.

12. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is enabled to execute the method according to any one of claims 1-5 in the method claims.

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