Rail-to-Rail Amplifier with Dynamic Bias Current Common-Mode Feedback

Abstract

The present application discloses a rail-to-rail amplifier with dynamic bias current common-mode feedback, comprising a bias circuit, a constant transconductance input circuit, a cascode load circuit, a floating bias circuit, a class-AB output circuit, and a Miller compensation circuit. The amplifier also includes a complementary dynamic bias common-mode feedback circuit for compensating for current changes in a floating current source disposed in the cascode load circuit due to input common-mode changes in the constant transconductance input circuit, thereby maintaining a constant current in the floating current source. The output terminals Vop and Von of the class-AB output circuit serve as input terminals of the complementary dynamic bias common-mode feedback circuit. By creatively adding complementary common-mode feedback n-type CMFB and p-type CMFB, the present invention dynamically adjusts the current to maintain a stable current flowing through the floating current source. This stabilizes the amplifier's open-loop gain and output common-mode when the input common-mode voltage Vicm dynamically changes, thereby ensuring the amplifier's linearity.

Description

Technical Field

[0001] The present invention relates to the technical field of amplifiers, in particular to the technical field of high-linearity rail-to-rail amplifiers, and specifically to a rail-to-rail amplifier with dynamic bias current common-mode feedback. Background Art

[0002] The signal chain of a high-precision analog-to-digital converter requires modules such as high-precision buffers, filters, and adjustable-gain amplifiers. Amplifiers are a core component of these modules. When the input signal is accompanied by a large common-mode signal and the signal chain requires a high dynamic range, stringent requirements are placed on the amplifier in several aspects. For example, the amplifier must have a rail-to-rail input range, a high common-mode rejection ratio (CMRR), low equivalent input noise (IRN), and low total harmonic distortion (THD). These specifications make amplifier design challenging.

[0003] Differential amplifier circuits help suppress common-mode interference signals. Generally speaking, differential amplifiers require a common-mode feedback circuit to stabilize their output common-mode voltage. This way, the subsequent circuits can avoid being affected by common-mode interference. Rail-to-rail input range is usually achieved through a constant-gm input pair. Figure 7 A constant transconductance input circuit is shown, which mainly performs fixed compensation on the current of the PMOS tube and the NMOS tube respectively through two adapted current mirrors, wherein the adaptation coefficient of the current mirror is determined by the size of the PMOS tube and the NMOS tube, that is, due to the difference in the mobility of the PMOS tube and the NMOS tube, but based on this technology, no matter what kind of difference exists, effective matching can be achieved in theory, thereby achieving the effect of constant transconductance. Nevertheless, although the constant transconductance is solved and the rail-to-rail input range is met, the output current will cause the equivalent resistance of the back-end common source and common gate load to change due to the change of the input common mode, which will eventually cause the gain of the amplifier to change and decrease, deteriorate the linearity, and thus fail to meet the application requirements of high-precision scenarios. Therefore, how to ensure the stability of the amplifier gain and ensure that the linearity is not affected while meeting the rail-to-rail input range is a major problem in amplifier design. Summary of the Invention

[0004] In order to solve the problem in the prior art described in the background technology that the linearity of the amplifier will be reduced after the constant transconductance is used to meet the rail-to-rail input range, the present application provides a rail-to-rail amplifier with dynamic bias current common-mode feedback, which is used to simultaneously meet the rail-to-rail wide input range and gain stability, thereby ensuring the linearity of the amplifier.

[0005] In order to achieve the above objectives, the technical solutions adopted in this application are:

[0006] A rail-to-rail amplifier with dynamic bias current common-mode feedback includes a bias circuit, a constant transconductance input circuit, a cascode load circuit, a floating bias circuit, a class-AB output circuit, and a Miller compensation circuit. The amplifier also includes a complementary dynamic bias common-mode feedback circuit for compensating for a current change in a floating current source disposed in the cascode load circuit due to an input common-mode change in the constant transconductance input circuit, thereby maintaining a constant current in the floating current source. The output terminals Vop and Von of the Miller compensation circuit serve as input terminals of the complementary dynamic bias common-mode feedback circuit.

[0007] As a preferred design solution of the present invention, the cascode load circuit further includes a common-mode feedback pair of NMOS transistors and a common-mode feedback pair of PMOS transistors, respectively connected to the floating current source; the complementary dynamic bias common-mode feedback circuit includes an N-type CMFB for compensating for current changes in the common-mode feedback pair of NMOS transistors and a P-type CMFB for compensating for current changes in the common-mode feedback pair of PMOS transistors;

[0008] The common-mode feedback pair of NMOS transistors includes M39 and M40, each with a source connected to VSS and a drain connected to the floating current source via the common-gate NMOS pair. The gate is connected to the first common-mode feedback circuit output terminal CMFBn. The common-mode feedback pair of PMOS transistors includes M29 and M30, each with a source connected to VDD and a drain connected to the floating current source via the common-gate PMOS pair. The gate is connected to the second common-mode feedback circuit output terminal CMFBp. The above-described structural arrangement enables targeted compensation. Regardless of how the input voltages Vip and Vin fluctuate within the rail-to-rail range, dynamic compensation can be performed on the common-mode feedback pair of NMOS transistors and the common-mode feedback pair of PMOS transistors, ultimately ensuring that the current flowing in the floating current source remains constant and is not affected by fluctuations in the input voltages Vip and Vin.

[0009] Furthermore, the complementary dynamic bias common-mode feedback circuit also includes a common-mode feedback input circuit connected to the N-type CMFB and the P-type CMFB respectively and providing an output common-mode Vocm, wherein the output common-mode Vocm=(Vop+Von) / 2.

[0010] In order to ensure the matching of dynamic compensation, preferably, the present invention adopts the following specific solution: the N-type CMFB is composed of 4 PMOS transistors M53, M54, M55, and M58 and 3 NMOS transistors M56, M57, and M59; the gate of M54 is connected to the output common mode Vocm, the source of M54 is respectively connected to the drains of M53, M58, and M59 and the source of M55, the sources of M53 and M58 are connected to VDD, the drains of M54 and M56 are connected to the gate of M56 and connected to the first common-mode feedback circuit output terminal CMFBn, the sources of M56, M57, and M59 are connected to VSS, the drain of M57 is connected to the gate of M55, the gate of M55 is connected to the reference voltage Vref, the gate of M58 is connected to the first dynamic bias voltage Vpsw, and the gate of M59 is connected to the second dynamic bias voltage Vnsw;

[0011] The P-type CMFB consists of four NMOS transistors M62, M63, M64, and M66 and three PMOS transistors M60, M61, and M65. The gate of M62 is connected to the output common mode Vocm, the source of M62 is respectively connected to the drains of M64, M65, and M66 and the source of M63, the sources of M64 and M66 are connected to VSS, the drains of M62 and M60 are connected to the gate of M60 and to the output terminal CMFBp of the second common-mode feedback circuit, the sources of M60, M61, and M65 are connected to VDD, the drain of M61 is connected to the gate of M63, the gate of M63 is connected to the reference voltage Vref, the gate of M65 is connected to the first dynamic bias voltage Vpsw, and the gate of M66 is connected to the second dynamic bias voltage Vnsw.

[0012] Advantageously, the common-mode feedback input circuit is composed of a pair of symmetrically arranged resistors Rcm and a pair of symmetrically arranged capacitors Ccm; one end of any one of the resistors Rcm is connected to the output common-mode Vocm, and the other end of the resistor Rcm is connected to Vop and Von respectively; one end of any one of the capacitors Ccm is connected to the output common-mode Vocm, and the other end of the capacitor Ccm is connected to Vop and Von respectively.

[0013] Beneficial effects:

[0014] By adding complementary common-mode feedback (n-type CMFB) and p-type CMFB, and creatively dynamically adjusting the currents of M29 / M30 and M39 / M40, this invention maintains the current flowing through the floating current source stable, thereby maintaining amplifier gain and enhancing linearity. This invention stabilizes the amplifier's open-loop gain and output common mode even when the input common-mode voltage (Vicm) dynamically changes, ensuring the amplifier's linearity.

[0015] The present invention fundamentally overcomes the problem that the equivalent output impedance of the common-source and common-gate load inevitably changes with the input common-mode Vicm, which is caused by the fact that one end of the existing CMOS amplifier is used as a constant current source and the other end is used as a common-mode feedback input, and ultimately causes the amplifier gain to change and the linearity to be inevitably greatly affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 is a circuit diagram of the present invention (excluding the complementary dynamic bias common-mode feedback circuit).

[0018] Figure 2 yes Figure 1 The graph of transconductance gm changes with input common mode Vicm.

[0019] Figure 3 This is the common-mode feedback circuit diagram of the existing constant bias.

[0020] Figure 4 It is a complementary dynamic bias common mode feedback circuit.

[0021] Figure 5 This is a schematic diagram of the structure of the buffer when the present invention is expanded to 4 inputs.

[0022] Figure 6 are the total harmonic distortion (THD) and spurious-free dynamic range (SFDR) of the input buffer.

[0023] Figure 7 This is the schematic diagram of the existing constant transconductance input circuit.

[0024] In the figure: 100-bias circuit; 200-constant transconductance input circuit; 201-PMOS switch; 202-NMOS switch; 300-cascode load circuit; 301-floating current source; 302-common-mode feedback pair NMOS transistor; 303-common-mode feedback pair PMOS transistor; 400-floating bias circuit; 500-class-AB output circuit; 600-Miller compensation circuit; 700-complementary dynamic bias common-mode feedback circuit; 701-common-mode feedback input circuit; 702-N-type CMFB; 703-P-type CMFB. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.

[0027] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0028] Example 1:

[0029] To better explain the present invention, the technical improvement principles and contents of the present invention are specifically and prominently described. First, this embodiment will be described based on the circuit structure and operating principle of the embodiment without the complementary dynamic bias common-mode feedback circuit 700. This is intended to enable those skilled in the art to fully understand the technical solution adopted by the complementary dynamic bias common-mode feedback circuit 700 to solve the problem of amplifier linearity and the beneficial technical effects that are inevitably achieved. The details are as follows:

[0030] In conjunction with the instructions Figure 1 The rail-to-rail amplifier shown includes a bias circuit 100 , a constant transconductance input circuit 200 , a cascode load circuit 300 , a floating bias circuit 400 , a class-AB output circuit 500 , and a Miller compensation circuit 600 .

[0031] The bias circuit 100 generates constant bias voltages Vpt, Vpcas, Vncas, and Vntail through four PMOS transistors and two NMOS transistors, and acts on the constant transconductance input circuit 200, the cascode load circuit 300, and the floating bias circuit 400, respectively, to achieve the operation of the corresponding PMOS transistors and NMOS transistors. Figure 1 shown.

[0032] The working principle of the constant transconductance input circuit 200 is as follows:

[0033] The most basic principle of implementing a constant input transconductance is achieved by taking advantage of the opposite conduction characteristics of PMOS and NMOS, that is, using PMOS to conduct for low levels (Vgs < Vthp < 0, where Vthp is the threshold voltage of the PMOS transistor), and NMOS to conduct for high levels (Vgs > Vthn > 0, where Vthn is the threshold voltage of the NMOS transistor). This ensures that when the input common mode changes over a wide range, there is always an input transistor conducting and the transconductance remains constant. As Figure 1 shown, M19 to M22 are input PMOS transistors, and M23 to M26 are input NMOS transistors. Here, since all input transistors operate in the subthreshold region, the transistor sizes are M19:M20:M21:M22 = 1, M23:M24:M25:M26 = 1.

[0034] Case 1: When the input common mode [Vicm = (Vip + Vin) / 2] is at the intermediate level (near VDD / 2), the PMOS input pair transistors M20 and M21 conduct. At this time, since the PMOS transistor M17 is in the cutoff state, therefore, the PMOS transistors M19 and M22 do not conduct; similarly, the NMOS input pair transistors M24 and M25 conduct simultaneously. Since the NMOS transistor M27 is in the cutoff state, therefore, the NMOS transistors M23 and M26 do not conduct. The input transconductance at this time is

[0035] gm-total = gmp + gmn = 2gm

[0036] Here, gmp and gmn are set to be approximately the same.

[0037] Case 2: When the input common mode decreases, because the tail currents (Id27, Id28) are constant current sources, the source voltage Vsn is pushed down. When Vicm is lower than around Vds27 / 28 + Vthn, the NMOS input pair transistors M24 and M25 gradually turn off, and the current flowing through them is zero. However, the current switch (current switch) M14 gradually turns on because Vsn is very low. The current Id27 of M27 then flows through M14 and M13. Through the current mirrors of M13 and M17, M17 mirror-copies this current, so the current flows into M19 and M22. At the same time, a first dynamic bias voltage Vpsw is generated at the gates of M13 and M17. The transistors that are working at this time are the 4 input PMOS transistors M19 to M22. The total input transconductance is

[0038] gm-total = 2*gmp = 2gm;

[0039] Scenario 3: When the input common mode increases, because the tail currents Id17 and Id18 are both constant current sources, the source voltage Vsp is also pushed up. When Vicm is higher than Vds17 / 18 + Vthp, the M20 and M21 PMOS input transistors gradually turn off, and the current flowing through them is zero. However, the other current switch (current switch) M15 gradually turns on due to its high Vsp. The current Id17 in M17 flows through M15 and M16, and through the current mirror of M16 and M27, M27 mirrors this current, causing the current to flow into M23 and M26. At the same time, the gates of M16 and M27 generate a second dynamic bias voltage Vnsw. At this time, the transistors working are the four input NMOS transistors from M23 to M26, and the total input transconductance is

[0040] gm-total=2*gmn=2gm;

[0041] It is worth noting that in the upper and lower transition regions, the sum of the transconductance gm-total of all tubes (including working PMOS tubes and NMOS tubes) may be slightly greater than or less than 2gm. Generally speaking, the variation range of gm-total is about 3-8%.

[0042] The fluctuation curve of the total transconductance gm-total of the above input common mode (Vicm=(Vip+Vin) / 2) fluctuates within the range of VSS-VDD is as follows Figure 2 shown.

[0043] The above description explains the operation of the input common mode Vicm within the rail-to-rail range. However, this will cause the current flowing into V1, V2, V3, and V4 in the subsequent source-common-gate load circuit 300 to change, that is, the current flowing into / out of M39, M40, M29, and M30 will change. Therefore, if a traditional CMOS amplifier is used, one end is used as a constant current source ( Figure 3 The bias voltage Vpt is shown in Figure 1), one end of which serves as the input of the common-mode feedback ( Figure 3 Common mode feedback CMFB shown in Figure 3As shown, the current flowing into the floating current sources M33 / M35, M34 / M36 will change according to the size of the input common mode. As a result, the equivalent output impedance of the source common-gate load circuit 300 will also change, causing the gain of the amplifier to change, and the linearity will be greatly affected. Moreover, even in the case of common-mode feedback, the output common mode will have a common-mode fluctuation of more than 5mV. Finally, Vop and Von are output through the floating bias circuit 400, the class-AB output circuit 500 and the Miller compensation circuit 600, resulting in the entire amplifier meeting the rail-to-rail input range, but the linearity of the gain cannot be guaranteed.

[0044] Example 2:

[0045] Based on the above-mentioned issues discussed in Example 1, the solution adopted in this embodiment further includes a complementary dynamic bias common-mode feedback circuit 700, which is used to compensate for the current variation of the floating current source 301 disposed in the cascode load circuit 300 due to the input common-mode variation in the constant transconductance input circuit 200, thereby maintaining a constant current in the floating current source 301. The output terminals Vop and Von of the Miller compensation circuit 600 serve as the input terminals of the complementary dynamic bias common-mode feedback circuit 700. The complementary dynamic bias common-mode feedback circuit 700 dynamically compensates the current, thereby maintaining a constant current in the floating current source 301 throughout the constant-gm process. This solves the problem described in Example 1 of variations in the equivalent output impedance of the cascode load caused by fluctuations in the input common-mode voltage Vicm within the rail-to-rail range, ultimately leading to variations in the amplifier's gain, thereby ensuring that the linearity of the amplifier is not significantly affected.

[0046] Under the guidance of the inventive concept provided by the present invention, this embodiment further provides a rail-to-rail amplifier with dynamic bias current common-mode feedback. The cascode load circuit 300 further includes a common-mode feedback pair of NMOS transistors 302 and a common-mode feedback pair of PMOS transistors 303, respectively connected to the floating current source 301. The complementary dynamic bias common-mode feedback circuit 700 includes an N-type CMFB 702 for compensating for current changes in the common-mode feedback pair of NMOS transistors 302 and a P-type CMFB 703 for compensating for current changes in the common-mode feedback pair of PMOS transistors 303.

[0047] The common-mode feedback NMOS transistor pair 302 includes M39 and M40 with a common source and common gate, wherein the source is connected to VSS, the drain is connected to the floating current source 301 through the common-gate NMOS transistor pair, and the gate is connected to the first common-mode feedback circuit output terminal CMFBn. The gate of the common-gate NMOS transistor pair is connected to the bias voltage Vpcas, the source is connected to the common-mode feedback NMOS transistor pair 302, and the drain is connected to the floating current source 301; the common-mode feedback PMOS transistor pair 303 includes M29 and M30 with a common source and common gate, wherein the source is connected to VDD, the drain is connected to the floating current source 301 through the common-gate PMOS transistor pair, and the gate is connected to the second common-mode feedback circuit output terminal CMFBp. The gate of the common-gate PMOS transistor pair is connected to the bias voltage Vncas, the source is connected to the common-mode feedback PMOS transistor pair, and the drain is connected to the floating current source 301; wherein, the first common-mode feedback circuit and the second common-mode feedback circuit adopt existing technologies and are not shown in the figure.

[0048] The complementary dynamic bias common mode feedback circuit 700 further includes a common mode feedback input circuit 701 connected to the N-type CMFB 702 and the P-type CMFB 703 respectively and providing an output common mode Vocm, wherein the output common mode Vocm=(Vop+Von) / 2. Figure 4 As shown, the common-mode feedback input circuit 701 consists of a pair of symmetrically arranged resistors Rcm and a pair of symmetrically arranged capacitors Ccm. One end of each resistor Rcm is connected to the output common-mode Vocm, and the other end of each resistor Rcm is connected to Vop and Von, respectively. One end of each capacitor Ccm is connected to the output common-mode Vocm, and the other end of each capacitor Ccm is connected to Vop and Von, respectively. With this structure, the output common-mode Vocm is averaged by the two Rcms, and their parasitic zeros are compensated by Ccm. The output common-mode Vocm is then input to the N-type CMFB 702 and P-type CMFB 703, respectively.

[0049] Specifically:

[0050] The N-type CMFB702 consists of four PMOS transistors M53, M54, M55, and M58, and three NMOS transistors M56, M57, and M59. The gate of M54 is connected to the output common mode Vocm, the source of M54 is respectively connected to the drains of M53, M58, and M59 and the source of M55, the sources of M53 and M58 are connected to VDD, the drains of M54 and M56 are connected to the gate of M56 and to the first common-mode feedback circuit output terminal CMFBn, the sources of M56, M57, and M59 are connected to VSS, the drain of M57 is connected to the gate of M55, the gate of M55 is connected to the reference voltage Vref, the gate of M58 is connected to the first dynamic bias voltage Vpsw, and the gate of M59 is connected to the second dynamic bias voltage Vnsw.

[0051] The N-type CMFB702 operates as follows: the output common-mode voltage Vocm is first input to the PMOS transistor M54. Current source transistor M53, controlled by a constant bias voltage Vpt, provides a stable current source. A first dynamic bias voltage, Vpsw, serves as the control voltage for the M13 / M17 current mirror. This controls the current in M58 based on the state of the PMOS switch 201 (current switch) M14, dynamically injecting I1. Similarly, a second dynamic bias voltage, Vnsw, serves as the control voltage for the M16 / M27 current mirror. This controls the current in M59 based on the state of the NMOS switch 202 (current switch) M15, dynamically injecting I2. Under the influence of I1 and I2, the current flowing through M56 is controlled by compensation current I3, thereby compensating for the increase or decrease in current in M39 / M40 caused by constant-gm.

[0052] The P-type CMFB703 consists of four NMOS transistors M62, M63, M64, and M66 and three PMOS transistors M60, M61, and M65. The gate of M62 is connected to the output common mode Vocm, the source of M62 is respectively connected to the drains of M64, M65, and M66 and the source of M63, the sources of M64 and M66 are connected to VSS, the drains of M62 and M60 are connected to the gate of M60 and to the output terminal CMFBp of the second common-mode feedback circuit, the sources of M60, M61, and M65 are connected to VDD, the drain of M61 is connected to the gate of M63, the gate of M63 is connected to the reference voltage Vref, the gate of M65 is connected to the first dynamic bias voltage Vpsw, and the gate of M66 is connected to the second dynamic bias voltage Vnsw.

[0053] The P-type CMFB703 operates as follows: the output common-mode voltage Vocm is first input to NMOS transistor M62. Current source transistor M64, controlled by a constant bias voltage Vntail, provides a stable current source. A first dynamic bias voltage, Vpsw, serves as the control voltage for the M13 / M17 current mirror. This controls the current in M65 based on the state of PMOS switch 201 (current switch M14), dynamically injecting current I4. Similarly, a second dynamic bias voltage, Vnsw, serves as the control voltage for the M16 / M27 current mirror. This controls the current in M66 based on the state of NMOS switch 202 (current switch M15), dynamically injecting current I5. Under the influence of currents I4 and I5, compensation current I6 controls the current flowing through M60, thereby compensating for the increase or decrease in current in M29 / M30 caused by constant-gm.

[0054] By dynamically adjusting the currents of M29 / M30 and M39 / M40 through the above structure, the requirement for maintaining a constant current in the floating current source 301 can be met. That is, the currents flowing through the floating current sources M33+M35, M34+M36 are stable, thereby fundamentally solving the problem of existing rail-to-rail amplifiers being unable to guarantee gain linearity when the input common-mode full swing is achieved.

[0055] In order to further illustrate the linearity of the structure shown in this embodiment, Figure 5 and Figure 6 As shown, Figure 5 Taking the input buffer shown in the figure as an example, the amplifier used in the figure has a 4-input structure, that is, a pair of constant current input stages are added to the original structure, and a unity gain input buffer is constructed through a closed loop. At a voltage of 3V, when the peak-peak voltage range of the input differential signal is ±2.26V, the harmonic performance of the output signal is as follows Figure 6 As shown, the input buffer of the amplifier using this embodiment has a low-frequency harmonic distortion of -118.4dB and a SFDR of up to 120dB. Compared to existing traditional structures, it is difficult for rail-to-rail amplifiers using single-ended common-mode feedback to achieve THD below -100dB and SFDR above 100dB. Therefore, the approach of this embodiment can stabilize the amplifier's open-loop gain and output common mode when the input common mode Vicm undergoes dynamic changes, thereby ensuring the linearity of the amplifier. The high-linearity rail-to-rail amplifier with dynamic bias current provided by this embodiment has outstanding substantive features and significant improvements compared to existing rail-to-rail amplifiers without dynamic bias compensation.

[0056] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A rail-to-rail amplifier with dynamic bias current common-mode feedback, comprising a bias circuit (100), a constant transconductance input circuit (200), a cascode load circuit (300), a floating bias circuit (400), a class-AB output circuit (500), and a Miller compensation circuit (600), characterized in that: It also includes a complementary dynamic bias common mode feedback circuit (700) for compensating for a current variation of a floating current source (301) provided in the common source and common gate load circuit (300) due to a change in the input common mode in the constant transconductance input circuit (200), so that the current in the floating current source (301) remains constant; the output terminals Vop and Von of the class-AB output circuit (500) serve as input terminals of the complementary dynamic bias common mode feedback circuit (700); The common-source common-gate load circuit (300) further comprises a common-mode feedback pair NMOS tube (302) and a common-mode feedback pair PMOS tube (303) respectively connected to the floating current source (301); the complementary dynamic bias common-mode feedback circuit (700) comprises an N-type CMFB (702) for compensating for a current variation of the common-mode feedback pair NMOS tube (302) and a P-type CMFB (703) for compensating for a current variation of the common-mode feedback pair PMOS tube (303); The common-mode feedback pair of NMOS transistors (302) includes M39 and M40 with a common source and common gate, wherein the source is connected to VSS, the drain is connected to the floating current source (301) through the common-gate NMOS pair, and the gate is connected to the first common-mode feedback circuit output terminal CMFBn; the common-mode feedback pair of PMOS transistors (303) includes M29 and M30 with a common source and common gate, wherein the source is connected to VDD, the drain is connected to the floating current source (301) through the common-gate PMOS pair, and the gate is connected to the second common-mode feedback circuit output terminal CMFBp; The N-type CMFB (702) is composed of four PMOS transistors M53, M54, M55, and M58 and three NMOS transistors M56, M57, and M59; the gate of M54 is connected to the output common mode Vocm, the source of M54 is respectively connected to the drains of M53, M58, and M59 and the source of M55, the sources of M53 and M58 are connected to VDD, the drains of M54 and M56 are connected to the gate of M56 and connected to the first common mode feedback circuit output terminal CMFBn, the sources of M56, M57, and M59 are connected to VSS, the drain of M57 is short-circuited with the gate and then connected to the drain of M55, the gate of M55 is connected to the reference voltage Vref, the gate of M58 is connected to the first dynamic bias voltage Vpsw, and the gate of M59 is connected to the second dynamic bias voltage Vnsw; The P-type CMFB (703) is composed of four NMOS transistors M62, M63, M64, and M66 and three PMOS transistors M60, M61, and M65; the gate of M62 is connected to the output common mode Vocm, the source of M62 is respectively connected to the drains of M64, M65, and M66 and the source of M63, the sources of M64 and M66 are connected to VSS, the drains of M62 and M60 are connected to the gate of M60 and connected to the output terminal CMFBp of the second common mode feedback circuit, the sources of M60, M61, and M65 are connected to VDD, the drain of M61 is short-circuited with the gate and then connected to the drain of M63, the gate of M63 is connected to the reference voltage Vref, the gate of M65 is connected to the first dynamic bias voltage Vpsw, and the gate of M66 is connected to the second dynamic bias voltage Vnsw.

2. The rail-to-rail amplifier with dynamic bias current common-mode feedback according to claim 1, wherein: The complementary dynamic bias common-mode feedback circuit (700) further comprises a common-mode feedback input circuit (701) connected to the N-type CMFB (702) and the P-type CMFB (703) respectively and providing an output common-mode Vocm, wherein the output common-mode Vocm=(Vop+Von) / 2.

3. The rail-to-rail amplifier with dynamic bias current common-mode feedback according to claim 2, wherein: The common-mode feedback input circuit (701) is composed of a pair of symmetrically arranged resistors Rcm and a pair of symmetrically arranged capacitors Ccm; one end of any resistor Rcm is connected to the output common-mode Vocm, and the other end of the resistor Rcm is connected to Vop and Von respectively; one end of any capacitor Ccm is connected to the output common-mode Vocm, and the other end of the capacitor Ccm is connected to Vop and Von respectively.

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