Level shifting circuit for converting from high level to low level

Abstract

The application provides a level conversion circuit for converting from a high level to a low level, the level conversion circuit comprising: a voltage dividing circuit configured to divide an input voltage to output an output voltage from an output node; an acceleration circuit configured to quickly switch the output voltage when the input voltage switches by quickly switching a first transistor to be turned on through a first capacitor; and a clamping protection circuit configured to prevent the output voltage from jumping up when the input voltage switches.

Description

Technical Field

[0001] This disclosure generally relates to level shifting circuits, and in particular, to level shifting circuits for shifting from high to low levels. Background Technology

[0002] With the continuous development of the integrated circuit industry, the constant updating of chip technology, and the increasing complexity of systems, logic communication between chips within the same system is becoming increasingly essential. However, the logic levels of different chips are not entirely consistent, and commonly used components within chips also vary between high-voltage and low-voltage devices. When two chips communicate, their input logic levels and output levels differ, making direct chip cascading impossible. Directly driving low-voltage components with high-level logic can damage the circuit. Therefore, level conversion circuits are needed to achieve logic driving. Furthermore, as signal frequencies continue to increase, the speed requirements for level conversion circuits are also rising. Summary of the Invention

[0003] Technical issues

[0004] Conventional level shifting circuits can transmit low-level signals to high-level signals. However, for high-level-to-low-level driving circuits, existing level shifting devices on the market are generally large in size and expensive. Furthermore, depending on the value of the voltage divider resistors, issues such as leakage current, increased circuit area, and increased cost may arise. Additionally, when the circuit has large parasitic capacitances, there may be excessively long level shifting times, or even failure to shift to the target level, resulting in bit errors.

[0005] Solution

[0006] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level. The level conversion circuit includes: a voltage divider circuit configured to divide an input voltage to output an output voltage from an output node; an acceleration circuit configured to quickly switch a first transistor to conduct via a first capacitor to rapidly switch the output voltage during the input voltage switching; and a clamping protection circuit configured to prevent the output voltage from jumping during the input voltage switching.

[0007] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein the voltage divider circuit includes N voltage divider diodes connected in series between an input node receiving the input voltage and a ground node, where N is a natural number greater than or equal to 2.

[0008] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein the voltage divider circuit further includes M resistors connected in series with the N voltage divider diodes to finely adjust the voltage divider circuit, wherein M is a natural number greater than or equal to 0.

[0009] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein any one of the N voltage divider diodes and the M resistors can serve as the output node.

[0010] An embodiment of the present invention provides a level shifting circuit for shifting from a high level to a low level, wherein one end of the first capacitor is connected to the input node and the other end is connected to the gate terminal of the first transistor.

[0011] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein the source and drain of the first transistor are connected to the output node and the ground node, respectively, and its gate is connected to one end of the first capacitor.

[0012] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein the acceleration circuit further includes a first resistor connected to the output node and the gate terminal of the first transistor.

[0013] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein the resistance value of the first resistor is greater than a first threshold.

[0014] An embodiment of the present invention provides a level shifting circuit for switching from a high level to a low level, wherein the clamping protection circuit includes a second transistor and a second capacitor, wherein the gate of the second transistor is connected to the gate of the first transistor through the second capacitor, and is configured to generate a pull-down signal instantaneously when a jump is made on the gate of the first transistor during the level switching from low to high.

[0015] An embodiment of the present invention provides a level shifting circuit for switching from a high level to a low level, wherein the clamping protection circuit further includes a second resistor, wherein the second resistor is connected between the gate of the second transistor and the ground node, and serves as a bias resistor to prevent leakage of the second transistor during normal operation.

[0016] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein the clamping protection circuit further includes a clamping diode, wherein the positive terminal of the clamping diode is grounded and its negative terminal is connected to the gate of the second transistor to clamp the gate of the second transistor.

[0017] An embodiment of the present invention provides a level conversion circuit for switching from a high level to a low level, wherein an equivalent parasitic capacitance for subsequent low-level logic circuitry is further included between the output node and the ground node.

[0018] Technical effect

[0019] This disclosure proposes a level shifting circuit for high-to-low level conversion. Without increasing power consumption, it effectively reduces the chip area of ​​existing circuits. Furthermore, by incorporating acceleration and clamping protection circuits into the level shifting circuit, it achieves rapid response from high to low and from low to high logic levels without damaging the low-voltage transistors in subsequent low-level logic chips. This satisfies the cascading application requirements of chips with different logic levels in complex multi-chip systems. Attached Figure Description

[0020] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a signal flow diagram illustrating a level shifting circuit used for transitioning from a high level to a low level.

[0022] Figure 2 This illustrates a level shifting circuit that includes a separate resistor voltage divider circuit.

[0023] Figure 3 This is a simulation diagram showing the signal changes of a level shifting circuit that includes a separate resistor voltage divider circuit;

[0024] Figure 4 This is a circuit schematic diagram illustrating a level conversion circuit according to an embodiment of the present disclosure;

[0025] Figure 5 This is a simulation diagram illustrating the signal changes of a level conversion circuit according to an embodiment of the present disclosure; and

[0026] Figure 6 This is a simulation diagram showing signal changes excluding clamping circuits and level conversion circuits. Detailed Implementation

[0027] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “comprising” and “including” and their derivatives mean including but not limited to. The term “or” is inclusive, meaning and / or. The phrase “associated with” and its derivatives mean including, comprising, interconnecting, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposing, proximate, binding or binding to, having, having attributes, having a relationship or being related to, etc. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase “at least one,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0028] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0029] In this patent document, the application combination of transform blocks and the hierarchical division of sub-transform blocks are for illustrative purposes only. Without departing from the scope of this disclosure, the application combination of transform blocks and the hierarchical division of sub-transform blocks can be in different ways.

[0030] The following discussion Figures 1 to 6 The various embodiments used to describe the principles of this disclosure in this patent document are for illustrative purposes only and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged system or device.

[0031] Figure 1 This is a signal flow diagram illustrating a level shifting circuit used for transitioning from a high level to a low level.

[0032] exist Figure 1 In the high-level logic circuit, the components are, for example, high-voltage transistors with a withstand voltage of 3.6V, generating a voltage signal CTRL_IN, which enters the logic level conversion circuit. The logic level conversion circuit converts the level from high to low and generates a voltage signal CTRL_OUT, which enters the low-level logic circuit. The components in the low-level logic circuit are, for example, low-voltage transistors with a withstand voltage of 1.8V.

[0033] Figure 2 This illustrates a level shifting circuit that includes a separate resistor voltage divider circuit.

[0034] like Figure 2 As shown, simple level-shifting circuits for high-to-low level conversion commonly use resistor voltage dividers. This circuit includes series-connected voltage divider resistors R1 and R2, and a parasitic capacitor Cp connected in parallel with resistor R2. This method offers high voltage division accuracy, but when the values ​​of resistors R1 and R2 are small, there will be significant leakage current, increasing circuit power consumption; when the values ​​of resistors R1 and R2 are large, it increases circuit area and cost. Furthermore, simply using resistor voltage dividers limits the speed of voltage transitions. For example, when driving a circuit with a large parasitic capacitor Cp, the level transition time will be very long.

[0035] Figure 3 This is a simulation diagram showing the signal changes of a level shifting circuit that includes a separate resistor voltage divider circuit.

[0036] exist Figure 3 The simulation results for this circuit structure are shown in the figure. When the CTRL_IN voltage jumps from 3.6V to 0V, the response time for CTRL_OUT to jump from 1.8V to 0V is very long, and it can only jump to 1.5V in a short time. Therefore, this circuit may produce bit errors during high-speed level transitions.

[0037] Figure 4 This is a circuit schematic diagram of a level conversion circuit according to an embodiment of the present disclosure.

[0038] exist Figure 4 In the embodiment of the present disclosure, the level conversion circuit includes a voltage divider circuit 101, an acceleration circuit 102, and a clamping protection circuit 103.

[0039] According to an embodiment of this disclosure, the voltage divider circuit 101 includes resistors R11 and R21, and voltage divider diodes D11, D12, D13, D21, D22, and D23. The input voltage CTRL_IN enters the voltage divider circuit 101 of the level conversion circuit through the input node, wherein diodes D11, D12, D13 and D21, D22, and D23 are connected in series between the input node and the ground node, and the six diodes are all of the same size, so that CTRL_IN is divided proportionally. According to an embodiment of this disclosure, resistors R11 and R21 can also be connected in series between D13 and D23 for fine voltage adjustment. After voltage division by the diodes and resistors, the output voltage is output from the output node between resistors R11 and R21. According to an embodiment of this disclosure, the level of the input voltage CTRL_IN is 3.6V, and the level of the output voltage CTRL_OUT is 1.8V.

[0040] The acceleration circuit 102 includes a signal transmission capacitor C1, a bias resistor R1, and a PMOS transistor MP1. Capacitor C1, transistor MP1, and resistor R1 together constitute the acceleration circuit for the level shifting circuit. One end of capacitor C1 is connected to the input node, and the other end is connected to the gate terminal of MP1; one end of resistor R1 is connected to the output node, and the other end is connected to the gate terminal of MP1; the source terminal of transistor MP1 is connected to the output node, and its drain terminal is grounded. Furthermore, the bias resistor R1 has a very large resistance (up to several thousand ohms or tens of thousands of ohms). During normal operation, it provides a DC voltage signal to the gate terminal of MP1, causing MP1 to turn off and preventing leakage. When the logic level switches from high to low, the level of CTRL_IN jumps from 3.6V to 0V. Capacitor C1 is connected to the input node and the gate of MP1, which causes the gate of MP1 to be pulled down quickly in a short time. MP1 is turned on instantly, and the source voltage of MP1 is pulled down to ground at an accelerated speed. That is, the output voltage of the level conversion circuit CTRL_OUT jumps from 1.8V to 0 quickly.

[0041] The clamping protection circuit 103 includes: a signal transmission capacitor C2, a bias resistor R2, a clamping diode D0, and an NMOS transistor MN1.

[0042] Capacitor C2, transistor MN1, resistor R2, and diode D0 together constitute a clamping protection circuit. One end of capacitor C2 is connected to the gate of MP1, and the other end is connected to the gate of MN1. One end of resistor R2 is connected to the gate of MN1, and the other end is grounded. The positive terminal of diode D0 is grounded, and the negative terminal is connected to the gate of MN1. The gate of MN1 is connected to C2, R2, and D0, its drain is connected to the gate of MP1, and its source is grounded. Resistor R2 is a bias resistor, providing a DC voltage signal to the gate of MN1 during normal operation, causing MN1 to turn off and preventing leakage. When the logic level switches from low to high, the level of CTRL_IN jumps from 0V to 3.6V. Due to the introduction of the acceleration circuit, the output voltage CTRL_OUT will experience an overshoot, momentarily exceeding 1.8V, which can damage transistor MP1 and subsequent low-level logic circuits. With the addition of the clamping protection circuit, when the voltage level switches from low to high, capacitor C2 connects to the gate terminals of MP1 and MN1. MN1 will momentarily generate a pull-down signal when it overshoots the gate terminal of MP1, preventing damage to the low-voltage transistor. Since capacitor C2 also generates a coupling signal, the gate terminal of MN1 will be in a negative voltage state. The positive terminal of diode D0 is grounded, and the negative terminal is connected to the gate terminal of MN1, clamping the gate terminal of MN1 and protecting transistor MN1.

[0043] According to embodiments of this disclosure, the level conversion circuit may further include a parasitic capacitance Cp, which is the equivalent parasitic capacitance of the input terminal of the subsequent low-level logic circuit that the CTRL_OUT signal needs to drive.

[0044] According to an embodiment of this disclosure, after the CTRL_IN signal is divided by a combination of resistors and diodes, the high-level voltage of the DC operating point changes from a logic voltage of 3.6V to 1.8V.

[0045] Figure 5 This is a simulation diagram of signal changes in a level conversion circuit including a clamping circuit according to an embodiment of the present disclosure.

[0046] exist Figure 5 The simulation results of the level shifting circuit, including the clamping circuit, are shown. When the voltage signal CTRL_IN generated by the high-level logic circuit jumps from a high level of 3.6V to a low level of 0V, capacitor C1 transiently charges and discharges. Due to the large resistance of the bias resistor R1, the gate terminal of transistor MP1 is rapidly pulled down in the transient state, meaning the output voltage CTRL_OUT of the level shifting circuit rapidly jumps from 1.8V to 0V. At this time, the NMOS transistor MN1 in the clamping protection circuit is in the off state and does not affect the circuit's accelerated pull-down.

[0047] When the output signal CTRL_IN of the high-level logic circuit transitions from low level 0V to high level 3.6V, such as Figure 5 As shown by point M3 in the diagram, capacitor C2 connects the gate terminals of MP1 and MN1. When MN1 overshoots at the gate terminal of MP1, it momentarily generates a pull-down signal to prevent damage to the low-voltage transistor. Since capacitor C2 also generates a coupling signal, the gate terminal of MN1 will be in a negative voltage state. The positive terminal of diode D0 is grounded, and the negative terminal is connected to the gate terminal of MN1, clamping the gate terminal of transistor MN1 and protecting it. This ensures that when CTRL_IN transitions from low to high, the output signal CTRL_OUT responds quickly without overshoot.

[0048] Figure 6 This is a simulation diagram showing the signal changes of a level conversion circuit excluding the clamping circuit.

[0049] exist Figure 6 The simulation results of the level shifting circuit excluding the clamping circuit are shown. When the output signal CTRL_IN of the high-level logic circuit transitions from low level 0V to high level 3.6V, without the clamping protection circuit capacitor C2, transistor MN1, resistor R2, and diode D0, the output voltage CTRL_OUT will overshoot to 2.1V when the logic level switches from low to high due to the introduction of the acceleration circuit. Figure 6 As indicated by point M0, the voltage momentarily exceeds 1.8V. Since both the level conversion circuit and the subsequent low-level logic circuit use low-voltage transistors, voltage overshoot can damage the circuit.

[0050] The text and accompanying drawings are provided by way of example only to aid in understanding this disclosure. They should not be construed as limiting the scope of this disclosure in any way. Although certain embodiments and examples have been provided, it will be apparent to those skilled in the art, based on the content disclosed herein, that changes may be made to the illustrated embodiments and examples without departing from the scope of this disclosure.

[0051] This disclosure proposes a level shifting circuit for high-to-low level conversion. Without increasing power consumption, it effectively reduces the chip area of ​​existing circuits. Furthermore, by incorporating acceleration and clamping protection circuits into the level shifting circuit, it achieves rapid response from high to low and from low to high logic levels without damaging the low-voltage transistors in subsequent low-level logic chips. This satisfies the cascading application requirements of chips with different logic levels in complex multi-chip systems.

[0052] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0053] Any description in this invention should not be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

Claims

1. A level shifter circuit for converting from high level to low level, the level shifter circuit comprising: a voltage dividing circuit configured to divide an input voltage to output an output voltage from an output node; an acceleration circuit configured to quickly switch the output voltage when the input voltage switches by quickly switching a first transistor to on through a first capacitor; a clamping protection circuit configured to prevent the output voltage from jumping up when the input voltage switches, wherein one end of the first capacitor is connected to an input node of the voltage dividing circuit and the other end is connected to a gate terminal of the first transistor, wherein a source and a drain of the first transistor are connected to the output node and a ground node respectively, and a gate thereof is connected to one end of the first capacitor, and wherein the acceleration circuit further comprises a first resistor connected between the output node and the gate terminal of the first transistor. 2.The level shifter circuit of claim 1, wherein the voltage dividing circuit comprises N voltage dividing diodes connected in series between an input node receiving the input voltage and a ground node, wherein N is a natural number greater than or equal to 2. 3.The level shifter circuit of claim 2, wherein the voltage dividing circuit further comprises M resistors connected in series into the N voltage dividing diodes for fine adjustment of the voltage dividing circuit, wherein M is a natural number greater than or equal to 0. 4.The level shifter circuit of claim 3, wherein any point in the N voltage dividing diodes and the M resistors can be as the output node. 5.The level shifter circuit of claim 1, wherein a resistance value of the first resistor is greater than a first threshold value.

6. The level shifting circuit of claim 1, wherein, the clamping protection circuit comprises a second transistor and a second capacitor, wherein a gate of the second transistor is connected to a gate of the first transistor through the second capacitor, and is configured to generate a pull-down signal when the gate of the first transistor jumps up when the level switches from low to high.

7. The level shifting circuit of claim 6, wherein, the clamping protection circuit further comprises a second resistor, wherein the second resistor is connected between the gate of the second transistor and the ground node, and acts as a bias resistor to prevent the second transistor from leaking when working normally.

8. The level shifting circuit of claim 6, wherein, the clamping protection circuit further comprises a clamping diode, wherein a positive terminal of the clamping diode is grounded, and a negative terminal thereof is connected to the gate of the second transistor to generate a clamping effect on the gate terminal of the second transistor. 9.The level shifter circuit of claim 1, wherein an equivalent parasitic capacitance for a low level logic circuit in a later stage is further included between the output node and the ground node.

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