Systems and methods for modeling and simulation of on-die capacitors

Abstract

The present disclosure relates to a method and system for analyzing an integrated circuit. The method includes performing a first resistor capacitor (RC) extraction process on a power receiving circuit and generating a first RC model. The method also includes scanning a netlist of a power distribution network that is electrically connected to the power receiving circuit. The method also includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method also includes performing a second RC extraction process on the selection of circuit elements and generating a second RC model. The method also includes performing a simulation process on the power receiving circuit and the power distribution network using the first RC model and the second RC model.

Description

BACKGROUND

[0001] Semiconductor devices are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. Advances in semiconductor manufacturing technology have enabled chips to use less power per transistor, however, as device densities have increased dramatically, chips produced with newer processes typically use more power. In addition, increasing the functionality of a single chip can also result in an increase in power consumption. Ensuring power integrity is therefore increasingly challenging for chip design and packaging. SUMMARY

[0002] Embodiments of a method for simulating a power receiving circuit and a system for performing the method are described in the present disclosure.

[0003] In some embodiments, a method for analyzing an integrated circuit can include performing a first resistor capacitor (RC) extraction process on a power receiving circuit to generate a first RC model, and scanning a netlist of a power distribution network. The power distribution network is electrically connected to the power receiving circuit. The method can also include determining a selection of circuit elements of the power distribution network based on a predetermined criterion. The method can also include performing a second RC extraction process on the selection of circuit elements to generate a second RC model. The method can also include performing a simulation process on the power receiving circuit and the power distribution network using the first RC model and the second RC model.

[0004] In some embodiments, a method for analyzing an integrated circuit can include performing a first resistor capacitor (RC) extraction process on a power receiving circuit and generating a first RC model. The method can also include selecting a memory circuit and a group of circuit elements from a power distribution network. The method can also include performing a second RC extraction process on the selected group of circuit elements and the memory circuit to generate a second RC model. The method can also include performing a simulation process on the power receiving circuit, the power distribution network, and the memory circuit using the first RC model and the second RC model.

[0005] In some embodiments, a computer system includes a processor and a memory having computer program code stored thereon. The processor is configured to execute the computer program code in the memory to implement the above-described methods.

[0006] In some embodiments, a non-transitory computer-readable medium containing a computer-executable program for, when executed by a processor, implementing a method for analyzing a signal waveform generated by an integrated circuit, the method can include performing a first resistor capacitor (RC) extraction process on a power receiving circuit and generating a first RC model. The method can also include scanning a netlist of a power distribution network that is electrically connected to the power receiving circuit. The method can also include determining a selection of circuit elements of the power distribution network based on a predetermined criterion. The method can also include performing a second RC extraction process on the selection of circuit elements and generating a second RC model. The method can also include performing a simulation process on the power receiving circuit and the power distribution network using the first RC model and the second RC model. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0008] Figure 1 A schematic diagram of an exemplary memory device is shown in accordance with some embodiments of the present disclosure.

[0009] Figure 2 A schematic diagram of a memory circuit diagram is shown in accordance with some embodiments of the present disclosure.

[0010] Figure 3 A schematic layout diagram of an exemplary power receiving circuit is shown in accordance with some embodiments of the present disclosure.

[0011] Figure 4A A schematic diagram of an exemplary modeling and simulation system is shown in accordance with some embodiments of the present disclosure.

[0012] Figure 4B A block diagram of an exemplary computer system implementing an exemplary modeling and simulation system is shown in accordance with some embodiments of the present disclosure.

[0013] Figure 5 An exemplary method of analyzing and simulating an integrated circuit is shown in accordance with some embodiments of the present disclosure.

[0014] The features and advantages of the present application will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout the several views. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is identified by the left-most digit(s) in the reference number.

[0015] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements can be employed without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be employed in a variety of other applications.

[0017] Note that references to “one embodiment,” “an embodiment,” “example embodiment,” “some embodiments,” etc., indicate that the described embodiment can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, the

[0018] Generally, the terminology can be understood at least in part from usage of the same in the context of the specification. For example, terms such as “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms such as “a” or “the” again, depending at least in part upon context, can be understood to convey a singular usage or to convey a plural usage, and it can be understood that such terms are used concretely, depending on context. Further, the term “based on” can be understood as not necessarily intended to convey an exclusive set of factors, but, instead, can allow for existence of additional factors not necessarily expressly described, again, depending on context.

[0019] Depending on the particular technical node, the term “about” can indicate a value of a given quantity that varies by, e.g., 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0020] Managing power integrity refers to providing a stable power supply that can accommodate fluctuations in current drawn by integrated circuits on a chip. Stable power supply is critical for proper operation of high frequency (e.g., high switching rate) devices (e.g., memory devices). Power receiving circuits are formed using integrated circuits containing semiconductor devices such as capacitors, resistors, transistors, etc. Design flows for designing integrated circuits (e.g., power circuits) typically involve many stages. Transistor-level circuits are designed and circuit-level simulations are performed thereon to ensure that the integrated circuits meet predetermined specifications. For example, electrical analysis is performed to verify and check the electrical behavior and performance of the circuit design. Analysis can be performed on the circuit design to create estimates of capacitances and resistances according to a process known as parasitic resistance and capacitance (RC) extraction. RC extraction tools include software and / or hardware that convert geometric descriptions of conductor and insulator objects or other shapes described in an integrated circuit design file or database into associated parasitic capacitance values.

[0021] Memory devices, such as volatile and non-volatile memory devices, require one or more power receiving circuits to operate. For example, power receiving circuits for memory devices include modules that receive external power supplies and provide power for read and / or write functions to operate physical memory cells, as well as modules that provide power for operating input / output (I / O) terminals and data buses for transferring data. For example, three-dimensional (3D) NAND flash memory devices utilize power supplied through power receiving circuits (e.g., pad regions connected directly to external power supply circuits) to perform tasks such as data transfer and storage. As the development of memory devices (e.g., 3D NAND flash memory) progresses toward high-density and high-capacity memory cells, the need for stable power supply continues to increase. However, as power supply circuits become more complex and larger in scale, the design and simulation of power receiving circuits have become increasingly challenging. Power distribution systems can include a large number of passive circuit components, such as on-die capacitors, resistors, inductors, etc. Additionally, the capacity of memory circuits has also greatly increased. As a result, the simulation process of the entire power distribution network for memory devices can be extremely time-consuming and consume a large amount of computing resources. Therefore, there is a need to improve the design and simulation efficiency of power circuit design in memory devices.

[0022] Systems and methods for improving efficiency of modeling and simulation of a power distribution network of a memory device without sacrificing simulation accuracy are provided in accordance with various embodiments of the present disclosure. Simulation results of circuit components of a power distribution network, such as on-die capacitors, can have different high frequency components and low frequency components. Different components can have different impacts on circuit simulation results. For example, high frequency response of on-die capacitors is critical for accurately simulating integrated circuits of 3D NAND memory devices. The systems and methods disclosed herein can reduce simulation complexity by constructing a simplified first order RC model for internal circuits and power distribution networks. The simplified model is added to a netlist for subsequent simulation. In some embodiments, a netlist includes a list of electronic components of a circuit and a list of terminals / nodes to which the components can be connected. The simplified model provides an equivalent on-die capacitor response function that varies with respect to an input frequency. The response function can be used by a simulation process to provide simulation results in a low frequency range without sacrificing simulation accuracy, which in turn results in reduction of simulation time and computing resources. The embodiments described herein can also be applied to simulation of any other suitable integrated circuits.

[0023] Figure 1 A schematic diagram of an exemplary memory device 100 is shown in accordance with some embodiments of the present disclosure. The memory device 100 is provided with an external power supply network 102. The memory device 100 can include a pad region 104, a power distribution network 106, internal circuits 120, and control circuits 126. The internal circuits 120 can be memory circuits including a memory array 128 and peripheral circuits 130. The peripheral circuits 130 can include page buffers 122, word line (WL) drivers 124, and control circuits 126. Other components can be included in the memory device 100 and are omitted from Figure 1 for simplicity. Figure 1 The circuit components shown in Figure 1 can be formed using standard cells including a set of transistors and interconnect structures.

[0024] The external power supply network 102 can be used to provide power supply to other components of the memory device 100. For example, the external power supply network 102 can include terminals for outputting power supply voltages (e.g., V cc , V ccq , and a ground voltage V ss ) in order to supply various operating powers to the internal circuits 120. The power supply voltage V cc may be a circuit power supply voltage provided as an operating power supply of core electronics of a chip, and can be any suitable voltage, such as a voltage between about 1.5 V and about 5 V. The power supply voltage V ccqmay be provided to circuit components used for data transfer, such as output drivers or input / output (I / O) data buses. ccq may be any suitable voltage, such as a voltage between about 1.2 V and about 3.3 V.

[0025] The pad region 104 can be referred to as a power receiving circuit, which is an integrated circuit that receives an external power supply and transfers the received external power supply to a power distribution network. The pad region 104 can also include suitable test ports, interconnects, and wires. The pad region 104 can include power supply terminals (e.g., conductive pads) that receive power from the external power supply network 102 and provide a power supply to the power distribution network 106. The pad region 104 can include conductive pads / regions configured to receive wire bonds for connection to the external power supply network. The conductive pads / regions can be formed of a conductive material, such as copper, aluminum, cobalt, tungsten, any suitable conductive material, and / or combinations thereof.

[0026] The power distribution network 106 is an electrical grid that delivers supply voltages and ground voltages from the pad region 104 to all components of the memory device 100. The power distribution network 106 can include various circuit components, including passive circuit components such as resistors, capacitors, inductors, and active circuit components such as transistors, diodes, generators, current sources, voltage sources, and the like.

[0027] The internal circuit 120 includes circuit components configured to perform data processing and storage. For example, the internal circuit 120 can include a memory array 128, and peripheral circuitry 130 including a page buffer 122, a WL driver 124, and a control circuit 126. Each of the above circuit components requires a stable power supply to perform at optimal device operating levels.

[0028] The page buffer 122 can store data before it is written to a relevant portion of the memory array 128, or store data read from the memory array 128 before it is transferred to the control circuit 126.

[0029] The WL drivers 124 can include local word line drivers and global word line drivers. For example, in high-density memory of a 3D NAND memory device, the array of memory cells is divided into blocks of memory cells. Each block can include a local word line that requires a corresponding local word line driver. The global word line drivers power a set of global word lines for a column of blocks in the array. Each word line in the set of global word lines is set depending on the operation applied to the selected block (e.g., read, program, and erase for high-density devices). The word line drivers can include pass transistors for passing voltage from the global word lines to the local word lines. Some word line drivers can require high voltage, and thus it is critical for the WL drivers 124 to have access to a stable power source to achieve optimal device operating levels.

[0030] The control circuitry 126 can be a processing unit that includes control logic or processing logic to process data prior to transferring the data to the memory array 128 or to process data received from the memory array 128. The control circuitry 126 can also be configured to control the operation of the page buffer 122 and the WL drivers 124. In some embodiments, the control circuitry 126 can include an array of logic gates. The control circuitry 126 can also include any suitable type of general- or specific- purpose microprocessor, digital signal processor, or microcontroller. The control circuitry 126 can be configured as a separate processor module dedicated to performing one or more specific operations. Alternatively, the control circuitry 126 can be configured as a shared processor module used to perform other operations unrelated to one or more specific operations disclosed herein.

[0031] The memory array 128 can include one or more memory planes, each of which can include a plurality of memory blocks. The same and concurrent operations can occur on each memory plane. The size of a memory block can be a megabyte (MB), and the memory block can be the smallest size to perform an erase operation. Each memory block can include a plurality of memory cells, each of which can be addressed by interconnections such as bit lines and word lines. The bit lines and word lines can be laid out perpendicularly (e.g., in rows and columns, respectively), forming an array of metal lines. A memory block can also be referred to as a “memory array” or “array.” A memory array is the core area in a memory device that performs the storage function.

[0032] The peripheral circuitry 130 can contain many digital, analog, and / or mixed-signal circuits to support the functionality of the memory array 128. In some embodiments, the peripheral circuitry 130 can include one or more of decoders (e.g., row decoders and column decoders), charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) needed in the circuitry.

[0033] In some embodiments, the peripheral circuit 130 can be formed by CMOS technology. In some embodiments, the process of forming the peripheral circuit 130 can include forming a high voltage region and a low voltage region. In some embodiments, P-wells, N-wells, oxide layers can be formed in the high voltage region and the low voltage region. Shallow trench isolation (STI) can be used to provide electrical isolation between the high voltage region and the low voltage region. In addition, polysilicon gate structures, silicides, source / drain regions, and other suitable structures can be formed in the peripheral circuit 130.

[0034] Figure 2 A schematic diagram of a circuit 200 is shown in accordance with some embodiments of the disclosure. The circuit 200 includes a schematic diagram of the pad region 104, the power distribution network 106, and the internal circuit 120. The circuit 200 can include additional components, and for simplicity is omitted from Figure 2 the detailed description. The circuit 200 is provided merely to illustrate the circuit components of the memory device 100, and actual circuit designs can differ or vary.

[0035] The pad region 104 includes one or more terminals for receiving a supply of electrical power from an external power source, such as the external power source network 102. In some embodiments, the pad region 104 includes at least a terminal 202 for receiving a ground voltage reference V ss and a terminal 204 for receiving a supply voltage V ccq . An integrated circuit, such as a memory chip, can include more than one power supply. For example, a power supply for the memory device 100 can include a first voltage power supply V cc for powering the core electronics of the chip and a second voltage V ccq for powering the output drivers of the chip. The output drivers transmit output signals to other chips of a system in which the chip is placed, and draw a significant amount of current and power to do so. The pad region 104 also includes various passive circuit elements, such as a resistor 206 and a capacitor 208. The resistor and capacitor form part of an RC network, which is a circuit containing resistors and capacitors. It can be driven by a voltage source or a current source, and these will produce different responses.

[0036] The power distribution network 106 can include an electrical grid composed of resistors and capacitors. For example, the power distribution network 106 includes a resistor 216 and a capacitor 218, and is configured to transmit a supply of electrical power from the terminal 204. In some embodiments, the capacitor 218 can be a decoupling capacitor connected to the ground reference voltage. In some embodiments, the power distribution network 106 is configured for a voltage power supply V ccqpower bus. In some embodiments, the power distribution network can also include a grid for other power sources, such as a battery connected to terminal 212 and omitted from Figure 2 V ss grid. Power distribution network 106 can include a larger number of circuit components than pad region 104 and be much larger in scale. Other suitable circuit components can be included in power distribution network 106 and are omitted from Figure 2 for simplicity.

[0037] Internal circuit 120 can include resistors 226 and capacitors 228, among other circuit components and blocks of devices. For example, internal circuit 120 can include amplifiers 221, comparators 222, and power terminals 224. Internal circuit 120 also includes memory circuit 240, which includes suitable circuit components such as page buffer 122, WL driver 124, control circuit 126, memory array 128, and peripheral circuit 130 described in Figure 1 In some embodiments, memory circuit 240 can be a 3D NAND memory circuit. For simplicity, components of memory circuit 240 and any additional suitable circuit components are not shown in Figure 2

[0038] The resistors and capacitors placed in pad region 104, power distribution network 106, and internal circuit 120 form a large-scale RC network. Including all of the resistors and capacitors in the netlist without simplification would require a large amount of computational resources during the simulation phase of the IC design. Methods and systems for simplifying the modeling and simulation of the RC network described in Figures 3-5 are described below in relation to Figure 2

[0039] Figure 3 A schematic layout of a die pad 300 is shown in accordance with some embodiments of the present disclosure. Die pad 300 can be with respect to Figure 2 ​​A portion of the described pad area 104. The die pad 300 can include a circuit base 301, test ports 302, wires 304, terminals 306, and interconnects 308. One or more test ports 302 are formed on the circuit base 301 for connecting the memory device 100 to a computer system configured to perform circuit analysis and simulation. The wires 304 can be used to conduct electrical signals between circuit components on the die pad 300. In some embodiments, the wires 304 can be wire bonds. The terminals 306 can be connection ports that provide electrical connections to circuit components of the memory device 100 (e.g., the power distribution network 106 and the internal circuit 120). The interconnects 308 can be vertical interconnects that provide electrical connections to circuit components formed on various device layers. In some embodiments, the interconnects 308 can be through-silicon vias (TSVs).

[0040] Figure 4A A schematic diagram of an example modeling and simulation system 400 is shown in accordance with some embodiments, and Figure 4B A block diagram of an example computer system implementing the modeling and simulation system 400 is shown in accordance with some embodiments. Additional suitable components can be included in Figure 4A and Figure 4B and are not shown for simplicity.

[0041] Figure 4A The modeling and simulation system 400 shown in FIG. 4 can include design constraints 402, a cell list 404, a cell library 406, an I / O (input / output) configuration table 408, a modeling and analysis unit 420, and a simulator 430. Other components can be included in the modeling and simulation system 400 and are omitted for simplicity. The modeling and simulation system can be executed by a processor in a computer and stored in a non-transitory computer-readable storage medium in the computer. The non-transitory computer-readable storage medium can be a hard drive, an optical disk, a random access memory, a read-only memory, or another non-volatile memory. The modeling and analysis unit 420 includes at least one processor and at least one memory storing instructions. When executed by the at least one processor, the instructions cause the at least one processor to perform operations.

[0042] Figure 4A The design constraints 402 shown in FIG. 4 contain rules applicable to integrated circuit designs. For example, the design constraints 402 can include design rules, such as requirements or parameters related to desired system specifications, budgets, requirements, mode settings, and the like. The design constraints 402 can be stored in a storage medium and can be accessed by other components of the modeling and simulation system 400. The design constraints can be logical values or analog values. In some embodiments, the design constraints can include input and output constraints for input and output pins of standard cells.

[0043] Figure 4A The cell list 404 and the cell library 406 shown in FIG. 4 contain standard cell information for use in integrated circuit design. The cell list 404 can include a sorted list of pointers to all cells stored in the cell library 406, with the cells preferably sorted by one or more categories. The cell library 406 can include a collection of standard cells in various formats, such as a netlist format for use in a Simulation Program with Integrated Circuit Emphasis (SPICE) simulation process or any other appropriate simulation process.

[0044] Figure 4A The I / O configuration table 408 shown in FIG. 4 includes a list of input pins and output pins for each cell in the cell list 404. The I / O configuration table 408 can be generated by an I / O configuration table script from the cell list 404 and modified by user input received from an input device such as a keyboard, touch screen, microphone, etc. The I / O configuration table 408 can be used to generate input stimuli and other configuration files for use in subsequent simulation.

[0045] Figure 4A The modeling and analysis cell 420 shown in FIG. 4 can perform various tasks, such as performing a resistance and capacitance (RC) extraction process for an IC circuit, constructing a circuit model based on the extracted RC information, and / or providing an equivalent impedance function for a circuit element. Electronic circuit extraction refers to a process of converting an integrated circuit back into a netlist of circuit elements that it is intended to represent. The extracted circuit can be used for various purposes, such as circuit simulation, timing analysis, signal integrity analysis, power integrity analysis, logic-to-layout comparison, etc. RC extraction results are especially necessary for producing reliable and accurate simulation results for power integrity analysis of memory circuits.

[0046] The RC extraction process can be performed on a component of an IC circuit or on the entire IC circuit. The RC extraction process can be performed by a suitable tool stored in the modeling and analysis cell 420, such as an electronic design automation (EDA) tool. The RC extraction is performed to determine various circuit parameters, such as the parasitic resistance and parasitic capacitance of circuit components. In some embodiments, the RC extraction is performed to obtain information such as about Figure 2The parameters of the resistors and capacitors in the power supply circuit of the described pad region 104 and power distribution network 106. In some embodiments, RC extraction is also performed on the internal circuit 120. RC extraction can obtain information about coupling capacitance as well as parasitic capacitance and their corresponding frequency responses. Parasitic capacitance arises due to the pattern configuration in the circuit layout and affects the device performance. In some embodiments, a technology file is used to extract the parasitic parameters. The parameters from the extracted full and reduced RC models are added to the netlist stored in the cell library 406 to produce a modified netlist. In some embodiments, the modeling and analysis unit is configured to produce frequency dependent S, Z, and Y parameters for different components of the memory circuit. For example, the simulator 430 can be configured to determine the effective capacitance of components of the power supply network in response to different operating frequencies.

[0047] Figure 4A The simulator 430 shown in FIG. 4 is configured to replicate the behavior of an actual integrated circuit by using the mathematical models constructed by the modeling and analysis unit 420. The simulator 430 is configured to perform a series of simulation operations on the netlist from one or more circuit components, such as the pad region 104, the power distribution network 106, and the internal circuit 120. The simulator 430 can obtain standard cell information such as cell netlists from the cell list 404 and the cell library 406 and perform circuit level simulation to produce simulation results. In some embodiments, the simulator 430 is configured to use any suitable tool to generate timing reports, perform timing retention optimization, and / or perform routing with timing center.

[0048] Figure 4B An exemplary computer system 450 for implementing an exemplary modeling and simulation system, such as the modeling and simulation system 400, in accordance with embodiments of the present disclosure is shown. With reference to Figure 4B , the computer system 450 can include at least one processor 455, a communication interface 460, and a memory 465. The memory 465 can be configured to store one or more computer instructions that, when executed by the processor 455, can cause the processor 455 to perform various operations disclosed herein. The memory 465 can be any non-transitory type mass storage device, such as a volatile or non-volatile, magnetic, semiconductor, tape-based, optical, removable, non-removable, or other type of storage device or tangible computer readable medium, including but not limited to ROM, flash memory, dynamic RAM, and static RAM.

[0049] The processor 455 can be configured to perform operations in accordance with instructions stored in the memory 465. The processor 455 can include any suitable type of general purpose or special purpose microprocessor, digital signal processor, or microcontroller. The processor 455 can be configured as a separate processor module dedicated to performing one or more particular operations. Alternatively, the processor 455 can be configured as a shared processor module used to perform other operations unrelated to one or more particular operations disclosed herein. The processor 455 can include various units or modules for performing circuit modeling and simulation. For example, the processor 455 can include a modeling and analysis module, a circuit simulator, an I / O configuration module, and / or any suitable module for receiving circuit information and performing circuit simulation and analysis. For example, the processor 455 can include a processor module dedicated to performing operations by the I / O configuration module 408, the modeling and analysis unit 420, the simulator 430, and any other suitable component of the modeling and simulation system 400.

[0050] The communication interface 460 can include any type of communications adapter, such as an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, the communication interface 460 can include a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links can also be implemented by the communication interface 460. In such implementations, the communication interface 460 can send and receive electrical, electromagnetic or optical signals that carry digital data streams representing various types of information. The network can include a cellular communication network, a wireless local area network (WLAN), a wide area network (WAN), etc. In some embodiments, the communication interface 460 can also include an input / output interface, such as a display interface (e.g., HDMI, DVI, VGA, etc.), an audio interface, a keyboard interface, a mouse interface, a printer interface, a touchscreen interface, etc.

[0051] The communication interface 460 can be configured to exchange information between the computer system 450 and one or more other systems / devices. For example, the communication interface 460 can communicate with a database 470, which can store information related to integrated circuit designs, standard cell information, routing rules, etc. In some embodiments, the database 470 can also store information related to cell lists, cell libraries, device constraints, or other suitable information related to the design and simulation of integrated circuits. In some embodiments, the processor 455 can receive information stored in the database 470 through the communication interface 460.

[0052] Display 475 can be coupled to computer system 450 through communication interface 460. Display 475 can include an LCD, LED, plasma display, or any other type of display, and provide a GUI rendered on the display for user input and data portrayal. Display 475 can be formed of different types of materials, such as plastic or glass, and can be touch sensitive to receive input from a user. For example, display 475 can include a substantially rigid or substantially flexible touch sensitive material. In some embodiments, information about circuit simulation results, thresholds, model information, and / or user input requests can be displayed on display 475. In some embodiments, a warning can be triggered and displayed on display 475 after completion of one or more operations performed by processor 455.

[0053] Terminal device 480 can be coupled to computer system 450 through communication interface 460. Terminal device 480 can include a desktop computer, workstation, laptop computer, mobile phone, tablet computer, or any other type of device configured to perform computing tasks. In some embodiments, a user can use terminal device 480 to control computer system 450, for example, to initiate, monitor, or terminate operations related to reviewing and analyzing circuit simulation results. In some embodiments, terminal device 480 can receive information about circuit simulation and analysis results generated by computer system 450. In some embodiments, terminal device 480 can receive notifications or warnings indicating the status of operations performed by processor 455.

[0054] One or more of database 470, display 475, and / or terminal device 480 can be part of computer system 450, and can be co-located with computer system 450, or located remotely with respect to computer system 450, and in communication with computer system 450 via a network or any suitable type of communication link.

[0055] Figure 5 is a flowchart of an exemplary method 500 for modeling and simulating a power network in a memory device, in accordance with some embodiments of the present disclosure. The operations of method 500 can be performed in different orders and / or variations, and method 500 can include more operations not described for the sake of brevity. Any reasonable application of method 500 in circuit simulation is within the scope of the present disclosure.

[0056] In operation 510, according to some embodiments of this disclosure, an initial simulation process is performed to obtain the operating operation of the power receiving circuit. Referring to FIG4, the simulator 430 can be configured to retrieve standard cell information of one or more circuits of the memory device. For example, the simulator 430 can retrieve elements of the power receiving circuit (e.g., pad area 104) from cell list 404 and cell library 406. For ease of description, the power receiving circuit in this disclosure refers to a circuit structure that receives power directly from an external power supply circuit. The circuit response during operation startup may differ from the circuit response during normal operation. Therefore, an initial simulation process is performed to simulate the operating parameters of the circuit during normal operation. In some embodiments, the initial simulation process performed on pad area 104 can avoid initial circuit conditions that may affect the determination of the effective resistance of pad area 104.

[0057] In operation 520, according to some embodiments of this disclosure, the modeling and analysis system can be configured to add suitable terminals to the power network layout. Modeling and analysis unit 420 is configured to add terminals to the power network layout for various reasons. (See reference...) Figure 3 As shown in Figure 4, the modeling and analysis unit 420 is configured to add vias 308 to the layout of the die pads 300 to resemble the final power bus layout. Vias 308 can be used to provide access to, for example... Figure 2 The V mentioned in ccq Electrical connections in the power distribution network. In some embodiments, any suitable tags and / or pins can be added to the information regarding... Figure 3 The described die pad 300, for example, can have pins added to test ports and / or terminals 306, allowing external power to be applied to the simulation. In some embodiments, the modeling and analysis unit 420 can be configured to add pins to the power distribution network, allowing the simulator 430 to incorporate a simplified RC model into the simulation process via the added pins.

[0058] In operation 530, according to some embodiments of this disclosure, the modeling and analysis system is configured to extract complete RC models of the circuit components of the power receiving circuit. (See reference...) Figure 3As with FIG. 4, the modeling and analysis unit 420 is configured to perform RC extraction of the power receiving circuit (e.g., the pad region 104) in both the low frequency spectrum (e.g., between approximately 100 MHz and approximately 600 MHz) and the high frequency spectrum (e.g., between approximately 600 MHz and approximately 1 GHz). Because the circuit size of the pad region 104 is relatively small compared to the power distribution network 106 and / or the internal circuit 120, it is feasible to extract a complete netlist of the circuit components of the pad region. The circuit components of the pad region 104 (e.g., the resistors 206 and the capacitors 208) are all included in the RC extraction process and converted into a netlist that is stored for subsequent simulation processes. In some embodiments, the capacitors 208 can include equivalent parasitic capacitors. In some embodiments, the modeling and analysis unit 420 is configured to perform the RC extraction process using any suitable extraction process. For example, the modeling and analysis unit 420 can utilize a model-based RC extraction product to perform the RC extraction process, such as the Quality Resistor Capacitance (QRC) product available from Cadence Design Systems, Inc. of San Jose, California. The RC extraction results can be stored in any appropriate format or in any appropriate medium. For example, the analysis results can be stored in SPEF, DSPF, or SPICE format, as would be apparent to one skilled in the semiconductor arts.

[0059] At operation 540, according to some embodiments of the present disclosure, the modeling and analysis system is configured to extract a simplified RC model of the circuit components of the power distribution network and the internal circuit. To provide fast and accurate power integrity and signal integrity (PI / SI) analysis for the large-scale power distribution network 106 and the internal circuit 120, Figure 4A The modeling and analysis unit 420 described in FIG. 4 is configured to perform an analysis process to identify circuit elements that satisfy predetermined criteria and perform an RC extraction process on the identified circuit elements to produce a simplified netlist. The modeling and analysis unit 420 can receive information of the circuit elements from the cell list 404 and the cell library 406 and proceed to scan the circuit elements to identify elements that satisfy one or more predetermined criteria. In some embodiments, the identified elements are included in the RC extraction process. In some embodiments, the identified elements are excluded from the RC extraction process. The predetermined criteria can include, but are not limited to, maximum or minimum resistance values, maximum or minimum capacitance values, and any suitable criteria. For example, the modeling and analysis unit 420 compares the capacitance of a circuit element (e.g., a capacitor) to a capacitance threshold and, in response to the capacitance being below the capacitance threshold, excludes the circuit element from the RC extraction process. Conversely, if the capacitance of the circuit element exceeds the capacitance threshold, the circuit element is included in the RC extraction process.

[0060] Further, the modeling and analysis unit 420 can be configured to perform an RC extraction process on the identified circuit elements and generate one or more sets of RC extraction results, referred to as a simplified RC extraction result or a simplified netlist. In some embodiments, the RC model extracted from the pad region 104 can be a complete RC model that includes all circuit elements of the pad region 104. The RC model extracted from the pad region 104 can be used as an RC model in a high frequency spectrum for memory device simulation. In some embodiments, the RC model extracted from the power distribution network 106 can be a simplified model in which certain circuit elements that meet predetermined criteria are included in the RC extraction process. In some embodiments, an RC extraction process is also performed on the internal circuit 120 and a simplified RC model is generated for the internal circuit 120. The RC extraction process for the internal circuit 120 can be part of the RC extraction process for the power distribution network 106. In some embodiments, the above-described RC extraction processes can be performed separately. In some embodiments, the complete RC model of the pad region 104 and the simplified RC model of the power distribution network 106 and / or the internal circuit 120 are used as a comprehensive RC model in a high frequency spectrum for memory device simulation.

[0061] The RC extraction process can be limited to a first order derivative of the circuit modeling and configured to exclude derivatives higher than the first order to provide fast analysis and simulation. For example, the RC extraction process excludes second order or higher order derivatives of the RC model. The modeling and analysis unit 420 can be configured to include frequency dependent S, Z, and Y parameters for the pad region 104, the power distribution network 106, the internal circuit 120, and / or any other suitable circuit of the memory device.

[0062] According to some embodiments of the disclosure, the modeling and analysis unit 420 can be configured to add the RC models of the circuit components to the cell library. For example, the extracted complete and simplified RC models are added to the netlist and stored in the cell library 406.

[0063] At operation 550, according to some embodiments of the disclosure, the simulator is configured to perform simulation on the memory device circuit using the RC models. Referring to FIG. 4, the simulator 430 can be configured to receive either or both of the complete and simplified RC models from the cell list 404 and the cell library 406. In some embodiments, the simulator 430 can receive the RC models directly from the modeling and analysis unit 420. In some embodiments, the simulator 430 is configured to simulate the circuit response based on the received RC models. In some embodiments, the simulator 430 can generate the real and imaginary parts of the memory circuit impedance waveform. The simulator 430 can also be configured to provide the effective capacitance of the on-die capacitor based on the imaginary part of the impedance.

[0064] Systems and methods for efficiently modeling and simulating power distribution networks for memory devices without sacrificing simulation accuracy are provided in accordance with various embodiments of the present disclosure. The systems and methods disclosed herein can reduce simulation complexity by constructing a simplified first order RC modeling for internal circuitry and power distribution networks. The simplified model is added to the netlist for subsequent simulation. The simplified model provides an equivalent on-die capacitor frequency dependent response function. The response function can be used by the simulation process to provide simulation results in the low frequency range without sacrificing simulation accuracy, which in turn results in a reduction in simulation time and computational resources.

[0065] The foregoing description of specific embodiments of the present disclosure will so fully reveal the general nature of the present disclosure that others can modify and / or adjust such embodiments for various applications without departing from the general concept thereof. Consequently, all such modifications and / or adjustments are intended to be within the scope of the disclosed embodiments. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in the art in light of the teachings and guidance.

[0066] Embodiments of the present disclosure have been described above by way of functional building blocks illustrating the implementation of specified functions and relationships of the various embodiments with the addition of various embodiments. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships of the alternatives are

[0067] The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0068] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A method for analyzing an integrated circuit, comprising: performing a first resistor capacitor (RC) extraction process on a power receiving circuit and generating a first RC model, wherein the first resistor capacitor (RC) extraction process is performed at a first frequency and a second frequency higher than the first frequency; scanning a netlist of a power distribution network, wherein the power distribution network is electrically connected to the power receiving circuit; selecting circuit elements of the power distribution network based on a predetermined criterion; performing a second RC extraction process on the selected circuit elements and generating a second RC model, wherein the second RC model is simplified compared to the first RC model; and performing a simulation process on the power receiving circuit and the power distribution network using the first RC model and the second RC model.

2. The method of claim 1, wherein, the first RC extraction process is configured to exclude second order or higher order derivatives of the first RC model.

3. The method of claim 1, wherein, the second RC extraction process is configured to exclude second order or higher order derivatives of the second RC model.

4. The method of claim 1, further comprising obtaining operating parameters of the power receiving circuit.

5. The method of claim 1, wherein, selecting the circuit elements includes comparing a capacitance of a circuit element to a capacitance threshold, wherein: in response to the capacitance being below the capacitance threshold, excluding the circuit element from the second RC extraction process; and in response to the capacitance being greater than the capacitance threshold, including the circuit element in the second RC extraction process.

6. The method of claim 1, wherein, performing the first RC extraction process on the power receiving circuit includes performing a first order derivative through a die pad of a pad region.

7. The method of claim 6, further comprising adding one or more vias on a layout of the die pad to resemble a power bus layout.

8. The method of claim 1, wherein, performing the first RC extraction process in a frequency spectrum from about 100 MHz to about 600 MHz, or from about 600 MHz to about 1 GHz.

9. A method for analyzing an integrated circuit, comprising: performing a first resistor capacitor (RC) extraction process on a power receiving circuit to generate a first RC model, wherein the first resistor capacitor (RC) extraction process is performed at a first frequency and a second frequency higher than the first frequency; selecting a memory circuit and a group of circuit elements from a power distribution network; performing a second RC extraction process on the selected group of circuit elements and the memory circuit to generate a second RC model, wherein the second RC model is simplified compared to the first RC model; and performing a simulation process on the power receiving circuit, the power distribution network, and the memory circuit using the first RC model and the second RC model.

10. The method of claim 9, wherein, the first RC extraction process is limited to performing first order derivatives of the first RC model.

11. The method of claim 9, wherein, the second RC extraction process is configured to exclude second order or higher order derivatives of the second RC model.

12. The method of claim 9, further comprising obtaining operating parameters of the power receiving circuit.

13. The method of claim 9, wherein, selecting the group of circuit elements includes comparing a capacitance of a circuit element to a capacitance threshold, wherein: excluding the circuit element from the second RC extraction process in response to the capacitance being below the capacitance threshold; and including the circuit element in the second RC extraction process in response to the capacitance being above the capacitance threshold.

14. The method of claim 9, wherein, performing the first RC extraction process on the power receiving circuit includes performing a first derivative through a die pad of a pad area.

15. The method of claim 14, further comprising adding one or more vias on a layout of the die pad to resemble a power bus layout.

16. The method of claim 10, wherein, performing the first RC extraction process in a frequency spectrum from about 100 MHz to about 600 MHz, or from about 600 MHz to about 1 GHz.

17. A computer system comprising: a processor and a memory having computer program code stored thereon, wherein the processor is configured to execute the computer program code in the memory to implement the method of any of claims 1-16.

18. A non-transitory computer readable medium containing a computer executable program for implementing a method for analyzing a signal waveform produced by an integrated circuit when executed by a processor, the method comprising: performing a first resistor capacitor (RC) extraction process on a power receiving circuit and producing a first RC model, wherein the first resistor capacitor (RC) extraction process is performed at a first frequency and a second frequency higher than the first frequency; scanning a netlist of a power distribution network, wherein the power distribution network is electrically connected to the power receiving circuit; selecting circuit elements of the power distribution network based on a predetermined criteria; performing a second RC extraction process on the selected circuit elements and producing a second RC model, wherein the second RC model is simplified than the first RC model; and performing a simulation process on the power receiving circuit and the power distribution network using the first RC model and the second RC model.

19. A computer program product containing a computer executable program for implementing a method for analyzing a signal waveform produced by an integrated circuit when executed by a processor, the method comprising: performing a first resistor capacitor (RC) extraction process on a power receiving circuit and producing a first RC model, wherein the first resistor capacitor (RC) extraction process is performed at a first frequency and a second frequency higher than the first frequency; scanning a netlist of a power distribution network, wherein the power distribution network is electrically connected to the power receiving circuit; selecting circuit elements of the power distribution network based on a predetermined criteria; performing a second RC extraction process on the selected circuit elements and producing a second RC model, wherein the second RC model is simplified than the first RC model; and performing a simulation process on the power receiving circuit and the power distribution network using the first RC model and the second RC model.

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