An inductive current peak detection circuit and its detection method

Abstract

The present invention discloses an inductive current peak detection circuit and its detection method, which directly samples the input current signal and controls the output current signal to maintain near the peak current of the cycle. It includes a first current unit and a second current unit. The first current unit is used to receive the changing input current and follow it, and transfer it to the second current unit. The second current unit automatically detects the moment corresponding to the maximum upward change of the output current of the first current unit, that is, the input current of the second current unit, latches the maximum value of the input current at this moment and outputs it.

Description

Technical Field

[0001] The present invention relates to the technology of inductance current detection, and particularly to a circuit and method for detecting the peak value of inductance current, belonging to the field of integrated circuit technology. Background Art

[0002] In many cases, it is necessary to sample and process a changing inductance current signal to obtain its peak current. Taking a flyback switching power supply as an example, the inductance current waveform is as Figure 1 shown. When the power device is turned on, that is, within the time t1, the inductance current linearly increases; when the power device is turned off, that is, within the time t2, the inductor continues to conduct, and the current charges the load capacitor.

[0003] When it is necessary to analyze the inductance current within a certain period, it is often necessary to sample the current peak value within this period. Traditional methods include: Method 1, after converting the inductance current into voltage, sampling the voltage peak value and then converting it into the current peak value. The principle is as Figure 2 shown. The inductance current I_in is converted into voltage V0A on the resistor R0A, and then the peak voltage V1A is obtained through sampling by the operational amplifier OP1A and the diode D0A. Then, V1A is converted into current through the operational amplifier OP2A and the resistor R1A, and the current I_out is output through the current mirror PM0A and PM1A. Then I_out is the peak value of the inductance current within a certain period; Method 2, directly sampling the current and obtaining the maximum value in the sampling data as the current peak value. The principle is as Figure 3 shown. Within the period T1, the inductance current is sampled by the high-frequency sampling pulse signal SA, and the sampling moment occurs at the falling edge of each sampling pulse. Figure 3 This process is schematically shown in. The current value sampled at the falling edge Ck1 of the first sampling pulse is I(1), and the current value sampled at the falling edge Ck1 of the first sampling pulse is I(2), and so on, until the next pulse after the falling edge Ck(k) of a certain sampling pulse, satisfying I(k + 1) < I(k), then the current value I(k) sampled by the kth sampling pulse is taken as the current peak value within the period T1.

[0004] Figure 2 The circuits shown often need to use multiple operational amplifiers, which increases the circuit area and cost, and the intermediate process includes errors caused by the offset voltage and response speed of the operational amplifier, and there are also certain requirements for the bandwidth of the operational amplifier, increasing the power consumption of the circuit module; Figure 3The shown solution requires a relatively high sampling frequency. Only when the sampling frequency is higher can the result be more accurate. It also needs to increase a certain circuit area cost, and the circuit implementation is relatively complex. Therefore, it is particularly necessary to use relatively small circuit resources to achieve relatively accurate sampling of the peak inductor current, and be able to directly process the current signal without intermediate conversion, bringing a faster response speed for the processing of the subsequent circuit. Summary of the Invention

[0005] The object of the present invention is to overcome at least one of the disadvantages mentioned in the above prior art, and provide a relatively simple circuit structure that directly samples the input inductor current signal and finally controls the output current signal to maintain near the peak current of this cycle.

[0006] To achieve the above object, the present invention adopts the following technical solutions: An inductor current peak detection circuit, characterized in that it includes a first current unit and a second current unit;

[0007] The first current unit is used to follow the input current and transmit it to the second current unit; the first current unit includes NMOS transistor NM1, NMOS transistor NM2, and NMOS transistor NM3. The drain and gate of MOS transistor NM1, the gate of NMOS transistor NM2, and the gate of NMOS transistor NM3 are connected together and connected to the input inductor current I_in. The source of NMOS transistor NM1, the source of NMOS transistor NM2, and the source of NMOS transistor NM3 are all grounded;

[0008] The second current unit is used to detect the maximum value during the change process of the output current of the first current unit and latch and output it; the second current unit includes PMOS transistor PM1, PMOS transistor PM2, PMOS transistor PM3, PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM6, resistor R1, capacitor C1, inverter INV1 and inverter INV2; the gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM2 and the drain of NMOS transistor NM2 in the first current unit, the drain of PMOS transistor PM1 is grounded, the source of PMOS transistor PM2 is connected to one end of resistor R1, one end of capacitor C1, the source of PMOS transistor PM4, the source of PMOS transistor PM5 and the source of PMOS transistor PM6 and is connected to VCC, the other end of resistor R1 is connected to the source of PMOS transistor PM3, the gate of PMOS transistor PM2 is connected to the drain of PMOS transistor PM3, the source of PMOS transistor PM1, the other end of capacitor C1, the gate of PMOS transistor PM5 and the gate of PMOS transistor PM6, the gate of PMOS transistor PM3 is connected to the output of inverter INV2, the input of inverter INV2 is connected to the output of inverter INV1 and the gate of PMOS transistor PM4, the drain of PMOS transistor PM4 is connected to the input of inverter INV1, the drain of PMOS transistor PM5 and the drain of NMOS transistor NM3 in the first current unit, the drain of PMOS transistor PM6 is the current output terminal of the second current unit, and the maximum value of the output current is the inductor current peak Ipk.

[0009] Further, in the first current unit, the output of NMOS transistor NM2 completely mirrors the input current, the output of NMOS transistor NM3 proportionally follows the input current, and the ratio k is determined by the required sampling accuracy, satisfying 1 < k < 1 + δ, where δ is the required current sampling error.

[0010] Further, if the required current sampling error δ = 5%, then 1 < k < 1.05.

[0011] Further, in the second current unit, resistor R1 and capacitor C1 need to satisfy: 100Td < R1 * C1, where Td is the delay between the drain of PMOS transistor PM5 and the gate of PMOS transistor PM3, and capacitor C1 satisfies C1 < T_set(max) * I_PM1 / Vthp, where T_set(max) is the maximum setup time of the working enable of the required current sampling, I_PM1 is the maximum pull-down current of PMOS transistor PM1, and Vthp is the turn-on voltage of PMOS transistor PM3.

[0012] According to the above inductor current peak detection method of the inductor current peak detection circuit, it includes the following steps:

[0013] (1) The first current unit receives the changing input current I_in, follows it, and transfers it to the second current unit. The output current of the first current unit and the input current of the second current unit are equal in magnitude and the same in direction as the input current I_in.

[0014] (2) The second current unit detects the moment when the output current of the first current unit, i.e., the input current of the second current unit, changes upward to the maximum value, latches the current maximum value corresponding to this moment, and outputs it.

[0015] Further, step (2) specifically includes the following steps:

[0016] (2.1) The second current unit receives the output current of the first unit as the input current. When the input current changes upward, the PMOS transistor PM1 in the second current unit conducts and pulls down the gate of the PMOS transistor PM2 until the PMOS transistor PM2 is fully conducting.

[0017] (2.2) After the PMOS transistor PM2 is fully conducting, when the input current changes upward, the current flowing through the PMOS transistor PM2 fully follows, and the input current information is stored on the capacitor C1.

[0018] (2.3) When the output current of the first current unit decreases, the gate of the PMOS transistor PM2 in the second current unit is clamped by the capacitor C1, and the clamping voltage is the gate voltage corresponding to the maximum input current.

[0019] (2.4) When the output current of the first current unit decreases, the gate charge of the PMOS transistor PM2 in the second current unit can only be discharged through the PMOS transistor PM3 and the resistor R1, that is, the capacitor C1 discharges through the PMOS transistor PM3 and the resistor R1, and the discharge time is determined by the product of the resistor R1 and the capacitor C1.

[0020] (2.5) The PMOS transistor PM5 in the second current unit mirrors the output current of the second current unit and compares it with the input current of the first current unit. The input current of the first current unit is mirrored by the NMOS transistor NM3. When the output current of the second current unit is greater than the input current of the first current unit, the discharge path of C1 is cut off, that is, the PMOS transistor PM3 is turned off, the charge on the capacitor C1 remains unchanged, and the voltage across C1 controls the gate potential of the PMOS transistor PM6 to generate the output current.

[0021] (2.6) If the current flowing through the PMOS transistor PM5 is less than the current flowing through the NMOS transistor NM3, the current comparison in step (2.5) is repeated.

[0022] Advantages and remarkable effects of the present invention: The present invention directly processes the current signal, realizes the detection and sampling output of the current peak value with less circuit cost. The sampling has safety and reliability, has a simple circuit structure and small circuit cost, and has high sampling accuracy. It can meet the peak current detection in different occasions and output the peak current. The detected peak current can be applied to subsequent circuit applications such as average current estimation and peak current current limiting. Description of the Drawings

[0023] Figure 1 is the inductor current waveform in a common switching power supply;

[0024] Figure 2 is a traditional current peak sampling principle and implementation method;

[0025] Figure 3 is another traditional current peak sampling principle and implementation method;

[0026] Figure 4 is the schematic diagram of the circuit structure of the present invention;

[0027] Figure 5 is the waveform diagram of the key node voltage and current signal of the present invention;

[0028] Figure 6 is the schematic diagram of the control flow of the current peak detection method of the present invention. Detailed Embodiment

[0029] The present invention will be further described below in conjunction with the drawings and embodiments.

[0030] Refer to Figure 4 , the current peak detection circuit of the present invention includes:

[0031] The first current unit is used to follow the input current and output it to the second current unit;

[0032] The second current unit is used to detect the maximum value in the change process of the output current of the first current unit, that is, the input current of the second current unit, and latch and output it.

[0033] In a preferred embodiment, the first current unit is a basic current mirror, which can follow the change of the input current as accurately as possible without distortion and input it to the second current unit. The first current unit includes NMOS transistor NM1, NMOS transistor NM2, and NMOS transistor NM3. The drain of NMOS transistor NM1, the gate of NMOS transistor NM1, the gate of NMOS transistor NM2, and the gate of NMOS transistor NM3 are connected to the input current. The source of NMOS transistor NM1, the source of NMOS transistor NM2, and the source of NMOS transistor NM3 are connected. The drain of NMOS transistor NM2, the drain of NMOS transistor NM3, and the second current unit are connected. The output of the first current unit is connected to the input of the second current unit.

[0034] In practical applications, the output of NMOS transistor NM2 mirrors the input current exactly, and the output of NMOS transistor NM3 follows the input current proportionally. The proportion k is determined by the required sampling accuracy and needs to satisfy 1 < k < 1 + δ, where δ is the required current sampling error. For example, if a 5% sampling error is required, the proportion is set between 1 and 1.05. However, it still needs to be greater than 1 to ensure that the current inverter composed of PMOS transistor PM5 and NMOS transistor NM3 can flip normally to output a definite high or low level to control the normal output of inverter INV1 and inverter INV2, so as to ensure the fast turn-on and turn-off of PMOS transistor PM3. If the proportion is set less than or equal to 1, the current I0 flowing through NMOS transistor NM3 and the current Ix flowing through PMOS transistor PM5 will always satisfy Ix > I0, and it will be impossible to turn off and turn on PMOS transistor PM3.

[0035] In a preferred embodiment, the second current unit follows the process of the current rising in the first current unit, but does not follow the process of the input current falling. And after the current peak arrives, the charge discharge path is completely cut off through current comparison to ensure that the output current remains approximately unchanged. As Figure 4As shown, the second current unit includes PMOS transistor PM1, PMOS transistor PM2, PMOS transistor PM3, PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM6, resistor R1, capacitor C1, inverter INV1 and inverter INV2. The gate of PMOS transistor PM1, the drain of PMOS transistor PM2 are connected to the drain of NMOS transistor NM1 of the first current unit. The drain of PMOS transistor PM1 is grounded. The source of PMOS transistor PM1, the gate of PMOS transistor PM2, the drain of PMOS transistor PM3, the gate of PMOS transistor PM5, the gate of PMOS transistor PM6 are connected to the first end of the capacitor C1. The source of PMOS transistor PM2, the second end of resistor R1, the second end of capacitor C1, the source of PMOS transistor PM4, the source of PMOS transistor PM5, the source of PMOS transistor PM6 are connected to the power supply. The source of PMOS transistor PM3 is connected to the first end of the resistor R1. The drain of PMOS transistor PM4, the drain of PMOS transistor PM5, the input of inverter INV1 are connected to the drain of NMOS transistor NM3 of the first current unit. The gate of PMOS transistor PM4, the output of inverter INV1 are connected to the input of the inverter INV2. The output of inverter INV2 is connected to the gate of PMOS transistor PM3. The drain of PMOS transistor PM6 outputs current.

[0036] In practical applications, when the current flowing through NMOS transistor NM1 of the first current unit increases, the gate of PMOS transistor PM1 of the second current unit is pulled down until PMOS transistor PM1 is fully turned on. The gate of PMOS transistor PM2 is pulled down to an appropriate potential to follow the process of increasing input current. When the input current increases to the maximum value, that is, when the current flowing through NMOS transistor NM1 reaches the maximum value, the gate of PMOS transistor PM2 is pulled down to the lowest potential, and the corresponding current reaches the maximum. Since PMOS transistor PM1 only has the ability to pull down, that is, the gate potential of PMOS transistor PM2 can only change unidirectionally downward under the action of PMOS transistor PM1 and cannot change upward, that is, the gate potential of PMOS transistor PM2 cannot be raised by PMOS transistor PM1. Refer to Figure 5 , during the process of the current flowing through NMOS transistor NM1 gradually increasing, the voltage difference Vm across both ends of the capacitor C1 connected between the gate of PMOS transistor PM2 and the power supply also gradually increases, and the gate potential VG of PMOS transistor PM2 gradually decreases. Until the current flowing through NMOS transistor NM1 reaches the maximum value, the voltage difference Vm across both ends of the capacitor C1 also reaches the maximum value Vm_max, and the gate potential VG of PMOS transistor PM2 reaches the lowest V L, at this time, if the current flowing through NMOS transistor NM1 starts to decrease, the voltage difference across capacitor C1 will not decrease immediately. Instead, it can only slowly discharge the charge through the relatively large resistor R1 and approximately maintain near the Vm_max value, and then slowly decrease. The rate of decrease is determined by the time constant formed by R1 and C1:

[0037] τ = R1C1

[0038] When the current flowing through PMOS transistor PM2 is at its maximum, the corresponding voltage across capacitor C1 is V m , then after time t, the voltage across the two ends becomes:

[0039]

[0040] In practical applications, if R1 = 5 Mohm and C1 = 10 pF are taken, a time constant of 50 us can be obtained. Then, when the voltage across C1 drops to 99% of the maximum amplitude, it takes approximately 0.01 time constant units, that is, 500 ns. Therefore, when the accuracy is controlled within 1%, the response time of the current comparator needs to be within 500 ns, which is generally easy to achieve. This time should be greater than the output delay required for the comparator to output a valid signal. Therefore, if the total delay of the current comparator composed of PM5, NM3, INV1, and INV2 is Td1, in order to make the sampling accuracy of this link above 99%, the values of R1 and C1 should satisfy: 0.01R1 * C1 > Td1. However, capacitor C1 cannot be infinitely large. Too large a capacitor will cause the circuit startup and establishment time to be too long. C1 needs to satisfy C1 < T_set(max) * I_PM1 / Vthp, where T_set(max) is the maximum establishment time required for the current sampling module to be enabled to work, I_PM1 is the maximum pull-down current of PMOS transistor PM1, and Vthp is the turn-on voltage of PMOS transistor PM3.

[0041] Figure 4 In, since the current reduction of PMOS transistor PM2 lags far behind the current in the first current unit, by continuously comparing the current Ix in PMOS transistor PM5 and the current I0 in NMOS transistor NM3, when the current Ix in PMOS transistor PM5 is greater than the current I0 in NMOS transistor NM3, it indicates that the current has reached the maximum value and starts to decrease. A control signal is generated to turn off PMOS transistor PM3, cutting off the discharge path of capacitor C1 through resistor R1. The charge on capacitor C1 basically no longer changes, and PMOS transistor PM6 is controlled to generate a constant output current Ipk.

[0042] See Figure 5 、 6 , according to the current peak detection method corresponding to the current peak detection circuit designed by the present invention, it includes the following steps:

[0043] (1) The first current unit receives a varying input current, follows it, and transfers it to the second current unit;

[0044] (2) The second current unit detects the moment when the input current changes upward to the maximum value, latches the maximum value, and outputs it.

[0045] In a preferred embodiment, referring to Figure 5 , if Figure 4 the current comparison output in the second current unit described in is at a high level, the inverters INV1 and INV2 are accelerated to flip through the PMOS transistor PM4, controlling the turn-off of the PMOS transistor PM3. During the actual working process, since the current comparison is real-time, that is, when the current in the second current unit is less than that in the first current unit again, the PMOS transistor PM3 will be turned on again to ensure that the voltage across the capacitor C1 will not accumulate to a large value, causing more current errors.

[0046] Further, referring to Figure 6 , the above step (2) specifically includes the following steps:

[0047] (2.1) The second current unit receives the current from the first unit. When the current changes upward, the PMOS transistor PM1 in the second current unit conducts and pulls down the gate of the PMOS transistor PM2 until the PMOS transistor PM2 is fully conductive;

[0048] (2.2) After the PMOS transistor PM2 is fully conductive, when the input current changes upward, the current flowing through the PMOS transistor PM2 fully follows, and the current information is stored on the capacitor C1;

[0049] (2.3) When the current in the first current unit drops, the gate of the PMOS transistor PM2 in the second current unit is clamped by the capacitor C1, and the clamping voltage is the gate voltage corresponding to the maximum input current;

[0050] (2.4) When the current in the first current unit drops, the gate charge of the PMOS transistor PM2 in the second current unit can only be discharged through the PMOS transistor PM3 and the resistor R1, that is, the capacitor C1 is discharged through the PMOS transistor PM3 and the resistor R1, and the discharge time is determined by the product of the resistor R1 and the capacitor C1;

[0051] (2.5) The PMOS transistor PM5 in the second current unit mirrors the current in the second current unit and compares it with the current in the first current unit. The current in the first current unit is mirrored by the NMOS transistor NM3. When the current in the second current unit is greater than the current in the first current unit, the PMOS transistor PM3 is turned off, cutting off the discharge path composed of the capacitor C1 and the resistor R1, and the charge on the capacitor C1 remains unchanged, controlling the gate potential of the PMOS transistor PM6 to generate an output current.

[0052] (2.6) If the current of PMOS transistor PM5 is less than the current of NMOS transistor NM3, repeat the current comparison in (2.5).

Claims

1. An inductive current peak detection circuit, characterized in that It includes a first current unit and a second current unit; The first current unit is used to follow the input current and transmit it to the second current unit; the first current unit includes NMOS transistor NM1, NMOS transistor NM2, and NMOS transistor NM3. The drain and gate of MOS transistor NM1, the gate of NMOS transistor NM2, and the gate of NMOS transistor NM3 are connected together and connected to the input inductor current I_in. The source of NMOS transistor NM1, the source of NMOS transistor NM2, and the source of NMOS transistor NM3 are all grounded; The second current unit is used to detect the maximum value during the change of the output current of the first current unit and latch and output it; the second current unit includes PMOS transistor PM1, PMOS transistor PM2, PMOS transistor PM3, PMOS transistor PM4, PMOS transistor PM5, and PMOS transistor PM6, as well as resistor R1, capacitor C1, inverter INV1, and inverter INV2; the gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM2 and connected to the drain of NMOS transistor NM2 in the first current unit. The drain of PMOS transistor PM1 is grounded. The source of PMOS transistor PM2 is connected to one end of resistor R1, one end of capacitor C1, the source of PMOS transistor PM4, the source of PMOS transistor PM5, and the source of PMOS transistor PM6 and connected to VCC. The other end of resistor R1 is connected to the source of PMOS transistor PM3. The gate of PMOS transistor PM2 is connected to the drain of PMOS transistor PM3, the source of PMOS transistor PM1, the other end of capacitor C1, and the gates of PMOS transistor PM5 and PMOS transistor PM6. The gate of PMOS transistor PM3 is connected to the output of inverter INV2. The input of inverter INV2 is connected to the output of inverter INV1 and the gate of PMOS transistor PM4. The drain of PMOS transistor PM4 is connected to the input of inverter INV1, the drain of PMOS transistor PM5, and the drain of NMOS transistor NM3 in the first current unit. The drain of PMOS transistor PM6 is the current output terminal of the second current unit, and the maximum value of the output current is the inductor current peak Ipk.

2. The inductor current peak detection circuit according to claim 1, characterized in that, In the first current unit, the output of NMOS transistor NM2 completely mirrors the input current, and the output of NMOS transistor NM3 follows the input current proportionally. The proportion k is determined by the required sampling accuracy and satisfies 1 < k < 1 + δ, where δ is the required current sampling error.

3. The inductor current peak detection circuit according to claim 2, wherein, Taking the required current sampling error δ = 5%, then 1 < k < 1.

05.

4. The inductor current peak detection circuit according to claim 1, wherein In the second current unit, resistor R1 and capacitor C1 need to satisfy: 100Td < R1 * C1, where Td is the delay between the drain of PMOS transistor PM5 and the gate of PMOS transistor PM3. Capacitor C1 satisfies C1 < T_set(max) * I_PM1 / Vthp, where T_set(max) is the maximum setup time for the required current sampling operation enable, I_PM1 is the maximum pull-down current of PMOS transistor PM1, and Vthp is the turn-on voltage of PMOS transistor PM3.

5. The method for detecting the peak inductor current of the inductor current peak detection circuit according to claim 1, characterized in that, It includes the following steps: (1) The first current unit receives the changing input current I_in, follows it, and transfers it to the second current unit. The output current of the first current unit and the input current of the second current unit are equal in magnitude and the same in direction as the input current I_in. (2) The second current unit detects the moment when the output current of the first current unit, i.e., the input current of the second current unit, changes upward to the maximum value, latches the current maximum value corresponding to this moment, and outputs it.

6. The method for detecting the peak inductor current of the inductor current peak detection circuit according to claim 5, wherein (2) The above step (2) specifically includes the following steps: (2.1) The second current unit receives the output current of the first unit as the input current. When the input current changes upward, the PMOS transistor PM1 in the second current unit conducts and pulls down the gate of the PMOS transistor PM2 until the PMOS transistor PM2 is fully conductive. (2.2) After the PMOS transistor PM2 is fully conductive, when the input current changes upward, the current flowing through the PMOS transistor PM2 fully follows, and the input current information is stored on the capacitor C1. (2.3) When the output current of the first current unit decreases, the gate of the PMOS transistor PM2 in the second current unit is clamped by the capacitor C1, and the clamping voltage is the gate voltage corresponding to the maximum input current. (2.4) When the output current of the first current unit decreases, the gate charge of the PMOS transistor PM2 in the second current unit can only be discharged through the PMOS transistor PM3 and the resistor R1, that is, the capacitor C1 is discharged through the PMOS transistor PM3 and the resistor R1, and the discharge time is determined by the product of the resistor R1 and the capacitor C1. (2.5) The PMOS transistor PM5 in the second current unit mirrors the output current of the second current unit and compares it with the input current of the first current unit. The input current of the first current unit is mirrored by the NMOS transistor NM3. When the output current of the second current unit is greater than the input current of the first current unit, the discharge path of C1 is cut off, that is, the PMOS transistor PM3 is turned off, the charge on the capacitor C1 remains unchanged, and the voltage across C1 controls the gate potential of the PMOS transistor PM6 to generate the output current. (2.6) If the current flowing through the PMOS transistor PM5 is less than the current flowing through the NMOS transistor NM3, the current comparison in step (2.5) is repeated.

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