Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate; forming a core layer extending along a first direction; forming a mask sidewall on a sidewall of the core layer; forming a first dividing layer extending along a second direction and contacting a sidewall of the mask sidewall along the first direction; forming a sacrificial layer arranged at intervals with the core layer along the second direction, covering the sidewall of the mask sidewall along the first direction, protruding from both sides of the first dividing layer along the first direction and covering a partial sidewall of the first dividing layer; forming a planar layer on the substrate exposed by the sacrificial layer, the core layer, the mask sidewall and the first dividing layer; removing the sacrificial layer to form a first groove, and the first groove is divided by the first dividing layer along the first direction; removing the core layer to form a second groove; using the mask sidewall, the first dividing layer and the planar layer as masks to pattern a target layer under the first groove and the second groove to form a target pattern. The embodiment of the present invention is beneficial to improving the pattern accuracy and pattern quality of the target pattern.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] During the development of integrated circuits, generally, as the functional density (i.e., the number of internal wiring structures per chip) gradually increases, the geometric size (i.e., the minimum element size that can be produced using process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, in the case of continuously shrinking technology nodes, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the pattern accuracy and pattern quality of the target pattern.

[0006] To solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a target layer for forming a target pattern; forming a core layer extending along a first direction on the substrate, and a direction perpendicular to the first direction is a second direction; forming a mask sidewall on a sidewall of the core layer; forming a first dividing layer extending along the second direction, the first dividing layer being in contact with a sidewall of the mask sidewall along the first direction; forming a sacrificial layer extending along the first direction and arranged at intervals along the second direction with the core layer, the sacrificial layer covering a sidewall of the mask sidewall along the first direction, and along the first direction, the sacrificial layer protruding from both sides of the first dividing layer and covering a part of the sidewall of the first dividing layer; forming a planar layer on the substrate exposed by the sacrificial layer, the core layer, the mask sidewall, and the first dividing layer; removing the sacrificial layer to form a first groove in the planar layer, and the first groove being divided by the first dividing layer along the first direction; removing the core layer to form a second groove in the planar layer; using the mask sidewall, the first dividing layer, and the planar layer as a mask to pattern the target layer below the first groove and the second groove to form a target pattern.

[0007] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a target layer for forming a target pattern; a core layer located on the substrate and extending in a first direction, and a second direction being perpendicular to the first direction; a mask sidewall located on a sidewall of the core layer; a first dividing layer extending in the second direction, the first dividing layer being in contact with a sidewall of the mask sidewall in the first direction; a sacrificial layer extending in the first direction and arranged at intervals with the core layer in the second direction, the sacrificial layer covering the sidewall of the mask sidewall in the first direction, in the first direction, the sacrificial layer protruding from both sides of the first dividing layer and covering a part of the sidewall of the first dividing layer; a planarization layer located on the substrate and covering the sacrificial layer, the core layer, the mask sidewall, and the sidewall of the first dividing layer, the planarization layer exposing top surfaces of the sacrificial layer and the core layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming the semiconductor structure provided by the embodiment of the present invention, after forming the core layer and the mask sidewall, a first dividing layer extending in the second direction is first formed, the first dividing layer being in contact with a sidewall of the mask sidewall in the first direction, and then a sacrificial layer is formed. In the first direction, the sacrificial layer protrudes from both sides of the first dividing layer and covers a part of the sidewall of the first dividing layer, so that the sacrificial layers located on both sides of the first dividing layer are divided by the first dividing layer. After removing the sacrificial layer to form a first groove, the first groove in the first direction is correspondingly divided by the first dividing layer, which is beneficial to enabling a smaller distance between adjacent first grooves in the first direction. After forming the target pattern by patterning the target layer under the first groove and the second groove, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns, which is beneficial to improving the layout design flexibility and freedom of the target pattern; moreover, in the embodiment of the present invention, the first dividing layer is first formed and then the sacrificial layer is formed. The first dividing layer correspondingly defines the cutting size and position of the first groove. Compared with directly implementing the division of the first groove through an etching process, the embodiment of the present invention is beneficial to reducing the difficulty of dividing the first groove, increasing the process window for cutting the first groove, and can also precisely control the size of the first groove at the head-to-head position by adjusting the size of the first dividing layer, which is further beneficial to improving the pattern accuracy and pattern quality of the target pattern.

[0010] In addition, in the embodiment of the present invention, the core layer is first formed, and then a mask sidewall, which is an outer spacer, is formed on the sidewall of the core layer. After the core layer is removed to form the second groove, the distance between adjacent second grooves in the first direction is defined by the core layer. Compared with the method of first forming a groove and then forming an inner sidewall on the sidewall of the groove, in the embodiment of the present invention, the distance between adjacent second grooves in the first direction is not the sum of the distance between adjacent core layers and twice the thickness of the inner sidewall, which is beneficial to achieving a smaller distance between adjacent second grooves in the first direction. Correspondingly, after forming the target pattern by patterning the target layer under the first groove and the second groove, the adjacent target patterns can achieve a smaller distance at the head-to-head position, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern, and also beneficial to saving process costs. Description of the Drawings

[0011] Figures 1 to 46 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments

[0012] As can be seen from the background art, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Specifically, in the current back-end process, the patterning process of metal interconnect lines is difficult and the process window is small.

[0013] For example: when the pattern of the interconnect pattern is relatively complex, the number of masks required for the lithography process is large, which not only leads to too high process costs, but also the pattern of the mask is complex, and the optical proximity correction process of the mask has a high degree of difficulty, resulting in poor pattern accuracy and pattern quality of the formed interconnect lines, and even easily leading to the problem of short circuit (bridge) at the position where the interconnect lines do not need to be connected.

[0014] One method uses dummy lines to increase the process window of the lithography process and reduce the complexity of the mask pattern. When the device is working, these dummy lines are in a floating state, that is, these interconnect lines are not electrically connected to the external circuit or other interconnect structures. However, these floating dummy lines are likely to increase the parasitic capacitance of the back-end interconnect, resulting in poor performance of the formed semiconductor structure.

[0015] To solve the above technical problem, in the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the core layer and the mask sidewall, a first dividing layer extending in the second direction is first formed. The first dividing layer is in contact with the sidewall of the mask sidewall in the first direction. Then, a sacrificial layer is formed. Along the first direction, the sacrificial layer protrudes from both sides of the first dividing layer and covers a part of the sidewall of the first dividing layer, so that the sacrificial layers located on both sides of the first dividing layer are divided by the first dividing layer. After removing the sacrificial layer to form a first groove, the first groove is correspondingly divided by the first dividing layer along the first direction, which is beneficial to achieving a smaller distance between adjacent first grooves along the first direction. After patterning the target layer below the first groove and the second groove to form a target pattern, the adjacent target patterns can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the layout design flexibility and freedom of the target pattern. Moreover, in the embodiment of the present invention, the first dividing layer is first formed, and then the sacrificial layer is formed. The first dividing layer correspondingly defines the cutting size and position of the first groove. Compared with directly realizing the division of the first groove through an etching process, the embodiment of the present invention is beneficial to reducing the difficulty of dividing the first groove, increasing the process window for cutting the first groove, and can also precisely control the size of the first groove at the head-to-head position by adjusting the size of the first dividing layer, thereby being beneficial to improving the pattern accuracy and pattern quality of the target pattern.

[0016] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings. Figures 1 to 46 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0017] Reference Figure 1 and Figure 2 , Figure 2 is Figure 1 A cross-sectional view along the y1-y1 secant line, providing a substrate 200, including a target layer 100 for forming a target pattern.

[0018] The substrate 200 is used to provide a platform for subsequent process steps. The target layer 100 is a film layer to be patterned to form a target pattern. Among them, the target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork-sheet transistor, a hard mask (HM) layer, and other patterns.

[0019] In this embodiment, the target layer 100 is a dielectric layer. Subsequently, the dielectric layer is patterned to form a plurality of interconnect grooves therein, and then interconnect lines are formed in the interconnect grooves. The dielectric layer is used to achieve electrical isolation between adjacent interconnect lines. Correspondingly, in this embodiment, the target pattern is an interconnect groove. Therefore, the dielectric layer is an Inter Metal Dielectric (IMD) layer. The material of the dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0020] Correspondingly, semiconductor devices such as transistors and capacitors can be formed in the substrate 200, and functional structures such as resistor structures and conductive structures can also be formed in the substrate 200. In this embodiment, the substrate 200 further includes a substrate 110 located at the bottom of the target layer 110. As an example, the substrate 110 is a silicon substrate.

[0021] In this embodiment, the substrate 200 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is first patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask, which is beneficial to improving the process stability of patterning the target layer 100 and the accuracy of pattern transfer.

[0022] The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon carbonitride, and silicon oxynitride. As an example, the material of the hard mask material layer 115 is titanium nitride.

[0023] In a specific process, according to actual process requirements, a stress buffer layer can also be provided between the hard mask material layer 115 and the target layer 100 to improve the adhesion between the hard mask material layer 115 and the target layer 100 and reduce the stress generated between the film layers. In addition, an etch stop layer can also be provided between the hard mask material layer 115 and the stress buffer layer, as well as on the hard mask material layer 115 to define the stop position of the subsequent etching process, which is beneficial to improving the effect of the subsequent patterning process. The related descriptions of the stress buffer layer and the etch stop layer are not elaborated in this embodiment.

[0024] Continue to refer to Figure 1 and Figure 2 , a core layer 120 extending in a first direction (such as the X direction shown in Figure 1 ) is formed on the substrate 200, and the direction perpendicular to the first direction is the second direction (such as the Y direction shown in Figure 1 ).

[0025] The core layer 120 is used to occupy the spatial position for forming the second groove, thereby defining the pattern and position of the subsequent second groove. Compared with directly forming the second groove through an etching process, in this embodiment, the core layer 120 is first formed, and then the core layer 120 is removed subsequently to form the second groove. Thus, by adjusting the size and shape of the core layer 120, the size and shape of the second groove can be precisely controlled, which is beneficial to reducing the difficulty of forming the second groove and ensuring the pattern accuracy of the second groove. Correspondingly, after subsequently etching the target layer 100 below the second groove to form the target pattern, it is beneficial to improve the pattern accuracy of the target pattern. Subsequently, a mask sidewall is formed on the sidewall of the core layer 120, and the core layer 120 also provides support for forming the mask sidewall.

[0026] In this embodiment, the core layer 120 is made of a material that is easy to be removed, thereby reducing the difficulty of removing the core layer 120 subsequently. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride. As an example, the core layer 120 is a single-layer structure, and the material of the core layer 120 is amorphous silicon.

[0027] Reference Figures 3 to 5 , in this embodiment, after forming the core layer 120, the method for forming the semiconductor structure further includes: forming a cutting groove 20 that penetrates the core layer 120 along the second direction; the core layer 120 is divided by the cutting groove 20 along the first direction.

[0028] The cutting groove 20 is used to divide the core layer 120 along the first direction, so that a smaller distance can be achieved between adjacent core layers 120 along the first direction, so that a smaller distance can be achieved between adjacent target patterns at the head-to-head positions. The cutting groove 20 is also used to occupy the spatial position for forming the second dividing layer.

[0029] In this embodiment, the step of forming the cutting groove 20 includes the following steps.

[0030] As Figure 3 shown, a cross-sectional view along the first direction at the position of the core layer 120 is shown. A pattern layer (not labeled) covering the core layer 120 is formed on the substrate 200, including a filling layer 121, a first anti-reflection coating 122, and a first photoresist layer 123 stacked in sequence from bottom to top. A first pattern opening 10 is formed in the first photoresist layer 123. The pattern layer is used as a mask for etching the core layer 120.

[0031] The filling layer 121 is used to provide a flat surface for forming the first anti-reflection coating 122 and the first photoresist layer 123. In this embodiment, the material of the filling layer 121 is spin-on carbon (SOC).

[0032] The first anti-reflection coating 122 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the first anti-reflection coating is a Si-ARC layer, and the Si-ARC layer is beneficial to increasing the depth of focus (DOF) during the lithography process and improving the exposure uniformity. In other embodiments, the material of the first anti-reflection coating may also be a BARC material.

[0033] The first photoresist layer 123 is used as a mask for etching the first anti-reflection coating 122, the filling layer 121, and the core layer 120. The photoresist layer 123 is formed by lithography processes such as exposure and development.

[0034] As Figure 4 and Figure 5 shown, Figure 5 for Figure 4 a cross-sectional view along the first direction at the position of the core layer 120, using the first photoresist layer 123 as a mask, sequentially etching the first anti-reflection coating 122, the filling layer 121, and the core layer 120 along the first pattern opening 10, and forming the cutting groove 20 in the core layer 120; removing the pattern layer.

[0035] In this embodiment, an anisotropic dry etching process is used to sequentially etch the first anti-reflection coating 122, the filling layer 121, and the core layer 120. The anisotropic dry etching process has the characteristics of anisotropic etching, thereby improving the pattern transfer accuracy.

[0036] In this embodiment, one or both of an ashing process and a wet stripping process are used to remove the pattern layer.

[0037] In other embodiments, after forming the core layer and before forming the mask sidewall, the method for forming the semiconductor structure further includes: ion doping a part of the core layer, which is suitable for improving the etching resistance of the core layer, and the core layer doped with ions is used as the second segmentation layer; the core layer is segmented by the second segmentation layer along the first direction. Ion doping is suitable for improving the etching resistance of the core layer. Correspondingly, the etching resistance of the second segmentation layer is greater than that of the core layer, and the etching selectivity between the core layer and the second segmentation layer is correspondingly increased, so that the second segmentation layer can be retained during the subsequent process of removing the core layer to form the second groove, and thus the second segmentation layer can segment the second groove. Specifically, the ions for ion doping include one or more of boron ions, phosphorus ions, and argon ions.

[0038] Reference Figures 6 to 8 , Figure 7 is Figure 6 a cross-sectional view along the y1 - y1 secant line, Figure 8 is Figure 6 a cross-sectional view along the first direction at the position of the core layer 120. A mask sidewall 130 is formed on the sidewall of the core layer 120. The mask sidewall 130 is used as a mask for subsequent patterning of the target layer 100.

[0039] Subsequently, a first groove and a second groove are formed. The mask sidewall 130 is also used to isolate adjacent first and second grooves, and in this embodiment, the thickness of the mask sidewall 130 can also be adjusted to make the minimum designed interval between the subsequent first and second grooves satisfied.

[0040] In this embodiment, the core layer 120 is first formed, and then the mask sidewall 130 is formed on the sidewall of the core layer 120. The mask sidewall 130 is an outer spacer; after removing the core layer 120 to form the second groove, the distance between adjacent second grooves along the first direction is defined by the core layer 120. Compared with first forming the groove and then forming the inner sidewall on the sidewall of the groove, in this embodiment, the distance between adjacent second grooves along the first direction is not the sum of the distance between adjacent core layers and twice the thickness of the inner sidewall, which is beneficial to achieving a smaller distance between adjacent second grooves along the first direction. Correspondingly, after forming the target pattern in the target layer below the first and second grooves, adjacent target patterns can achieve a smaller distance at the head - to - head position, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern and is also beneficial to saving process costs.

[0041] In this embodiment, the mask sidewall 130 fills the cutting groove 20. The mask sidewall 130 located in the cutting groove 20 is used as the second dividing layer 140. After removing the core layer 120 to form the second groove, the second dividing layer 140 is used to divide the second groove along the first direction.

[0042] The mask sidewall 130 selects a material having etching selectivity with respect to the core layer 120 and the target layer 100. The material of the mask sidewall 130 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon.

[0043] In this embodiment, the process of forming the mask sidewall 130 includes an atomic layer deposition process, which is beneficial to improving the thickness uniformity of the mask sidewall 130 and is easy to precisely control the thickness of the mask sidewall 130.

[0044] Reference Figures 9 to 22, a first dividing layer 170 extending in the second direction is formed, and the first dividing layer 170 is in contact with the side wall of the mask sidewall 130 in the first direction.

[0045] The first dividing layer 170 is used to divide the subsequent sacrificial layer in the first direction. Thus, after the subsequent sacrificial layer is removed to form the first groove, the first groove is correspondingly divided by the first dividing layer 170 in the first direction, which is beneficial to enabling a smaller distance between adjacent first grooves in the first direction. After the target layer 100 below the patterned first groove and second groove forms the target pattern, the adjacent target patterns can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern. Compared with directly achieving the division of the first groove through an etching process, this embodiment is beneficial to reducing the difficulty of dividing the first groove, increasing the process window for cutting the first groove, and can also precisely control the size of the first groove at the head-to-head position by adjusting the size of the first dividing layer 170, thereby being beneficial to improving the pattern accuracy and pattern quality of the target pattern.

[0046] In this embodiment, along the second direction, the first dividing layer 170 further extends to cover a part of the top of the mask sidewall 130 and the core layer 120, that is to say, the first dividing layer 170 is an Overcut, which is not only beneficial to reducing the requirement for the dimensional accuracy of the first dividing layer 170 in the second direction, but also beneficial to preventing the problem that the second dividing layer cannot effectively divide the sacrificial layer.

[0047] Therefore, the first dividing layer 170 is made of a material having an etching selectivity with respect to the core layer 120 and the subsequent sacrificial layer. In this embodiment, the material of the first dividing layer 170 includes one or more of silicon oxide, metal oxide (for example: titanium oxide), polysilicon, and amorphous silicon. As an example, the material of the first dividing layer 170 is silicon oxide.

[0048] In this embodiment, the step of forming the first dividing layer 170 includes the following steps.

[0049] As Figures 9 to 11 shown, Figure 10 for Figure 9 the cross-sectional view along the y2 - y2 secant line, Figure 11 for Figure 9 the cross-sectional view along the x - x secant line, a support layer 131 is formed on the substrate 100 where the core layer 120 and the mask sidewall 130 are exposed. The support layer 131 is used to form a cutting opening subsequently, and after the cutting opening is formed, the support layer 131 serves to provide support for forming the first dividing layer in the cutting opening.

[0050] After the first split layer is subsequently formed, the support layer 131 is also removed. Therefore, a material that is easy to remove is selected for the support layer 131 to reduce the difficulty of removing the support layer 131. In this embodiment, the material of the support layer 131 is Spin-On Carbon (SOC). Spin-On Carbon is suitable for the spin coating process, which helps to reduce the difficulty of forming the support layer 131 and improve the flatness of the top surface of the support layer 131. Spin-On Carbon is also easy to remove.

[0051] In other embodiments, the material of the support layer may further include one or more of an Organic Dielectric layer (ODL), a Bottom Anti-reflective coating (BARC), a Silicon Anti-reflective coating (Si-ARC), a Deep UV light absorbing Oxide (DUO), a Dielectric Anti-reflective Coating (DARC), and an Advanced Patterning Film (APF). Correspondingly, in this embodiment, the spin coating process is used to form the support layer 131.

[0052] In this embodiment, after the support layer 131 is formed, the forming method further includes: forming a second anti-reflective coating 132 on the support layer 131; forming a second photoresist layer 133 on the second anti-reflective coating 132, and a second pattern opening 30 is formed in the second photoresist layer 133.

[0053] The second photoresist layer 133 is used to define the size and position of the cutting opening. The second anti-reflective coating 132 is used to reduce the reflection effect during exposure. In this embodiment, the material of the second anti-reflective coating 132 is BARC.

[0054] As Figures 12 to 14 shown, Figure 13 For Figure 12 the cross-sectional view along the y2-y2 cut line, Figure 14 For Figure 12 the cross-sectional view along the x-x cut line, a cutting opening 150 extending in the second direction is formed in the support layer 131, and the cutting opening 150 exposes a part of the side wall of the mask side wall 130 in the first direction and a part of the substrate 200. The cutting opening 150 is used to define the size and position of the first split layer.

[0055] In this embodiment, the cutting opening 150 also exposes a part of the top and part of the sidewalls of the mask sidewall 130 and the core layer 120. In this embodiment, the step of forming the cutting opening 150 includes: using the second photoresist layer 133 as a mask, and sequentially etching the second anti-reflection coating 132 and the support layer 131 along the second pattern opening 30 to form the cutting opening 150 in the support layer 131.

[0056] In this embodiment, an anisotropic dry etching process is used to sequentially etch the second anti-reflection coating 132 and the support layer 131, which is beneficial to improving the accuracy of pattern transfer. In this embodiment, in the step of etching the second anti-reflection coating 132 and the support layer 131, the second photoresist layer 133 is gradually consumed. Therefore, after the cutting opening 150 is formed, the second photoresist layer 133 has been removed.

[0057] As Figures 15 to 19 shown, a first dividing layer 170 is formed in the cutting opening 150.

[0058] Specifically, the step of forming the first dividing layer 170 includes: as Figures 15 to 16 shown, Figure 15 for the cross-sectional view based on Figure 13 , a dividing material layer 160 is formed in the cutting opening 150, and the dividing material layer 160 also covers the second anti-reflection coating 132; as Figure 16 shown, Figure 14 for the cross-sectional view based on Figures 17 to 19 , Figure 18 for Figure 17 the cross-sectional view along the y2-y2 secant line, Figure 19 for Figure 17 the cross-sectional view along the x-x secant line, the dividing material layer 160 higher than the support layer 131 is removed, and the remaining dividing material layer 160 in the cutting opening 150 is used as the first dividing layer 170.

[0059] The process of forming the first dividing layer 170 includes one or more of a spin coating process, an atomic layer deposition process, and a chemical vapor deposition process. In this embodiment, a spin coating process is used to form the dividing material layer 160.

[0060] In this embodiment, an etching process (for example: an anisotropic dry etching process) is used to remove the dividing material layer 160 higher than the support layer 131. In this embodiment, in the step of removing the dividing material layer 160 higher than the support layer 131, the second anti-reflection coating 132 is also removed.

[0061] As Figures 20 to 22 shown, Figure 21 for Figure 20Cross-sectional view along the y2-y2 secant line Figure 22 is Figure 20 Cross-sectional view along the x-x secant line, removing the support layer 131.

[0062] Remove the support layer 131 to facilitate the subsequent formation of the sacrificial layer. In this embodiment, one or both of an ashing process and a wet stripping process are used to remove the support layer 131.

[0063] Refer to Figures 23 to 30 , form a sacrificial layer 180 that extends in a first direction and is arranged at intervals along a second direction with respect to the core layer 120. The sacrificial layer 180 covers the sidewalls of the mask sidewall 130 along the first direction. Along the first direction, the sacrificial layer 180 protrudes from both sides of the first dividing layer 170 and covers part of the sidewalls of the first dividing layer 170.

[0064] The sacrificial layer 180 is used to occupy space for forming the first groove. Correspondingly, the sacrificial layer 180 is used to define the pattern and position of the first groove. Compared with the solution of directly forming the first groove through an etching process, removing the sacrificial layer 180 subsequently to form the first groove is beneficial to reducing the difficulty of forming the first groove, and correspondingly beneficial to ensuring the pattern accuracy of the first groove.

[0065] In this embodiment, along the first direction, the sacrificial layer 180 is divided by the first dividing layer 170. Thus, after removing the sacrificial layer 180 to form the first groove, along the first direction, the first groove is correspondingly divided by the first dividing layer 170, which is beneficial to enabling a smaller distance between adjacent first grooves along the first direction. After forming the target pattern on the target layer 100 under the first groove and the second groove, a smaller distance can also be achieved at the head-to-head (HTH) position of adjacent target patterns.

[0066] In this embodiment, by first forming the core layer 120 and the mask sidewall 130 on the sidewall of the core layer 120, and then forming the sacrificial layer 180, correspondingly, the sacrificial layer 180 and the core layer 120 can be isolated by the mask sidewall 130, which is beneficial to enabling a minimum design interval between the sacrificial layer 180 and the core layer 120, and correspondingly enabling a minimum design interval between the second groove and the first groove.

[0067] Moreover, in this embodiment, the core layer 120 and the sacrificial layer 180 are formed in different steps respectively, and the patterns of the first groove and the second groove are defined by the core layer 120 and the sacrificial layer 180. Correspondingly, it is beneficial to reduce the difficulty of forming the first groove and the second groove, and further beneficial to improving the pattern accuracy of the first groove and the second groove. When etching the target layer 100 under the first groove and the second groove subsequently to form the target pattern, it is correspondingly beneficial to enable the target pattern to have a high pattern accuracy.

[0068] The sacrificial layer 180 is a single-layer or multi-layer structure, and the material of the sacrificial layer 180 includes one or more of spin-on carbon, silicon oxide, metal oxide, organic dielectric layer material, and advanced film material. Among them, the silicon oxide includes spin-on glass (SOG); the metal oxide includes spin-on metal oxide. The material of the sacrificial layer 180 is suitable for the spin-coating process, which is beneficial to reducing the difficulty of forming the sacrificial layer 180 and improving the top surface flatness of the sacrificial layer 180. In this embodiment, the material of the sacrificial layer 140 is spin-on carbon. Spin-on carbon has good filling performance, and spin-on carbon material is easy to be etched, which is beneficial to reducing the difficulty of forming the sacrificial layer 180.

[0069] In this embodiment, in the step of forming the sacrificial layer 180, the sacrificial layer 180 also covers a part of the top of the first dividing layer 170.

[0070] As an example, the step of forming the sacrificial layer 180 includes the following steps.

[0071] As Figures 23 to 26 shown, Figure 24 is Figure 23 a cross-sectional view along the y2-y2 cut line, Figure 25 is Figure 23 a cross-sectional view along the y1-y1 cut line, Figure 26 is Figure 23 a cross-sectional view along the x-x cut line. A sacrificial material layer 171 covering the core layer 120 is formed on the substrate 200. For the convenience of illustration and description, the shapes and positions of the core layer 120, the mask sidewall 130, and the first dividing layer 170 are schematically shown by dashed boxes in Figure 23 .

[0072] The sacrificial material layer 171 is used to form the sacrificial layer. In this embodiment, the sacrificial material layer 171 is formed by the spin-coating process. The spin-coating process is simple to operate, has low process cost, and is beneficial to improving the top surface flatness of the sacrificial material layer 171, and correspondingly beneficial to improving the pattern transfer accuracy when patterning the sacrificial material layer 171 subsequently.

[0073] In this embodiment, the forming method further includes: forming a third anti-reflection coating 172 on the sacrificial material layer 171, and a third photoresist layer 173 located on the third anti-reflection coating 172.

[0074] The third photoresist layer 173 is used to define the size and position of the sacrificial layer.

[0075] The third anti-reflection coating 172 is used to reduce the reflection effect during exposure.

[0076] With reference to Figures 27 to 30 ,Figure 28 is Figure 27 a cross-sectional view along the y2 - y2 secant line, Figure 29 is Figure 27 a cross-sectional view along the y1 - y1 secant line, Figure 30 is Figure 27 a cross-sectional view along the x - x secant line, graphically showing the sacrificial material layer 171, and retaining a part of the sacrificial material layer 171 adjacent to the side wall of the core layer 120 in the first direction as the sacrificial layer 180.

[0077] In this embodiment, the top surface of the sacrificial layer 180 is higher than the top surface of the core layer 120, thus eliminating the step of removing the sacrificial layer 180 higher than the top surface of the core layer 120, which is beneficial to further simplifying the process.

[0078] In this embodiment, using the third photoresist layer 173 as a mask, the third anti-reflection coating 172 and the sacrificial material layer 171 are etched in sequence, and the remaining sacrificial material layer 171 is used as the sacrificial layer 180.

[0079] In this embodiment, an anisotropic dry etching process is adopted to etch the third anti-reflection coating 172 and the sacrificial material layer 171 in sequence, thereby improving the accuracy of pattern transfer.

[0080] In this embodiment, in the step of etching the third anti-reflection coating 172 and the sacrificial material layer 171, the third photoresist layer 173 is also gradually consumed, so that after the sacrificial layer 180 is formed, the third photoresist layer 173 has been removed.

[0081] Refer to Figures 31 to 37 , a planarization layer 210 is formed on the substrate 200 where the sacrificial layer 180, the core layer 120, the mask sidewall 130, and the first dividing layer 170 are exposed. The planarization layer 210 is used together with the mask sidewall 130 and the first dividing layer 170 as a mask for the patterned target layer 100.

[0082] The planarization layer 210 is selected to be a material having an etching selectivity with respect to the materials of the core layer 120 and the sacrificial layer 180. In this embodiment, the material of the planarization layer 210 includes silicon oxide, metal oxides (e.g., titanium oxide), polysilicon, and amorphous silicon. As an example, the material of the planarization layer 210 is the same as the material of the first dividing layer 170, so that the first dividing layer 170 located on the core layer 120 can be removed during the formation of the planarization layer 210. Correspondingly, the material of the planarization layer 210 is silicon oxide.

[0083] In this embodiment, the step of forming the planarization layer 210 includes the following steps.

[0084] As Figures 31 to 33 shown, Figure 31 is based onFigure 28 Cross-sectional view of Figure 32 is based on Figure 29 Cross-sectional view of Figure 33 is based on Figure 30 Cross-sectional view, a flat material layer 190 covering the core layer 120, the mask sidewall 130, the sacrificial layer 180, and the first dividing layer 170 is formed on the substrate 200.

[0085] The process of forming the flat material layer 190 includes one or more of atomic layer deposition process, chemical vapor deposition process, and spin coating process. As an example, the spin coating process is used to form the flat material layer 190. The spin coating process is simple in operation, low in process cost, and is beneficial to improving the top surface flatness of the flat material layer 190.

[0086] As Figures 34 to 37 shown, Figure 35 is Figure 34 Cross-sectional view along the y2 - y2 cut line, Figure 36 is Figure 34 Cross-sectional view along the y1 - y1 cut line, Figure 37 is Figure 34 Cross-sectional view along the x - x cut line, the flat material layer 190 is etched back to expose the sacrificial layer 180.

[0087] Exposing the sacrificial layer 180 enables subsequent etching of the flat material layer 190 and the first dividing layer 170 exposed by the sacrificial layer 180 in the same step, and further enables exposure of the top surface of the core layer 120.

[0088] As Figures 34 to 37 shown, the flat material layer 190 and the first dividing layer 170 with a partial thickness exposed by the sacrificial layer 180 are etched to expose the top surface of the core layer 120, and the remaining flat material layer 190 is used as the flat layer 210. Exposing the top surface of the core layer 120 facilitates subsequent removal of the core layer 120.

[0089] In this embodiment, in the same step, the flat material layer 190 and the first dividing layer 170 with a partial thickness exposed by the sacrificial layer 180 are etched, so that there is no need for an additional step of removing the first dividing layer 170 located on the core layer 120, which is beneficial to improving process integration and compatibility, and is also beneficial to saving process cost.

[0090] In this embodiment, after etching the flat material layer 190 and the first dividing layer 170 with a partial thickness exposed by the sacrificial layer 180, the first dividing layer 170 includes a first part 71 (as Figure 35 shown) located below the sacrificial layer 180 and a second part 72 (as Figure 35As shown, the top surface of the second part 72 is flush with the top surfaces of the core layer 120, the flat layer 210, and the mask sidewall 130.

[0091] Reference Figures 38 to 41 , Figure 39 is Figure 38 a cross-sectional view along the y2-y2 cutting line, Figure 40 is Figure 38 a cross-sectional view along the y1-y1 cutting line, Figure 41 is Figure 38 a cross-sectional view along the x-x cutting line. After removing the sacrificial layer 180, a first groove 230 is formed in the flat layer 210. Along the first direction (as shown by the x direction in Figure 38 ), the first groove 230 is divided by the first dividing layer 170.

[0092] The first groove 230 is used to define the shape and position of part of the target pattern.

[0093] The first groove 230 is divided by the first dividing layer 170 along the first direction, which is beneficial to enabling a smaller distance between adjacent first grooves 230 along the first direction. After forming the target pattern in the target layer 100 below the first groove 230 and the second groove, the adjacent target patterns can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern. Compared with directly implementing the division of the first groove through an etching process, this embodiment is beneficial to reducing the difficulty of dividing the first groove 230, increasing the process window for cutting the first groove 230, and can also precisely control the size of the first groove 230 at the head-to-head position by adjusting the size of the first dividing layer 170, thereby being beneficial to improving the pattern accuracy and pattern quality of the target pattern.

[0094] In this embodiment, the process of removing the sacrificial layer 180 has a high etching selectivity for the sacrificial layer 180 and the first dividing layer 170. Therefore, the probability of the first dividing layer 170 being etched by mistake is low, thereby preventing the distance between the first grooves 230 at the head-to-head position from being increased, and correspondingly enabling precise control of the distance between the first grooves 230 at the head-to-head position.

[0095] In this embodiment, the material of the sacrificial layer 180 is spin-on carbon, and the sacrificial layer 180 is removed by using one or both of an ashing process and a wet stripping process.

[0096] Continuing to refer to Figures 38 to 41 , after removing the core layer 120, a second groove 220 is formed in the flat layer 210. The second groove 220 and the first groove 230 are used to define the shape and position of the target pattern.

[0097] In this embodiment, along the second direction, the first groove 230 and the second groove 220 are isolated by the mask sidewall 130, which is conducive to ensuring that the minimum designed interval is satisfied between the first groove 230 and the second groove 220.

[0098] In this embodiment, the mask sidewall 130 is an outer sidewall. After removing the core layer 120 to form the second groove 220, the distance between adjacent second grooves 220 along the first direction is defined by the core layer 120. Compared with the case where a groove is first formed and then an inner sidewall is formed on the sidewall of the groove, in this embodiment, the distance between adjacent second grooves along the first direction is not the sum of the distance between adjacent core layers and twice the thickness of the inner sidewall, which is conducive to achieving a smaller distance between adjacent second grooves 220 along the first direction. Correspondingly, after forming the target pattern on the target layer 100 below the first groove 230 and the second groove 220, a smaller distance can be achieved at the head-to-head position of adjacent target patterns, which is conducive to improving the flexibility and freedom of the layout design of the target pattern and also conducive to saving process costs.

[0099] In this embodiment, the process of removing the core layer 120 includes one or both of wet etching and dry etching processes. As an example, the wet etching process is used to remove the core layer 120. In this embodiment, the etching solution for the wet etching process includes a TMAH solution (tetramethylammonium hydroxide solution), an SC1 solution, or an SC2 solution. Among them, the SC1 solution refers to a mixed solution of NH4OH and H2O2, and the SC2 solution refers to a mixed solution of HCl and H2O2.

[0100] In this embodiment, after removing the core layer 120, the second groove 220 is divided by the second dividing layer 140 along the first direction, so as to achieve a smaller distance between adjacent second grooves 220.

[0101] Reference Figures 42 to 45 , Figure 43 is Figure 42 the cross-sectional view along the y2-y2 secant line, Figure 44 is Figure 42 the cross-sectional view along the y1-y1 secant line, Figure 45 is Figure 42 the cross-sectional view along the x-x secant line. Using the mask sidewall 130, the dividing layer 170, and the planar layer 210 as masks, the target layer 100 below the first groove 230 and the second groove 220 is patterned to form the target pattern 300.

[0102] As can be seen from the foregoing, the first groove 230 and the second groove 220 both have a small distance at the head-to-head position. Therefore, when etching the target layer 100 below the first groove 230 and the second groove 220 to form the target pattern 300, the adjacent target patterns 300 can also achieve a smaller distance at the head-to-head position, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern 300; moreover, along the second direction, it is easy to meet the designed minimum interval between the first groove 230 and the second groove 220, and then it is easy to meet the designed minimum interval between the target patterns 300; in addition, the first groove 230 and the second groove 220 have high pattern accuracy, which correspondingly helps the target pattern 300 to have high pattern accuracy.

[0103] In this embodiment, the target layer 100 is a dielectric layer. Therefore, using the mask sidewall 130, the spacer layer 170, and the planarization layer 210 as masks, the dielectric layer below the first groove 230 and the second groove 220 is patterned to form interconnect trenches (Trench) 310. Correspondingly, the target pattern 300 is the interconnect trench 310. The interconnect trench 310 is used to provide space for forming interconnect lines.

[0104] Specifically, in this embodiment, using the mask sidewall 130, the spacer layer 170, and the planarization layer 210 as masks, the hard mask material layer 115 below the first groove 230 and the second groove 220 is patterned to form the hard mask layer 240; using the hard mask layer 240 as a mask, the dielectric layer is patterned to form the interconnect trench 310.

[0105] Combined with reference to Figure 46 , in this embodiment, the method for forming the semiconductor structure further includes: after forming the interconnect trench 310, forming an interconnect line 320 in the interconnect trench 310.

[0106] In this embodiment, the interconnect trenches 310 can achieve a small distance at the head-to-head position, and the interconnect lines 320 can correspondingly achieve a small distance at the head-to-head position, which is beneficial to improving the wiring ability of the interconnect lines 320 at the head-to-head position, and is also beneficial to improving the freedom and flexibility of the layout design of the interconnect lines 320; moreover, the interval between adjacent interconnect trenches 310 in the second direction is easy to meet the designed minimum interval. At the same time, the pattern accuracy of the interconnect trenches 310 is high, which correspondingly helps the interval between the interconnect lines 320 in the second direction to meet the designed minimum interval and improve the pattern accuracy of the interconnect lines 320, thereby improving the performance of the semiconductor structure.

[0107] The interconnect line 320 is used to achieve the electrical connection between the semiconductor structure and the external circuit or other interconnect structures. In this embodiment, the material of the interconnect line 320 is copper. In other embodiments, the material of the interconnect line can also be conductive materials such as cobalt, tungsten, aluminum, etc. In this embodiment, in the step of forming the interconnect line 320, the planarization layer 210, the mask sidewall 130, the first segmentation layer 170, and the hard mask layer 240 are also removed to prepare for subsequent processes.

[0108] Correspondingly, the present invention also provides a semiconductor structure. Refer to Figures 34 to 37 , Figure 35 is Figure 34 a cross-sectional view along the y2 - y2 secant line, Figure 36 is Figure 34 a cross-sectional view along the y1 - y1 secant line, Figure 37 is Figure 34 a cross-sectional view along the x - x secant line, showing the structural schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0109] The semiconductor structure includes: a substrate 200, including a target layer 100 for forming a target pattern; a core layer 120, located on the substrate 200 and extending along a first direction (such as Figure 34 the X direction shown in Figure 34 ), and the direction perpendicular to the first direction is the second direction (such as

[0110] the Y direction shown in

[0111] The sacrificial layer 180 is used to occupy a spatial position for forming the first groove. The core layer 120 is used to occupy a spatial position for forming the second groove.The first dividing layer 170 is used to divide the sacrificial layer 180 along the first direction. Thus, after the sacrificial layer 180 is removed subsequently to form the first groove, the first groove is correspondingly divided by the first dividing layer 170 along the first direction, which is conducive to enabling a smaller distance between adjacent first grooves along the first direction. After the target layer 100 under the first groove and the second groove is patterned to form the target pattern, the adjacent target patterns can also achieve a smaller distance at the head-to-head (HTH) position, which is conducive to improving the flexibility and freedom degree of the layout design of the target pattern. Compared with directly realizing the division of the first groove through an etching process, this embodiment is conducive to reducing the difficulty of dividing the first groove, increasing the process window for cutting the first groove, and can also precisely control the size of the first groove at the head-to-head position by adjusting the size of the first dividing layer 170, thereby being conducive to improving the pattern accuracy and pattern quality of the target pattern.

[0112] In addition, in this embodiment, the mask sidewall 130 is located on the outer sidewall of the core layer 120, and the mask sidewall 130 is an outer sidewall; after the second groove is formed, the distance between adjacent second grooves along the first direction is defined by the core layer 120. Compared with first forming the groove and then forming the inner sidewall on the sidewall of the groove, in this embodiment, the distance between adjacent second grooves along the first direction is not the sum of the distance between adjacent core layers and twice the thickness of the inner sidewall, which is conducive to enabling a smaller distance between adjacent second grooves along the first direction. Correspondingly, after the target layer under the first groove and the second groove is patterned to form the target pattern, the adjacent target patterns can achieve a smaller distance at the head-to-head position, which is conducive to improving the flexibility and freedom degree of the layout design of the target pattern, and is also conducive to saving process costs.

[0113] The substrate 200 is used to provide a platform for the process. The target layer 100 is a film layer to be patterned to form the target pattern. Among them, the target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate-all-around (GAA) transistor or a fork-sheet transistor, a hard mask (HM) layer and other patterns.

[0114] In this embodiment, the target layer 100 is a dielectric layer. Subsequently, the dielectric layer is patterned to form a plurality of interconnect trenches, and then interconnect lines are formed in the interconnect trenches. The dielectric layer is used to achieve electrical isolation between adjacent interconnect lines. Correspondingly, in this embodiment, the target pattern is an interconnect trench. Therefore, the dielectric layer is an inter-metal dielectric (IMD) layer. The material of the dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, etc.

[0115] Accordingly, in this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate 200, and functional structures such as resistance structures and conductive structures may also be formed in the substrate 200. In this embodiment, the substrate 200 further includes a substrate 110 located at the bottom of the target layer 110.

[0116] In this embodiment, the substrate 200 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is first patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask, which is beneficial to improving the process stability of patterning the target layer 100 and correspondingly improving the accuracy of pattern transfer. The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon carbon oxide, and silicon carbonitride oxide.

[0117] The core layer 120 is used to occupy a spatial position for forming the second groove, thereby defining the pattern and position of the second groove. The core layer 120 also provides support for forming the mask sidewall 130.

[0118] In this embodiment, the core layer 120 is made of a material that is easy to remove, thereby reducing the difficulty of removing the core layer 120 subsequently. The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbonitride oxide. As an example, the core layer 120 is a single-layer structure, and the material of the core layer 120 is amorphous silicon.

[0119] In this embodiment, the semiconductor structure further includes: a second dividing layer 140 that penetrates the core layer 120 in the second direction; the core layer 120 is divided by the second dividing layer 140 in the first direction.

[0120] The second dividing layer 140 is used to divide the core layer 120 in the first direction, so that a smaller distance can be achieved between adjacent core layers 120 in the first direction, enabling a smaller distance to be achieved at the head-to-head positions of adjacent target patterns.

[0121] As an example, the semiconductor structure further includes: a cutting groove 20 (as Figure 4 shown), which penetrates the core layer 120 in the second direction; the mask sidewall 130 is filled in the cutting groove 20, and the mask sidewall 130 located in the cutting groove 20 is used as the second dividing layer 140. Accordingly, in this embodiment, the material of the second dividing layer 140 is the same as that of the mask sidewall 130.

[0122] In other embodiments, the second dividing layer has the same material as the core layer, and ions are doped in the second dividing layer. The ions are adapted to make the etching resistance of the second dividing layer greater than that of the core layer. Ion doping is adapted to make the etching resistance of the second dividing layer greater than that of the core layer, correspondingly increasing the etching selectivity between the core layer and the second dividing layer, so that the second dividing layer can be retained during the process of removing the core layer to form the second groove, and thus the second dividing layer can divide the second groove. Specifically, the ions for ion doping include one or more of boron ions, phosphorus ions, and argon ions. The second dividing layer has the same material as the core layer, including one or several of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride; the doping ions include one or more of boron ions, phosphorus ions, and argon ions.

[0123] The mask sidewall 130 is used as a mask for subsequent patterning of the target layer 100.

[0124] After the first groove and the second groove are formed, the mask sidewall 130 is further used to isolate adjacent first grooves and second grooves, and in this embodiment, the thickness of the mask sidewall 130 can also be adjusted to make the minimum designed interval between the subsequent first grooves and second grooves satisfied.

[0125] The mask sidewall 130 is selected from materials having etching selectivity with respect to the core layer 120, the sacrificial layer 180, and the target layer 100. The material of the mask sidewall 130 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, aluminum oxide, and amorphous silicon.

[0126] The first dividing layer 170 is used to divide the sacrificial layer 180 along the first direction. Thus, after the sacrificial layer 180 is removed to form the first groove subsequently, the first groove is correspondingly divided by the first dividing layer 170 along the first direction, which is beneficial to enabling a smaller distance between adjacent first grooves along the first direction. After the target pattern is formed in the target layer 100 below the first groove and the second groove, a smaller distance can also be achieved at the head-to-head position of adjacent target patterns, which is beneficial to improving the flexibility and freedom of the layout design of the target pattern. Compared with directly realizing the division of the first groove through an etching process, this embodiment is beneficial to reducing the difficulty of dividing the first groove, increasing the process window for cutting the first groove, and can also precisely control the size of the first groove at the head-to-head position by adjusting the size of the first dividing layer 170, thereby being beneficial to improving the pattern accuracy and pattern quality of the target pattern.

[0127] The first dividing layer 170 is made of a material that has an etching selectivity with respect to the core layer 120 and the sacrificial layer 180. In this embodiment, the material of the first dividing layer 170 includes one or more of silicon oxide, metal oxides (such as titanium oxide), polysilicon, and amorphous silicon. As an example, the material of the first dividing layer 170 is the same as the material of the planarization layer 210, and the material of the first dividing layer 170 is silicon oxide.

[0128] In this embodiment, the first dividing layer 170 includes a first portion 71 located below the sacrificial layer 180 and a second portion 72 exposed from the sacrificial layer 180. The top surface of the second portion 72 is flush with the top surfaces of the core layer 120, the planarization layer 210, and the mask sidewall 130. The second portion 72 is formed by etching a partial thickness of the first dividing layer 170 and the planarization layer 210 using the sacrificial layer 180 as a mask during the step of forming the planarization layer 210.

[0129] The sacrificial layer 180 is used to occupy space for forming the first groove. Correspondingly, the sacrificial layer 180 is used to define the pattern and position of the first groove. Compared with the scheme of directly forming the first groove through an etching process, removing the sacrificial layer 180 subsequently to form the first groove is beneficial to reducing the difficulty of forming the first groove, and correspondingly beneficial to ensuring the pattern accuracy of the first groove.

[0130] In this embodiment, the sacrificial layer 180 is divided by the first dividing layer 170 along the first direction. Thus, after removing the sacrificial layer 180 to form the first groove, the first groove is correspondingly divided by the first dividing layer 170 along the first direction, which is beneficial to enabling a smaller distance between adjacent first grooves along the first direction. After patterning the target layer 100 below the first groove and the second groove to form the target pattern, a smaller distance can also be achieved at the head-to-head position of adjacent target patterns.

[0131] In this embodiment, the sacrificial layer 180 is isolated from the core layer 120 by the mask sidewall 130, which is beneficial to enabling a minimum design interval between the sacrificial layer 180 and the core layer 120, and correspondingly enabling a minimum design interval between the second groove and the first groove.

[0132] The sacrificial layer 180 has a single-layer or stacked structure, and the material of the sacrificial layer 180 includes one or more of spin-on carbon, silicon oxide, metal oxides, organic dielectric layer materials, and advanced film materials. Among them, the silicon oxide includes spin-on silicon oxide; the metal oxides include spin-on metal oxides. The material of the sacrificial layer 180 is suitable for the spin-on process, which is beneficial to reducing the difficulty of forming the sacrificial layer 180 and improving the flatness of the top surface of the sacrificial layer 180. In this embodiment, the material of the sacrificial layer 140 is spin-on carbon. Spin-on carbon has good filling performance, and the spin-on carbon material is easy to be etched, which is beneficial to reducing the difficulty of forming the sacrificial layer 180.

[0133] In this embodiment, the sacrificial layer 180 also covers a part of the top of the first dividing layer 170.

[0134] The planarization layer 210 is used as a mask for the patterned target layer 100 together with the mask sidewall 130 and the first dividing layer 170. The planarization layer 210 is selected to have an etching selectivity with respect to the materials of the core layer 120 and the sacrificial layer 180. In this embodiment, the material of the planarization layer 210 includes silicon oxide, metal oxides (such as titanium oxide), polysilicon, and amorphous silicon. As an example, the material of the planarization layer 210 is the same as that of the first dividing layer 170, so that the first dividing layer 170 located on the core layer 120 can be removed during the formation of the planarization layer 210. Accordingly, the material of the planarization layer 210 is silicon oxide.

[0135] The semiconductor structure can be formed by the formation method described in the foregoing embodiment or by other formation methods. For a specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0136] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including a target layer for forming a target pattern; Forming a core layer extending in a first direction on the substrate, and a direction perpendicular to the first direction is a second direction; Forming a mask sidewall on a sidewall of the core layer; Forming a first dividing layer extending in the second direction, and the first dividing layer is in contact with a sidewall of the mask sidewall in the first direction; Forming a sacrificial layer extending in the first direction and arranged at intervals from the core layer in the second direction, the sacrificial layer covering a sidewall of the mask sidewall in the first direction, and in the first direction, the sacrificial layer protrudes from both sides of the first dividing layer and covers a part of the sidewall of the first dividing layer; Forming a planarization layer on the substrate exposed by the sacrificial layer, the core layer, the mask sidewall, and the first dividing layer; Removing the sacrificial layer to form a first groove in the planarization layer, and the first groove is divided by the first dividing layer in the first direction; Removing the core layer to form a second groove in the planarization layer; Using the mask sidewall, the first dividing layer, and the planarization layer as a mask to pattern the target layer below the first groove and the second groove to form a target pattern.

2. The method for forming a semiconductor structure as described in claim 1, wherein, The step of forming the first dividing layer includes: forming a support layer on the substrate exposed by the core layer and the mask sidewall; Forming a cutting opening extending in the second direction in the support layer, and the cutting opening exposes a part of the sidewall of the mask sidewall in the first direction and a part of the substrate; Forming the first dividing layer in the cutting opening; Removing the support layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process of forming the first dividing layer includes one or more of a spin coating process, an atomic layer deposition process, and a chemical vapor deposition process.

4. The method for forming a semiconductor structure according to claim 1, wherein, After forming the core layer and before forming the mask sidewall, the method for forming the semiconductor structure further includes: forming a cutting groove penetrating the core layer in the second direction; the core layer is divided by the cutting groove in the first direction; In the step of forming the mask sidewall, the mask sidewall fills the cutting groove, and the mask sidewall located in the cutting groove is used as a second dividing layer; After removing the core layer, the second groove is divided by the second dividing layer in the first direction.

5. The method for forming a semiconductor structure according to claim 1, wherein, After forming the core layer and before forming the mask sidewall, the method for forming the semiconductor structure further includes: ion doping a part of the core layer, which is suitable for improving the etching resistance of the core layer, and the core layer doped with ions is used as a second dividing layer; the core layer is divided by the second dividing layer in the first direction.

6. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the first dividing layer, in the second direction, the first dividing layer further extends to cover a part of the top of the mask sidewall and the core layer.

7. The method for forming a semiconductor structure according to claim 6, wherein, In the step of forming the sacrificial layer, the sacrificial layer further covers a part of the top of the first dividing layer; The step of forming the planarization layer includes: forming a planarization material layer covering the core layer, the mask sidewall, the sacrificial layer, and the first dividing layer on the substrate; back-etching the planarization material layer to expose the sacrificial layer; etching a part of the thickness of the planarization material layer and the first dividing layer exposed by the sacrificial layer to expose the top surface of the core layer, and the remaining planarization material layer is used as the planarization layer.

8. The method for forming a semiconductor structure according to claim 7, wherein, The material of the flat layer is the same as that of the first dividing layer.

9. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first dividing layer includes one or more of silicon oxide, metal oxide, polysilicon, and amorphous silicon.

10. The method for forming a semiconductor structure according to claim 1, wherein, The material of the sacrificial layer includes one or more of silicon oxide, metal oxide, spin-on carbon, advanced film, and organic dielectric layer.

11. The method for forming a semiconductor structure according to claim 1, wherein, The target layer is a dielectric layer; the target pattern is an interconnect trench. The method for forming the semiconductor structure further includes: after forming the interconnect trench, forming an interconnect line in the interconnect trench.

12. A semiconductor structure, characterized in that, Including: A substrate, including a target layer for forming a target pattern; A core layer, located on the substrate and extending in a first direction, and a direction perpendicular to the first direction is a second direction; A mask sidewall, located on the sidewall of the core layer; A first dividing layer, extending in the second direction, and the first dividing layer is in contact with the sidewall of the mask sidewall along the first direction; A sacrificial layer, extending in the first direction and arranged at intervals from the core layer in the second direction, the sacrificial layer covers the sidewall of the mask sidewall along the first direction, and along the first direction, the sacrificial layer protrudes from both sides of the first dividing layer and covers a part of the sidewall of the first dividing layer; A flat layer, located on the substrate and covering the sacrificial layer, the core layer, the mask sidewall, and the sidewalls of the first dividing layer, and the flat layer exposes the top surfaces of the sacrificial layer and the core layer.

13. The semiconductor structure according to claim 12, wherein The semiconductor structure further includes: a second dividing layer, penetrating the core layer in the second direction; the core layer is divided by the second dividing layer in the first direction.

14. The semiconductor structure according to claim 13, wherein, The semiconductor structure further includes: a cutting groove, penetrating the core layer in the second direction; the mask sidewall is filled in the cutting groove, and the mask sidewall located in the cutting groove is used as the second dividing layer; Alternatively, the material of the second dividing layer is the same as that of the core layer, and ions are doped in the second dividing layer, and the ions are adapted to make the etching resistance of the second dividing layer greater than that of the core layer.

15. The semiconductor structure according to claim 14, wherein The material of the second dividing layer is the same as that of the core layer, and ions are doped in the second dividing layer; the material of the core layer includes one or several of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbon oxynitride; the doped ions include one or more of boron ions, phosphorus ions, and argon ions.

16. The semiconductor structure according to claim 12, wherein, The sacrificial layer also covers a part of the top of the first dividing layer; The first dividing layer includes a first part located below the sacrificial layer and a second part exposed from the sacrificial layer, and the top surface of the second part is flush with the top surfaces of the core layer, the flat layer, and the mask sidewall.

17. The semiconductor structure according to claim 16, wherein The material of the first dividing layer is the same as that of the flat layer.

18. The semiconductor structure according to claim 12, wherein, The material of the first dividing layer includes one or more of silicon oxide, metal oxide, polysilicon, and amorphous silicon.

19. The semiconductor structure according to claim 12, wherein The material of the sacrificial layer includes one or more of silicon oxide, metal oxide, spin-on carbon, advanced film, and organic dielectric layer.

20. The semiconductor structure according to claim 12, wherein The target layer is a dielectric layer; the target pattern is an interconnect trench.

Images