Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a substrate, a capacitor contact structure, and a landing pad layer. The capacitor contact structure protrudes from the substrate. The landing pad layer covers a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Description

[0001] This invention claims priority and benefits to U.S. Patent Application No. 17 / 071,444, filed October 15, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device having a protruding contact point and a method for fabricating the same. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is gradually shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasingly complex problems. Therefore, the challenges of improving quality, yield, performance, and reliability, while reducing complexity, continue to exist.

[0004] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and a method for its fabrication, in order to solve at least one of the above-mentioned problems.

[0006] One embodiment of this disclosure provides a semiconductor device including a substrate; a capacitor contact structure protruding from the substrate; and a landing pad layer covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0007] In some embodiments, the semiconductor element further includes a bit line structure located on the substrate and adjacent to the capacitor contact structure. An upper surface of the bit line structure is located at a vertical bit plane, which is lower than a vertical bit plane of the upper surface of the capacitor contact structure.

[0008] In some embodiments, the semiconductor device further includes a bit line spacer located between the capacitor contact structure and the bit line structure. An upper surface of the bit line spacer is substantially coplanar with the upper surface of the bit line structure.

[0009] In some embodiments, the bitline structure includes a bitline under-conductive layer, a bitline intermediate conductive layer, a bitline above-conductive layer, and a bitline capping layer. The bitline under-conductive layer is located on the substrate, the bitline intermediate conductive layer is located on the bitline under-conductive layer, the bitline above-conductive layer is located on the bitline intermediate conductive layer, and the bitline capping layer is located on the bitline above-conductive layer.

[0010] In some embodiments, the capacitor contact structure includes a lower conductive layer, a middle conductive layer, and an upper conductive layer. The lower conductive layer protrudes from the substrate, the middle conductive layer is located on the lower conductive layer, the upper conductive layer is located on the middle conductive layer, and the landing pad layer covers a portion of an upper surface of the upper conductive layer and an upper portion of a sidewall of the upper conductive layer.

[0011] In some embodiments, the conductive layer below the capacitor contact comprises polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium; the conductive layer in the middle of the capacitor contact comprises cobalt silicide, nickel silicide, nickel platinum silicide, or tantalum silicide; and the conductive layer above the capacitor contact comprises titanium nitride or tantalum nitride.

[0012] In some embodiments, the lower surface of the capacitor contact structure is located at a vertical plane, which is lower than a vertical plane of the lower surface of the bit line spacer.

[0013] In some embodiments, the semiconductor device further includes a bit line contact located beneath the conductive layer below the bit line.

[0014] In some embodiments, the lower surface of the bit line spacer is approximately coplanar with the lower surface of the bit line contact point.

[0015] In some embodiments, the semiconductor device further includes a plurality of source / drain regions located below the bit line contact and capacitor contact structure.

[0016] In some embodiments, the semiconductor device further includes an isolation structure located between the bit line structure and the capacitor contact structure. The isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer includes a lower portion and two side portions. The lower portion is horizontally disposed on the substrate, and the two side portions are vertically connected to both ends of the lower portion. The second isolation layer is located between the lower portion and the two side portions.

[0017] In some embodiments, the first isolation layer comprises silicon nitride, and the second isolation layer comprises silicon oxide.

[0018] In some embodiments, the semiconductor device further includes an isolation structure located between the bit line structure and the capacitor contact structure. The isolation structure includes a first isolation layer and an air gap. The first isolation layer includes a lower portion and two side portions. The lower portion is horizontally disposed on the substrate, and the two side portions are vertically connected to both ends of the lower portion. The air gap is located between the lower portion and the two side portions.

[0019] In some embodiments, the capacitor contact structure includes a capacitor contact under conductive layer protruding from the substrate, the landing pad layer covering a portion of an upper surface of the capacitor contact under conductive layer and an upper portion of a sidewall of the capacitor contact under conductive layer, and the capacitor contact under conductive layer comprising polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium.

[0020] In some embodiments, the semiconductor element further includes an adjustment layer located between the landing pad layer and the conductive layer below the capacitor contact point, wherein the adjustment layer comprises cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide.

[0021] In some embodiments, the capacitor contact structure includes a capacitor contact under conductive layer protruding from the substrate, the landing pad layer covering a portion of an upper surface of the capacitor contact under conductive layer and an upper portion of a sidewall of the capacitor contact under conductive layer, and the capacitor contact under conductive layer comprising titanium nitride or tantalum nitride.

[0022] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing an upper surface of the bit line structure; and forming a landing pad layer to cover a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0023] In some embodiments, the bitline structure includes a bitline under conductive layer, a bitline intermediate conductive layer, a bitline above conductive layer, and a bitline capping layer. The bitline under conductive layer is formed on the substrate, the bitline intermediate conductive layer is formed on the bitline under conductive layer, the bitline above conductive layer is formed on the bitline intermediate conductive layer, and the bitline capping layer is formed on the bitline above conductive layer.

[0024] In some embodiments, the step of forming the landing pad includes: forming a conductive layer to cover an upper portion of the capacitor contact structure; and performing an etching process to convert the conductive layer into the landing pad. During the etching process, the etching rate of the conductive layer on the capacitor contact structure is between approximately 100:1 and approximately 10:1.

[0025] In some embodiments, the capacitor contact structure comprises polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or titanium nitride or tantalum nitride.

[0026] Due to the design of the semiconductor element disclosed herein, the contact surface between the landing pad layer and the capacitor contact structure can be increased. Accordingly, the resistance between the landing pad layer and the capacitor contact structure can be reduced. Furthermore, the protruding capacitor contact structure can provide sufficiently strong support for the landing pad layer.

[0027] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0028] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0029] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure is shown.

[0030] Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0031] Figure 3 and Figure 4 Examples along Figure 2Schematic diagram of cross-sections A-A' and B-B'.

[0032] Figure 5 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0033] Figure 6 Example edge Figure 5 A schematic cross-sectional view along section line B-B'.

[0034] Figure 7 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0035] Figure 8 Example edge Figure 7 A schematic cross-sectional view along section line B-B'.

[0036] Figure 9 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0037] Figure 10 and Figure 11 Examples along Figure 9 Schematic diagram of cross-sections A-A' and B-B'.

[0038] Figure 12 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0039] Figure 13 and Figure 14 Examples along Figure 12 Schematic diagram of cross-sections A-A' and B-B'.

[0040] Figure 15 and Figure 16 Examples along Figure 12 Schematic diagram of cross-sections A-A' and B-B'.

[0041] Figure 17 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0042] Figure 18 and Figure 19 Examples along Figure 17 Schematic diagram of cross-sections A-A' and B-B'.

[0043] Figure 20 and Figure 21 Examples along Figure 17 Schematic diagram of cross-sections A-A' and B-B'.

[0044] Figure 22A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0045] Figure 23 and Figure 24 Examples along Figure 22 Schematic diagram of cross-sections A-A' and B-B'.

[0046] Figure 25 and Figure 26 Examples along Figure 22 Schematic diagram of cross-sections A-A' and B-B'.

[0047] Figure 27 Example edge Figure 22 A cross-sectional view of section line A-A'.

[0048] Figure 28 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0049] Figure 29 Example edge Figure 28 A cross-sectional view of section line A-A'.

[0050] Figures 30 to 36 Another embodiment of this disclosure is illustrated along Figure 12 The cross-sectional view along section A-A' is a schematic diagram of each step in the fabrication process of the semiconductor device.

[0051] Figures 37 to 44 Another embodiment of this disclosure is illustrated along Figure 17 The cross-sectional view along section A-A' is a schematic diagram of each step in the fabrication process of the semiconductor device.

[0052] The attached figures are labeled as follows:

[0053] 10: Preparation method

[0054] 1A: Semiconductor components

[0055] 1B: Semiconductor components

[0056] 1C: Semiconductor components

[0057] 1D: Semiconductor Components

[0058] 1E: Semiconductor components

[0059] 1F: Semiconductor components

[0060] 101: Base

[0061] 103: Insulation layer

[0062] 105: Active Zone

[0063] 107-1: Source Region

[0064] 107-3: Drain region

[0065] 109: First dielectric layer

[0066] 201: Character Line Structure

[0067] 203: Character line dielectric layer

[0068] 205: Conductive layer below the character line

[0069] 207: Conductive layer on character line

[0070] 209: Character Line Overlay

[0071] 301: Bitline Structure

[0072] 303: Conductive layer below the bit line

[0073] 305: Intermediate conductive layer of bit line

[0074] 307: Conductive layer on bit line

[0075] 309: Bit line capping layer

[0076] 309TS: Top surface

[0077] 311: Bit line contact point

[0078] 311BS: Lower surface

[0079] 313: Bit line gap

[0080] 313BS: Lower surface

[0081] 313TS: Top surface

[0082] 315: Sacrificing a Gap

[0083] 317: Adjustment Layer

[0084] 317SW: Sidewall

[0085] 317TS: Top surface

[0086] 401: Capacitor contact structure

[0087] 403: Conductive layer beneath capacitor contact point

[0088] 403BS: Lower surface

[0089] 405: Intermediate conductive layer at capacitor contact point

[0090] 407: Conductive layer on capacitor contact point

[0091] 407SW: Sidewall

[0092] 407TS: Top surface

[0093] 501: Landing cushion layer

[0094] 601: Isolation Structure

[0095] 603: First Isolation Layer

[0096] 603B: Lower part

[0097] 603S: Side

[0098] 605: Second Isolation Layer

[0099] 607: Air gap

[0100] 701: Character line structure groove

[0101] 703: Capacitor contact point opening

[0102] 705: First trench

[0103] 801: First conductive layer

[0104] 803: Second conductive layer

[0105] 805: First isolation material

[0106] 807: Second isolation material

[0107] 809: Third conductive material

[0108] 811: Fourth Conductive Material

[0109] D1: First Direction

[0110] S11: Steps

[0111] S13: Steps

[0112] S15: Steps

[0113] S17: Steps

[0114] S19: Steps

[0115] S21: Steps

[0116] S23: Steps

[0117] X: First axis

[0118] Y: Second axis

[0119] Z: Direction Detailed Implementation

[0120] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0121] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used in this invention to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used in this invention can be interpreted accordingly.

[0122] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0123] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0124] Unless otherwise specified in the text, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, substantially identical orientation, layout, location, shape, size, amount, or other measure, for example, that may occur due to manufacturing processes. The term "substantially" may be used in this invention to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" can mean exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which may occur due to the manufacturing process.

[0125] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0126] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0127] Figure 1 A schematic flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure is shown. Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 and Figure 4 Examples along Figure 2 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0128] Please refer to Figures 1 to 4 In step S11, a substrate 101 may be provided, an insulating layer 103 may be formed in the substrate 101, and a plurality of active regions 105 may be defined by the insulating layer 103.

[0129] Please refer to Figures 2 to 4 The substrate 101 may include an organic semiconductor or a single-layer semiconductor, such as silicon / silicon-germanium, silicon-on-insulator, or silicon-germanium-on-insulator. When the substrate 101 includes silicon-on-insulator, the substrate 101 may include an upper semiconductor layer and a lower semiconductor layer containing silicon, and a buried isolation layer that separates the upper and lower semiconductor layers. For example, the buried isolation layer may include a crystalline or non-crystalline oxide, nitride, or any combination thereof.

[0130] Please refer to Figures 2 to 4 An insulating layer 103 may be formed in the substrate 101. The upper surface of the insulating layer 103 may be substantially coplanar with the upper surface of the substrate 101. For example, the insulating layer 103 may comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. It should be understood that in this disclosure, silicon oxynitride is a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide is a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0131] Please refer to Figures 2 to 4 An insulating layer 103 may surround portions of a substrate 101. The multiple portions of the substrate 101 surrounded can be considered as multiple active regions 105. In a top view, the multiple active regions 105 may be in a bar shape. Each active region 105 may extend in a first direction D1. The multiple active regions 105 may be arranged along a first axis X and a second axis Y. The multiple active regions 105 may be spaced apart from each other in the first direction D1. The first axis X and the second axis Y are perpendicular to each other. The first direction D1 may be inclined relative to the first axis X and the second axis Y.

[0132] Figure 5 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 6 Example edge Figure 5A cross-sectional view along line B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Figure 7 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 8 Example edge Figure 7 A cross-sectional view along line B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0133] Please refer to Figure 1 and Figures 5 to 8 In step S13, multiple character line structures 201 may be formed in the substrate 101.

[0134] Please refer to Figure 5 and Figure 6 Multiple character line structure trenches 701 may be formed in the substrate 101. In a top view, the multiple character line structure trenches 701 may extend along a first axis X and be parallel to each other. The multiple character line structure trenches 701 may be arranged along a second axis Y. Each active region 105 may intersect with two of the character line structure trenches 701. The two character line structure trenches 701 may divide the corresponding active region 105 into three segments. In some embodiments, in a cross-sectional view, the lower surfaces of the multiple character line structure trenches 701 may be flat. In some embodiments, the lower surfaces of the multiple character line structure trenches 701 may be rounded to reduce the facet density and reduce the electric field concentration during operation of the semiconductor device 1A.

[0135] It should be understood that in this disclosure, the term "segment" may be used interchangeably with "portion".

[0136] Please refer to Figure 7 and Figure 8 Multiple character line dielectric layers 203 may be conformally formed in multiple character line structure trenches 701. The multiple character line dielectric layers 203 may have a U-shaped cross-sectional profile. In some embodiments, the fabrication technique for the multiple character line dielectric layers 203 includes a thermal oxidation process. For example, the fabrication technique for the multiple character line dielectric layers 203 involves oxidizing the lower surfaces and sidewalls of the multiple character line structure trenches 701.

[0137] In some embodiments, the fabrication technique for the plurality of word line dielectric layers 203 includes a deposition process, such as chemical vapor deposition or atomic layer deposition. The plurality of word line dielectric layers 203 may comprise a high-k dielectric material, an oxide, a nitride, an oxide oxynitride, or a combination thereof, wherein the oxide is, for example, silicon oxide, the nitride is, for example, silicon nitride, and the oxide oxynitride is, for example, silicon oxynitride. The high-k dielectric material includes a hafnium-containing material. For example, the hafnium-containing material may be hafnium monoxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0138] Please refer to Figure 7 and Figure 8 Multiple character line conductive layers 205 can be formed on multiple character line dielectric layers 203 and in multiple character line structural trenches 701, respectively. Multiple character line conductive layers 207 can be formed on multiple character line conductive layers 205 and in multiple character line structural trenches 701, respectively. The upper surface of each of the multiple character line conductive layers 207 can be located at a vertical plane, which is lower than the upper surface of the substrate 101.

[0139] For example, the multiple character line conductive layers 205 may comprise polysilicon, polysilicon, polysilicon-germanium, or a combination thereof. In some embodiments, the multiple character line conductive layers 205 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. For example, the multiple character line conductive layers 207 may comprise tungsten, aluminum, titanium, copper, titanium nitride, the like, or a combination thereof.

[0140] Please refer to Figure 7 and Figure 8 Multiple character line capping layers 209 may be formed on the multiple character line conductive layers 207 respectively. The upper surfaces of the multiple character line capping layers 209 may be substantially coplanar with the upper surface of the substrate 101. For example, the multiple character line capping layers 209 may comprise silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, other semiconductor nitrides, or combinations thereof.

[0141] Please refer to Figure 7 and Figure 8 Multiple character line dielectric layers 203, multiple character line under-conductive layers 205, multiple character line above-conductive layers 207, and multiple character line capping layers 209 together form multiple character line structures 201. In a top view, the multiple character line structures 201 may extend along a first axis X and be parallel to each other. The multiple character line structures 201 may be arranged along a second axis Y. Each active region 105 may intersect with two of the character line structures 201.

[0142] Please refer to Figure 7 and Figure 8 An implantation process can be performed on the substrate 101. After the implantation process, in a cross-sectional view, source / drain regions 107-1, 107-3 can be formed in the upper portion of each of the plurality of active regions 105. In a top view, for each active region 105, the source region 107-1 can be formed between two word line structures 201 that intersect with the active region 105. The drain region 107-3 can be formed at both ends of the active region 105. The source / drain regions 107-1, 107-3 can be doped with a dopant, such as phosphorus, arsenic, antimony, or boron.

[0143] Figure 9 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 10 and Figure 11 Examples along Figure 9 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Figure 12 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 13 and Figure 14 Examples along Figure 12 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Figure 15 and Figure 16 Examples along Figure 12 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0144] Please refer to Figure 1 and Figures 9 to 16 In step S15, a plurality of bit line contact points 311 may be formed in the substrate 101, and a plurality of bit line structures 301 and a plurality of bit line spacers 313 may be formed on the substrate 101.

[0145] Please refer to Figures 9 to 11Multiple bitline contacts 311 can be formed in multiple source regions 107-1. The upper surfaces of each bitline contact 311 can be approximately coplanar with the upper surface of the substrate 101. For example, the multiple bitline contacts 311 can comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The multiple bitline contacts 311 can be electrically coupled to the multiple source regions 107-1.

[0146] Please refer to Figures 12 to 14 A series of deposition processes can be sequentially performed to deposit a bit-line conductive layer 303, a bit-line intermediate conductive layer 305, a bit-line conductive layer 307, and a bit-line capping layer 309 on the substrate 101. Next, a photolithography process and an etching process can be applied to pattern the aforementioned layers. Multiple patterned layers can together form multiple bit-line structures 301.

[0147] In a cross-sectional view, multiple bitline structures 301 may be formed on multiple bitline contact points 311. Each upper surface 309TS of the multiple bitline cover layers 309 can be considered as an upper surface of the multiple bitline structures 301. In some embodiments, such as Figure 13 As shown, during the etching process, portions of multiple bitline contact points 311 can be removed. In a top view, multiple bitline structures 301 can extend along a second axis Y and are parallel to each other. Multiple bitline structures 301 can be configured along a first axis X. That is, multiple bitline structures 301 can intersect with multiple wordline structures 201. Multiple bitline structures 301 can be electrically coupled to the source region 107-1 via multiple bitline contact points 311.

[0148] For example, the multiple bit-line conductive layers 303 may comprise polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, titanium, tantalum, tungsten, copper, aluminum, tungsten silicide, cobalt silicide, or titanium silicide. For example, the multiple bit-line intermediate conductive layers 305 may comprise titanium nitride or tantalum nitride. For example, the multiple bit-line conductive layers 307 may comprise tungsten, tantalum, titanium, copper, or aluminum. The multiple bit-line intermediate conductive layers 305 may reduce or potentially prevent the diffusion of conductive material in the multiple bit-line conductive layers 307 toward the multiple bit-line conductive layers 303. For example, the multiple bit-line capping layers 309 may comprise silicon nitride, silicon nitride oxide, silicon oxynitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride.

[0149] Please refer to Figures 12 to 14 A spacer material layer can be formed to cover the multiple bitline structures 301 and the substrate 101. For example, the spacer material may comprise silicon oxide, silicon nitride, silicon boron nitride, silicon nitride oxide, or silicon oxynitride. An etching process, such as an anisotropic dry etching process, can be performed to remove portions of the spacer material layer and simultaneously form multiple bitline spacers 313, which are attached to the sidewalls of the multiple bitline structures 301. In some embodiments, such as... Figure 13 As shown, some portions of the lower surfaces 313BS of the multiple bit line spacers 313 can be approximately coplanar with the lower surfaces 311BS of the multiple bit line contact points 311.

[0150] In some embodiments, after the plurality of bit line contacts 311 are formed, an interlayer may be formed on the substrate 101. A plurality of bit line structures 301 may be formed on this interlayer. For example, the interlayer may comprise a carbon-doped oxide, carbon-incorporated silicon oxide, or nitrogen-doped silicon carbide.

[0151] Please refer to Figure 15 and Figure 16 A first dielectric layer 109 is formed to cover the substrate 101 and the plurality of bit line structures 301. A planarization process, such as chemical mechanical polishing, may be performed until the upper surfaces 309TS of the plurality of bit line capping layers 309 are exposed to remove excess material and provide a generally flat surface for subsequent processing steps. For example, the first dielectric layer 109 may comprise silicon oxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, a low-k dielectric material, or a combination thereof. The low-k dielectric material may have a dielectric constant less than 3.0, or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant less than 2.0.

[0152] Figure 17 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 18 and Figure 19 Examples along Figure 17 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0153] Please refer to Figure 1 and Figures 17 to 19In step S17, multiple capacitor contact point openings 703 may be formed to extend into the substrate 101.

[0154] Please refer to Figures 17 to 19 A photolithography process and a subsequent etching process can be performed to form a plurality of capacitor contact openings 703, which extend along the first dielectric layer 109 and to the upper portion of the substrate 101. Some portions of the plurality of drain regions 107-3 may be exposed via the plurality of capacitor contact openings 703. In a top view, the plurality of capacitor contact openings 703 may be located at each end of the active region 105.

[0155] Figure 20 and Figure 21 Examples along Figure 17 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure. Figure 22 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 23 and Figure 24 Examples along Figure 22 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0156] Please refer to Figure 1 and Figures 20 to 24 In step S19, multiple capacitor contact point structures 401 can be formed in multiple capacitor contact point openings 703.

[0157] Please refer to Figure 20 and Figure 21 The conductive layer 403 under the multiple capacitor contact points can be formed in the multiple capacitor contact point openings 703 respectively. In some embodiments, such as Figure 21 As shown, the lower surfaces 403BS of the multiple capacitor contact conductive layers 403 may be located on a vertical plane, which is lower than a vertical plane of the lower surfaces 313BS of the multiple bit line spacers 313. For example, the multiple capacitor contact conductive layers 403 may comprise polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium. In some embodiments, the multiple capacitor contact conductive layers 403 may be doped with a dopant, such as phosphorus, arsenic, antimony, or boron. For example, the multiple capacitor contact intermediate conductive layers 405 may comprise cobalt silicide, titanium silicide, nickel silicide, nickel-platinum silicide, or tantalum silicide. The upper surfaces of the multiple capacitor contact intermediate conductive layers 405 may be located on a vertical plane, which is lower than a vertical plane of the upper surfaces 309TS of the multiple bit line capping layers 309.

[0158] A first conductive layer 801 can be formed to completely fill the multiple capacitor contact point openings 703 and cover the first dielectric layer 109 and the multiple bit line capping layers 309. For example, the first conductive layer 801 can be titanium nitride or tantalum nitride. The conductive layer 405 between the multiple capacitor contacts can reduce the contact resistance between the first conductive layer 801 and the conductive layer 403 under the multiple capacitor contacts.

[0159] Please refer to Figures 22 to 24 A planarization process, such as chemical mechanical polishing, can be performed until the upper surfaces of the multiple bit line capping layers 309 are exposed to remove excess material, providing a generally flat surface for subsequent processing steps, and simultaneously forming multiple conductive layers 407 on the capacitor contacts over the intermediate conductive layers 405. At this stage, the upper surfaces 407TS of the multiple capacitor contact conductive layers 407 are generally coplanar with the upper surfaces of the multiple bit line capping layers 309.

[0160] Multiple capacitor contact point lower conductive layers 403, multiple capacitor contact point intermediate conductive layers 405, and multiple capacitor contact point upper conductive layers 407 can together form a multiple capacitor contact point structure 401. Each upper surface 407TS of the multiple capacitor contact point upper conductive layers 407 can be considered as each upper surface of the multiple capacitor contact point structure 401. The multiple capacitor contact point structure 401 can be electrically coupled to multiple drain regions 107-3.

[0161] Figure 25 and Figure 26 Examples along Figure 22 The cross-sectional view along lines A-A' and B-B' illustrates a portion of the manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0162] Please refer to Figure 1 , Figure 25 and Figure 26 In step S21, the upper surfaces of the multiple bit line structures 301 can be recessed.

[0163] Please refer to Figure 25 and Figure 26A recessing process can be performed to remove portions of multiple bitline capping layers 309, a first dielectric layer 109, and multiple bitline spacers 313. For example, the recessing process can be isotropic dry etching, anisotropic dry etching, or wet etching. During the recessing process, the etching rate of the multiple bitline capping layers 309 on the conductive layer 407 at the multiple capacitor contacts can be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1. During the recessing process, the etching rate of the first dielectric layer 109 on the conductive layer 407 at the multiple capacitor contacts can be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1. During the recessing process, the etching rate of the multiple bitline spacers 313 on the conductive layer 407 at the multiple capacitor contacts can be between approximately 100:1 and approximately 10:1, and approximately 10:1.

[0164] After the recessing process, the upper surfaces 309TS of the plurality of bit line capping layers 309 can be recessed. That is, the conductive layer 407 on the plurality of capacitor contacts can protrude from the plane where the upper surfaces 309TS of the plurality of bit line capping layers 309 are located. The upper surfaces 407TS of the conductive layer 407 on the plurality of capacitor contacts can be located at a vertical plane, which is higher than a vertical plane of the upper surfaces 309TS of the plurality of bit line capping layers 309, the upper surfaces 313TS of the plurality of bit line spacers 313, and the upper surfaces of the first dielectric layer 109. In some embodiments, the upper surfaces 309TS of the plurality of bit line capping layers 309, the upper surfaces 313TS of the plurality of bit line spacers 313, and the upper surfaces of the first dielectric layer 109 can be substantially coplanar.

[0165] It should be understood that the term "about" modifies a quantity of an ingredient, component, or reactant of this disclosure, which is a possible variation in numerical quantity, for example, through typical measurements and liquid handling procedures used to produce concentrates or solutions. Furthermore, variation can arise from unintentional errors in the measurement procedures applied to the manufacture of components or the implementation of multiple methods or similar methods, differences in manufacturing, source, or purity of the component. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0166] Figure 27 Example edge Figure 22 A cross-sectional view along line A-A' illustrates a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 28 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 29 Example edge Figure 28 A cross-sectional view along line A-A' illustrates a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0167] Please refer to Figure 1 and Figures 27 to 29 In step S23, multiple landing pads 501 can be formed to partially cover multiple capacitor contact point structures 401.

[0168] Please refer to Figure 27 A second conductive layer 803 can be formed to cover the conductive layers 407 on the plurality of capacitor contacts, the plurality of bit line capping layers 309, and the plurality of bit line spacers 313. In some embodiments, the second conductive layer 803 may comprise a material that has an etch selectivity relative to the conductive layers 407 on the plurality of capacitor contacts. In some embodiments, for example, the second conductive layer 803 may be tungsten, copper, or aluminum.

[0169] Please refer to Figure 28 and Figure 29A photolithography process and a subsequent etching process can be performed to remove portions of the second conductive layer 803 and transform the second conductive layer 803 into multiple landing pad layers 501. During etching, the etching rate of the second conductive layer 803 on the conductive layer 407 at the multiple capacitor contacts can be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1.

[0170] For ease of description, only a landing pad 501 and a conductive layer 407 on the capacitor contact point are described. In a cross-sectional view, the landing pad 501 may cover a portion of the upper surface 407TS of the conductive layer 407 on the capacitor contact point and an upper portion of the sidewall 407SW of the conductive layer 407 on the capacitor contact point. In other words, the landing pad 501 may partially cover the conductive layer 407 on the capacitor contact point. In a top view, the landing pad 501 may be offset relative to the conductive layer 407 on the capacitor contact point.

[0171] The landing pad layer 501, which partially covers the conductive layer 407 on the capacitor contact point, increases the contact surface between the landing pad layer 501 and the conductive layer 407 on the capacitor contact point. This reduces the resistance between the landing pad layer 501 and the conductive layer 407 on the capacitor contact point, thereby reducing the power consumption of the semiconductor device 1A. Furthermore, the protruding conductive layer 407 on the capacitor contact point provides sufficiently strong support for the landing pad layer 501.

[0172] Figures 30 to 34 Another embodiment of this disclosure is illustrated along Figure 12 The cross-sectional view along line A-A' illustrates a portion of the manufacturing process of semiconductor device 1B according to an embodiment of the present disclosure.

[0173] Please refer to Figure 30 It can provide something similar to Figure 13 The image shows an intermediate semiconductor device. The fabrication technique for the multiple sacrificial spacers 315 is similar to that shown below. Figure 13 A process is shown for a plurality of bit-line spacers 313. In some embodiments, the plurality of sacrificial spacers 315 may comprise a material having an etch selectivity relative to the plurality of bit-line capping layers 309 and the first dielectric layer 109. In some embodiments, for example, the plurality of sacrificial spacers 315 may comprise an energy-removable material, such as a thermally degradable material, a photodegradable material, an electron beam degradable material, or a combination thereof. The fabrication technique of the first dielectric layer 109 may be similar to that shown below. Figure 15 The program shown.

[0174] Please refer to Figure 31 In some embodiments, another planarization process may be applied to, for example... Figure 30 The intermediate semiconductor element is shown to expose the upper surfaces of a plurality of sacrificial spacers 315. In some embodiments, a planarization process for the first dielectric layer 109 may be performed until the upper surfaces of the plurality of sacrificial spacers 315 are exposed. Next, a removal process may be performed to remove the plurality of sacrificial spacers 315. After the removal process, a plurality of first trenches 705 may be formed in the aforementioned locations occupied by the plurality of sacrificial spacers 315.

[0175] In some embodiments, the removal process may be an etching process, such as dry etching or wet etching. During the etching process, the etch ratio of the plurality of sacrificial spacers 315 to the first dielectric layer 109 may be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1. During the etching process, the etch ratio of the plurality of sacrificial spacers 315 to the plurality of bit line capping layers 309 may be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1.

[0176] In some embodiments, an energy treatment may be applied to remove a plurality of sacrificial spacers 315 comprising energy-removable material. By applying an energy source thereto, such as Figure 30 The intermediate semiconductor element shown performs energy processing. The energy source may include heat, light, or a combination thereof. When heat is used as an energy source, the temperature of the energy processing may be between approximately 800°C and approximately 900°C. When light is used as an energy source, ultraviolet light may be applied.

[0177] Please refer to Figure 32 A first insulating material 805 may be conformally formed in a plurality of first trenches 705 and cover the first dielectric layer 109 and a plurality of bit line capping layers 309. A second insulating material 807 may be formed on the first insulating material 805 and may completely fill the plurality of first trenches 705.

[0178] In some embodiments, for example, the first insulating material 805 may be silicon nitride, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbide silicon nitride. In some embodiments, for example, the second insulating material 807 may be silicon oxide.

[0179] Please refer to Figure 33A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the multiple bit-line capping layers 309 is exposed to remove excess material and provide a generally flat surface for subsequent processing steps. After the planarization process, the first isolation material 805 can be converted into a plurality of first isolation layers 603. The second isolation material 807 can be converted into a plurality of second isolation layers 605. The plurality of first isolation layers 603 and the plurality of second isolation layers 605 together form a plurality of isolation structures 601.

[0180] For ease of description, only one isolation structure 601 is described. A first isolation layer 603 may have a U-shaped cross-sectional profile. The first isolation layer 603 may include a lower portion 603B and two side portions 603S. The lower portion 603B may be linear in shape and may be horizontally disposed on the substrate 101, particularly on the drain region 107-3. The two side portions 603S may be linear in shape and may be vertically connected to both ends of the lower portion 603B. One side portion 603S may be attached to the sidewall of a plurality of bit structures 301, and the other side portion 603S may be attached to the sidewall of a plurality of capacitor contact point structures 401. A second isolation layer 605 may be disposed between the lower portion 603B and the two side portions 603S. In some embodiments, the lower portion 603B may be horizontally disposed in the substrate 101 and on the source region 107-1. One side portion 603S may be attached to the sidewall of the plurality of capacitor contact point structures 401 and the sidewall of the bit line contact point 311.

[0181] Please refer to Figure 34 The fabrication technique for the multiple capacitor contact point structure 401 can be similar to that of... Figures 17 to 24 The procedure shown is an example of a recessed process. The recessed process can be performed similarly to... Figure 25 The procedure shown is as follows. The fabrication technology for multiple landing pads 501 can be similar to that shown below. Figures 27 to 29 The procedure shown is as follows. Multiple landing pads 501 can be formed to cover some isolation structures 601.

[0182] Figure 35 and Figure 36 Another embodiment of this disclosure is illustrated along Figure 12 The cross-sectional view along line A-A' illustrates a portion of the manufacturing process of a semiconductor device 1C according to an embodiment of the present disclosure.

[0183] Please refer to Figure 35 It can provide, for example Figure 33 An intermediate semiconductor device is shown. A removal process can be performed to remove multiple second isolation layers 605 (e.g., Figure 33(As shown). Multiple air gaps 607 can be formed simultaneously in locations previously occupied by multiple second isolation layers 605. In particular, each air gap 607 can be formed between the lower portion 603B and the two side portions 603S. Multiple first isolation layers 603 and multiple air gaps 607 can together form multiple isolation structures 601. Multiple air gaps 607 can reduce parasitic capacitance between multiple capacitor contact structures 401 and multiple bit line structures 301. Therefore, the performance of semiconductor device 1C can be improved.

[0184] In some embodiments, the second isolation layer 605 may comprise a material having an etch selectivity relative to the first isolation layer 603. The removal process may be an etching process, such as dry etching or wet etching. During the etching process, the etch ratio of the plurality of second isolation layers 605 to the plurality of first isolation layers 603 may be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1. During the etching process, the etch ratio of the plurality of second isolation layers 605 to the first dielectric layer 109 may be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1. During the etching process, the etch ratio of the plurality of second isolation layers 605 to the plurality of bit line capping layers 309 may be between approximately 100:1 and approximately 10:1, or between approximately 20:1 and approximately 10:1.

[0185] In some embodiments, for example, the plurality of second insulating layers 605 include an energy-removable material, such as a thermally decomposable material, a photodecomposable material, an electron beam decomposable material, or a combination thereof. The removal process may apply an energy treatment to remove the plurality of second insulating layers 605. The energy treatment can be performed by applying an energy source to the plurality of second insulating layers 605. The energy treatment may include heat, light, or a combination thereof. When heat is used as an energy source, a temperature for the energy treatment may be between approximately 800°C and approximately 900°C. When light is used as an energy source, ultraviolet light may be applied.

[0186] Please refer to Figure 36 The fabrication technique for the multiple capacitor contact point structure 401 can be similar to that of... Figures 17 to 24 The procedure shown is an example of a recessed process. A similar process can be performed as follows: Figure 25 The procedure shown is as follows. The fabrication technology for multiple landing pads 501 can be similar to that shown below. Figures 17 to 29 The procedure shown is as follows. Multiple landing pads 501 can be formed to cover some isolation structures 601.

[0187] Figures 37 to 39 Another embodiment of this disclosure is illustrated along Figure 17The cross-sectional view along line A-A' illustrates a portion of the manufacturing process of a semiconductor device 1D according to an embodiment of the present disclosure.

[0188] Please refer to Figure 37 It can provide, for example Figure 18 The diagram shows an intermediate semiconductor device. A third conductive material 809 can be formed to completely fill the multiple capacitor contact openings 703 and cover the multiple bit line structures 301 and the first dielectric layer 109. For example, the third conductive material 809 can be polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium.

[0189] Please refer to Figure 38 Similar to the operation performed on the third conductive material 809 of this layer, such as... Figures 22 to 25 The procedure shown is as follows. The third conductive material 809 can be converted into multiple capacitor contact structure 401. Each capacitor contact structure 401 may include only one capacitor contact under conductive layer 403, which comprises polysilicon, polysilicon germanium, or polysilicon germanium. The capacitor contact under conductive layer 403 may protrude from the plane where the upper surfaces 309TS of the multiple bit line capping layers 309 are located.

[0190] Please refer to Figure 39 The manufacturing technology for multiple landing cushion layers 501 can be similar to that of... Figures 27 to 29 The landing pad 501 may partially cover the conductive layer 403 below the capacitor contact point. In particular, the landing pad 501 may cover a portion of the upper surface 403TS of the conductive layer 403 below the capacitor contact point and an upper portion of the sidewall 403SW of the conductive layer 403 below the capacitor contact point.

[0191] Figure 40 and Figure 41 Another embodiment of this disclosure is illustrated along Figure 17 The cross-sectional view along line A-A' illustrates a portion of the manufacturing process of the semiconductor device 1E according to an embodiment of the present disclosure.

[0192] Please refer to Figure 40 It can provide, for example Figure 38 An intermediate semiconductor device is shown. Next, a layer of conductive material (not shown) can be formed on it. Figure 38On the intermediate semiconductor element shown. For example, the conductive material may include titanium, nickel, platinum, tantalum, or cobalt. A heat treatment may be performed. During the heat treatment, multiple metal molecules of the conductive material layer may chemically react with multiple molecules of the conductive layer 403 under the multiple capacitor contacts to form multiple adjustment layers 317. The multiple adjustment layers 317 may include titanium silicide, nickel silicide, nickel-platinum silicide, tantalum silicide, or cobalt silicide. The heat treatment may be a dynamic surface annealing process. After the heat treatment, a cleaning process may be performed to remove unreacted conductive material. The cleaning process may use an etchant, such as hydrogen peroxide, and an SC-1 (standard clean-1) solution.

[0193] Multiple adjustment layers 317 may have a thickness between approximately 2 nm and approximately 20 nm. Each adjustment layer 317 may cover the upper surface 403TS of the conductive layer 403 below the capacitor contact and the upper part of each sidewall 403SW of the conductive layer 403 below the capacitor contact.

[0194] Please refer to Figure 41 The manufacturing technology for multiple landing cushion layers 501 can be similar to that of... Figures 27 to 29 The procedure is shown. The landing pad 501 may partially cover the conditioning layer 317. In particular, the landing pad 501 may cover a portion of the upper surface 317TS of the conditioning layer 317 and one of the sidewalls 317SW of the conditioning layer 317.

[0195] Figures 42 to 44 Another embodiment of this disclosure is illustrated along Figure 17 The cross-sectional view along line A-A' illustrates a portion of the manufacturing process of a semiconductor element 1F according to an embodiment of the present disclosure.

[0196] Please refer to Figure 42 It can provide, for example Figure 18 The diagram shows an intermediate semiconductor device. A fourth conductive material 811 can be formed to completely fill the multiple capacitor contact openings 703 and cover the multiple bit line structures 301 and the first dielectric layer 109. For example, the fourth conductive material 811 can be titanium nitride or tantalum nitride.

[0197] Please refer to Figure 43 Similar to that shown, the fourth conductive material 811 in this layer can be subjected to... Figures 22 to 25The procedure shown is as follows. The fourth conductive material 811 can be converted into multiple capacitor contact structure 401. Each capacitor contact structure 401 may include only one capacitor contact under conductive layer 403, and the capacitor contact under conductive layer 403 comprises titanium nitride or tantalum nitride. The capacitor contact under conductive layer 403 may protrude from the plane where the upper surfaces 309TS of the multiple bit line capping layers 309 are located.

[0198] Please refer to Figure 44 The manufacturing technology for multiple landing cushion layers 501 can be similar to that of... Figures 27 to 29 The procedure shown is as follows. The landing pad 501 may partially cover the conductive layer 403 below the capacitor contact point. In particular, the landing pad 501 may cover a portion of the upper surface 403TS of the conductive layer 403 below the capacitor contact point and an upper portion of the sidewall 403SW of the conductive layer 403 below the capacitor contact point.

[0199] One embodiment of this disclosure provides a semiconductor device, including: a substrate; a capacitor contact structure protruding from the substrate; and a landing pad layer covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0200] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing an upper surface of the bit line structure; and forming a landing pad layer to cover a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0201] Due to the design of the semiconductor device disclosed herein, the contact surface between the landing pad layer 501 and the conductive layer 407 at the capacitor contact point can be increased. Accordingly, the resistance between the landing pad layer 501 and the conductive layer 407 at the capacitor contact point can be reduced. Therefore, the power consumption of the semiconductor device 1A can be reduced. Furthermore, the protruding conductive layer 407 at the capacitor contact point can provide sufficiently strong support for the landing pad layer 501.

[0202] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0203] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this invention that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described in this invention can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A semiconductor device, comprising: a substrate; a capacitor contact structure protruding from the substrate; and a landing pad layer covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure; a bit line structure on the substrate and beside the capacitor contact structure; an isolation structure between the bit line structure and the capacitor contact structure, the isolation structure comprising a first isolation layer and a second isolation layer, wherein the first isolation layer comprises a lower portion horizontally disposed on the substrate and two side portions vertically connected to two ends of the lower portion.

2. The semiconductor device of claim 1, wherein an upper surface of the bit line structure is at a vertical level lower than a vertical level of the upper surface of the capacitor contact structure.

3. The semiconductor device of claim 2, further comprising a bit line gap spacer between the capacitor contact structure and the bit line structure, wherein an upper surface of the bit line gap spacer is coplanar with the upper surface of the bit line structure.

4. The semiconductor device of claim 3, wherein the bit line structure comprises a bit line lower conductive layer on the substrate, a bit line middle conductive layer on the bit line lower conductive layer, a bit line upper conductive layer on the bit line middle conductive layer, and a bit line cap layer on the bit line upper conductive layer.

5. The semiconductor device of claim 4, wherein the capacitor contact structure comprises a capacitor contact lower conductive layer protruding from the substrate, a capacitor contact middle conductive layer on the capacitor contact lower conductive layer, and a capacitor contact upper conductive layer on the capacitor contact middle conductive layer, and the landing pad layer covers a portion of an upper surface of the capacitor contact upper conductive layer and an upper portion of a sidewall of the capacitor contact upper conductive layer.

6. The semiconductor device of claim 5, wherein the capacitor contact lower conductive layer comprises polysilicon, polygermanium, or polysilicon germanium, the capacitor contact middle conductive layer comprises cobalt silicide, nickel silicide, nickel platinum silicide, or tantalum silicide, and the capacitor contact upper conductive layer comprises titanium nitride or tantalum nitride.

7. The semiconductor device of claim 6, wherein a lower surface of the capacitor contact structure is at a vertical level lower than a vertical level of a lower surface of the bit line gap spacer.

8. The semiconductor device of claim 6, further comprising a bit line contact under the bit line lower conductive layer.

9. The semiconductor device of claim 8, wherein a lower surface of the bit line gap spacer is coplanar with a lower surface of the bit line contact.

10. The semiconductor device of claim 9, further comprising a plurality of source / drain regions under the bit line contact and the capacitor contact structure. ​ 11. The semiconductor device of claim 2, wherein the second isolation layer is located between the lower portion and the two side portions.

12. The semiconductor device of claim 11, wherein the first isolation layer comprises silicon nitride and the second isolation layer comprises silicon oxide.

13. The semiconductor device of claim 4, wherein the capacitor contact structure includes a capacitor contact lower conductive layer protruding from the substrate, the landing pad layer covers a portion of an upper surface of the capacitor contact lower conductive layer and an upper portion of a sidewall of the capacitor contact lower conductive layer, and the capacitor contact lower conductive layer comprises polysilicon, polygermanium, or polysilicon germanium.

14. The semiconductor device of claim 13, further comprising a tuning layer located between the landing pad layer and the capacitor contact lower conductive layer, wherein the tuning layer comprises cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or tantalum silicide.

15. The semiconductor device of claim 4, wherein the capacitor contact structure includes a capacitor contact lower conductive layer protruding from the substrate, the landing pad layer covers a portion of an upper surface of the capacitor contact lower conductive layer and an upper portion of a sidewall of the capacitor contact lower conductive layer, and the capacitor contact lower conductive layer comprises titanium nitride or tantalum nitride.

16. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing an upper surface of the bit line structure; and forming a landing pad layer to cover a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure; wherein forming the landing pad layer comprises: forming a conductive layer to cover an upper portion of the capacitor contact structure; and performing an etching process to transform the conductive layer into the landing pad layer; wherein, during the etching process, an etch rate of the conductive layer to the capacitor contact structure is between about 100: 1 and about 10:

1.

17. The method of fabricating a semiconductor device of claim 16, wherein the bit line structure includes a bit line lower conductive layer formed on the substrate, a bit line middle conductive layer formed on the bit line lower conductive layer, a bit line upper conductive layer formed on the bit line middle conductive layer, and a bit line cap layer formed on the bit line upper conductive layer.

18. The method of fabricating a semiconductor device of claim 16, wherein the capacitor contact structure comprises polysilicon, polygermanium, polysilicon germanium, cobalt silicide, titanium silicide, nickel silicide, nickel platinum silicide, or titanium nitride or tantalum nitride. ​

Images