Semiconductor device anti-static structure and method of manufacturing the same

Abstract

The application discloses a semiconductor device anti-static structure and a preparation method thereof. The semiconductor device anti-static structure is prepared by growing an InGaP layer, an N-type GaAs layer, an I layer and a P-type GaAs layer on an N-type semiconductor layer, evaporating and etching two spaced first metal layers on the surface of the P-type GaAs layer, controlling a wet etching process to form PIN semiconductor layers with a width smaller than the first metal layers under the first metal layers, coating photoresist to a thickness exceeding the first metal layers, exposing and developing to open a window on the first metal layers and in the region between the two PIN semiconductor layers, evaporating metal and high-temperature annealing to form an ohmic contact second metal layer on the N-type semiconductor layer and an ohmic contact third metal layer on the first metal layers, and the second metal layer has a gap with the two PIN semiconductor structures. The preparation method of the semiconductor device anti-static structure can make the second metal layer very wide, greatly reduce the series resistance between the two PINs, and improve the anti-static capability of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular, to an anti-static structure of a semiconductor device and a preparation method thereof. BACKGROUND

[0002] In the whole life cycle of an integrated circuit (IC), from manufacturing, packaging, transportation, assembly, and even in the finished IC product, it is always subject to the impact of electro-static discharge (ESD). When a certain amount of static charge is accumulated in the external environment of the chip or inside the chip, the instantaneous current (peak value up to several amperes) or voltage generated when the static charge flows into or out of the chip through the pins of the chip will damage the integrated circuit and cause the chip to malfunction. With the development of the semiconductor industry, the feature size is further reduced, and the element integration density is increased, and the possibility of electronic components being damaged by static electricity is greatly increased.

[0003] In the prior art, in order to prevent the semiconductor chip (Die) from being electro-statically broken down, an anti-static bypass is usually designed as two series reverse PIN anti-static structures. For example, one kind of anti-static bypass of a semiconductor chip is to connect the anode of one diode to the base region of a transistor and the anode of another diode to the collector region of the transistor through a metal wire. When electro-static discharge occurs in the semiconductor chip, a large voltage difference is formed between the base region of the device and the substrate, which will break down the base region of the device. Therefore, two series reverse diodes are added near the base region and the collector region. When electro-static discharge occurs, no matter the direction of the current flow, one of the two diodes will be turned on, thereby clamping the voltage difference between the base region and the substrate, and the base region will not be broken down. However, the anti-static capability of the two series reverse PIN anti-static structures is mainly affected by the resistance Rt between the back-to-back structures, and the value of the resistance Rt is determined by the concentration and thickness of the N+ doped layer of the transistor and the distance between the back-to-back structures. Among them, the N+ doped layer is determined by the index of the transistor, and the distance between the back-to-back structures is limited by the wet etching process and cannot be too narrow, which limits the anti-static capability of the back-to-back structure.

[0004] The existing process is to coat photoresist, expose and develop to open a window, and evaporate a layer of metal between the two PIN back-to-back structures to reduce the resistance Rt between the back-to-back structures. Since photolithography has a bias and overlay also has a bias, the minimum exposure can only be 1.6 μm, and the evaporated metal cannot be made wide enough, the resistance Rt between the back-to-back structures cannot be further reduced, and the anti-static capability is still limited.

[0005] Therefore, it is urgent to provide a new conductor device anti-static structure to solve the problem of limited anti-static ability of a semiconductor chip. SUMMARY

[0006] The semiconductor device anti-static structure is prepared by growing an InGaP layer, an N-type GaAs layer, an I layer, and a P-type GaAs layer on an N-type semiconductor layer, evaporating and etching two spaced first metal layers on the surface of the P-type GaAs layer, controlling the etching liquid and time of a wet etching process to form a PIN semiconductor structure with a width smaller than the first metal layer under the first metal layer, coating photoresist to a thickness exceeding the first metal layer, exposing and developing to open a window above the first metal layer and in the region between the two PIN semiconductor structures, evaporating metal to form a second metal layer with a gap from the two PIN semiconductor structures above the N-type semiconductor layer and a third metal layer above the first metal layer, and high-temperature annealing to form an ohmic contact between the second metal layer and the N-type semiconductor layer and an ohmic contact between the third metal layer and the first metal layer. The preparation method of the semiconductor device anti-static structure can make the second metal layer very wide, break through the limitation of the minimum line width of the traditional photolithography process, greatly reduce the series resistance between the two PINs, and improve the anti-static ability of the chip.

[0007] The embodiment of the present application is implemented as follows:

[0008] In one aspect of the present application, a semiconductor device anti-static structure is provided, which comprises an N-type semiconductor layer, two PIN semiconductor layers formed above the N-type semiconductor layer and spaced apart, a first metal layer formed above the PIN semiconductor layers, and a second metal layer formed above the N-type semiconductor layer and between the two PIN semiconductor layers, wherein the first metal layer has a protruding portion extending to the middle of the two PIN semiconductor layers beyond the PIN semiconductor layers in the width direction, the second metal layer has a gap from each of the two PIN semiconductor layers, and the width of the protruding portion is equal to the width of the corresponding gap below the protruding portion.

[0009] Optionally, the spacing distance between the two PIN semiconductor layers is 1.5 μm to 4 μm.

[0010] Optionally, the thickness of the second metal layer is 1500 Å to 3500 Å.

[0011] Optionally, the width of the protruding portion and the gap is 0.5 μm to 1 μm.

[0012] Optionally, the second metal layer is in ohmic contact with the N-type semiconductor layer.

[0013] Optionally, the first metal layer further has a third metal layer above it, and the second metal layer and the third metal layer have the same thickness.

[0014] Optionally, the second metal layer and the third metal layer are Au / Ge / Ni / Au.

[0015] In another aspect of the present application, a preparation method of an anti-static structure of a semiconductor device is provided, comprising:

[0016] Step one, growing an InGaP layer, an N-type GaAs layer, an I layer, and a P-type GaAs layer on an N-type semiconductor layer, coating photoresist on the surface of the P-type GaAs layer, exposing, developing, and evaporating to form two spaced first metal layers;

[0017] Step two, wet etching the P-type GaAs layer, the I layer, the N-type GaAs layer, and the InGaP layer below the first metal layer to expose the N-type semiconductor layer, and forming a PIN semiconductor layer with a width smaller than the first metal layer below the two spaced first metal layers, the PIN semiconductor layer being composed of the InGaP layer, the N-type GaAs layer, the I layer, and the P-type GaAs layer from bottom to top;

[0018] Step three, coating photoresist to a thickness exceeding the first metal layer, exposing, developing, and opening a window above the first metal layer and between the two first metal layers;

[0019] Step four, evaporating metal to form a second metal layer with a gap from the two PIN semiconductor layers above the N-type semiconductor layer, and a third metal layer above the first metal layer; high-temperature annealing to form an ohmic contact between the second metal layer and the N-type semiconductor layer, and an ohmic contact between the third metal layer and the first metal layer.

[0020] Optionally, the method further comprises step five, depositing a passivation layer above the N-type semiconductor layer, above the second metal layer, above the third metal layer, on the side of the first metal layer, and on the side of the PIN semiconductor layer, and etching the passivation layer to form a lead opening above the third metal layer.

[0021] Optionally, in step two, the P-type GaAs layer, the I layer, and the N-type GaAs layer are etched by a wet etching solution of H3PO4:H2O2:H2O=1:1:20, with an etching time of 15s to 20s for the P-type GaAs layer, 130s to 140s for the I layer, and 7s to 10s for the N-type GaAs layer; the InGaP layer is etched by a wet etching solution of H3PO4:HCL=1:3, with an etching time of 50s to 60s.

[0022] The present application has the following advantages:

[0023] The application provides a semiconductor device anti-static structure and a preparation method thereof. First, an InGaP layer, an N-type GaAs layer, an I layer and a P-type GaAs layer are grown on an N-type semiconductor layer, and two spaced first metal layers are formed on the surface of the P-type GaAs layer by evaporation and etching; second, the etching liquid is modulated and the etching time is appropriately prolonged to form a PIN semiconductor structure with a width smaller than the first metal layer under the first metal layer; third, photoresist is coated to a thickness greater than the first metal layer, exposed, developed, and a window is opened above the first metal layer and between the two PIN semiconductor structures; then, metal is evaporated to form a second metal layer with a gap between the two PIN semiconductor structures above the N-type semiconductor layer and a third metal layer above the first metal layer; high-temperature annealing is performed to form an ohmic contact between the second metal layer and the N-type semiconductor layer and an ohmic contact between the third metal layer and the first metal layer; finally, a passivation layer is deposited on the N-type semiconductor layer, the second metal layer, the third metal layer, the side of the first metal layer and the PIN semiconductor layer, and a lead opening is formed on the third metal layer by etching the passivation layer. The preparation method of the semiconductor device anti-static structure uses the first metal layer to block the etching liquid, and during the process of etching downward to the N-type semiconductor layer in the non-first metal layer area to form two PIN semiconductor structures spaced from each other, the etching time is appropriately prolonged, the etching liquid will over-etch a part of the area below the edge of the first metal layer (i.e. the side of the PIN semiconductor layer), so that the edge of the first metal layer forms a convex part; in the subsequent metal evaporation process, the blockage of the convex part prevents the evaporated metal from depositing on the N-type semiconductor layer below the area, and there is no blockage above the N-type semiconductor layer between the two first metal layers, so the evaporated metal forms a second metal layer with a gap between the two PIN semiconductor layers, the width of the convex part is equal to the width of the gap formed below it; after high-temperature annealing, the second metal layer is in ohmic contact with the N-type semiconductor layer, which increases the cross-sectional area and reduces the resistance between the two PIN semiconductor layers due to the lower resistivity of the second metal layer. The preparation method can make the second metal layer very wide, breaking through the limit of the minimum line width (1.6 μm) of traditional photolithography process, greatly reducing the series resistance between the two PIN semiconductor structures, and further improving the anti-static ability of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0025] Figure 1One of the state schematic diagrams of the semiconductor device anti-static structure preparation method provided by the embodiment of the present application;

[0026] Figure 2 The second state schematic diagram of the semiconductor device anti-static structure preparation method provided by the embodiment of the present application;

[0027] Figure 3 The third state schematic diagram of the semiconductor device anti-static structure preparation method provided by the embodiment of the present application;

[0028] Figure 4 The fourth state schematic diagram of the semiconductor device anti-static structure preparation method provided by the embodiment of the present application;

[0029] Figure 5 The fifth state schematic diagram of the semiconductor device anti-static structure preparation method provided by the embodiment of the present application;

[0030] Figure 6 The equivalent circuit diagram of the semiconductor device anti-static structure provided by the embodiment of the present application.

[0031] Icon: 1-N type semiconductor layer; 2-InGaP layer; 3-N type GaAs layer; 4-I layer; 5-P type GaAs layer; 6-first metal layer; 7-isolation ring; 8-second metal layer; 9-third metal layer; 10-fourth metal layer. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0034] In the description of the present application, it should be noted that the terms "center", "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the positional relationship in the usual use of the product of the present application, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for differentiation in description and cannot be understood as indicating or implying relative importance.

[0035] Please refer to Figures 1-6 The embodiment provides a preparation method of a semiconductor device anti-static structure.

[0036] First, grow InGaP layer 2, N-type GaAs layer 3, I layer 4, and P-type GaAs layer 5 on N-type semiconductor layer 1, coat photoresist on the surface of P-type GaAs layer 5, expose, develop, and evaporate to form two first metal layers 6 with a spacing of 1.5 μm to 4 μm, and the material of the first metal layer 6 is Pt / Ti / Pt / Au / Ti with a thickness of Pt-50Å / Ti-500Å / Pt-500Å / Au-800Å / Ti-30Å;

[0037] Second, wet etch P-type GaAs layer 5, I layer 4, and N-type GaAs layer 3 layer by layer, the etching solution is H3PO4:H2O2:H2O=1:1:20, and the etching time is 15s to 20s for P-type GaAs layer 5, 130s to 140s for I layer 4, and 7s to 10s for N-type GaAs layer 3; then wet etch InGaP layer 2 as an etching stop layer, the etching solution is H3PO4:HCL=1:3, and the etching time is 50s to 60s; the etching solution is blocked by the first metal layer 6, and etching is performed downward in the area other than the first metal layer 6 to expose N-type semiconductor layer 1, in the process of forming two PIN semiconductor layers spaced apart and composed of P-type GaAs layer 5, I layer 4, N-type GaAs layer 3, and InGaP layer 2, the etching time is appropriately prolonged, a part of the area below the edge of the first metal layer 6 (i.e. the side surface of P-type GaAs layer 5, I layer 4, N-type GaAs layer 3, and InGaP layer 2) is over-etched, and a convex part is formed at the edge of the first metal layer 6, and the width of the convex part is 0.5 μm to 1 μm;

[0038] Third, coat photoresist to a thickness exceeding the first metal layer 6, expose, develop, and remove the photoresist in the non-patterned area to open a window above the first metal layer 6 and between the two first metal layers 6;

[0039] Then, evaporate metal, the barrier of the convex part prevents the evaporated metal from depositing on the N-type semiconductor layer 1 below, there is no barrier between the two first metal layers 6 and the N-type semiconductor layer 1 therebetween, the evaporated metal forms a second metal layer 8 and a third metal layer 9, the material is Au / Ge / Ni / Au, the thickness is 1500-3500 angstrom, the second metal layer 8 is deposited on the N-type semiconductor layer 1, and there is a gap between the second metal layer 8 and the two PIN semiconductor layers, the width of the convex part is equal to the corresponding gap width below (note: the preparation method of the semiconductor device belongs to micro-process, a small amount of metal may be deposited below the convex part during the evaporation process, and finally a metal layer with a generally tapered shape of upper narrow and lower wide is formed, therefore, the width is approximately equal, not absolute equal in metrology), and the third metal layer 9 is deposited above the first metal layer 6; after high-temperature annealing, the second metal layer 8 partially penetrates into the N-type semiconductor layer 1, and the thickness of the second metal layer 8 penetrating into the N-type semiconductor layer 1 is 300-8600 angstrom, the second metal layer 8 and the N-type semiconductor layer 1 are in ohmic contact, and the third metal layer 9 and the first metal layer 6 are in ohmic contact;

[0040] Finally, a SiN thin film is deposited on the N-type semiconductor layer 1, the second metal layer 8, the third metal layer 9, the side of the first metal layer 6 and the side of the PIN semiconductor layer as a passivation layer by using a plasma enhanced chemical vapor deposition (PECVD) method, an opening is formed on the third metal layer 9 by etching the passivation layer, and a layer of thick gold is deposited as a fourth metal layer 10 for wire bonding. The passivation layer can be composed of three layers of V0+V1+TP, with a thickness of 4500 angstrom. Due to chemical vapor deposition, the SiN thin film uniformly covers the surface of the semiconductor device antistatic structure, and the convex part or the gap is also uniformly covered. The fourth metal layer 10 is deposited to the surface of the convex passivation layer, which is convenient for subsequent wire bonding connection.

[0041] The preparation method can make the second metal layer 8 very wide, break through the limitation of the minimum line width (1.6 μm) of the traditional photolithography process, greatly reduce the series resistance between the two PIN semiconductor layers, and further improve the antistatic ability of the chip.

[0042] Of course, in order to define the functional area, the outer periphery of the N-type semiconductor layer 1 is formed with an isolation ring 7 by ion implantation, the active functional area is in the isolation ring 7, and the semiconductor device antistatic structure is formed in the functional area.

[0043] The above only describes optional embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0044] It should be further noted that various specific technical features described in the above specific embodiments can be combined in any suitable manner, and in order to avoid unnecessary repetition, the present application will not describe various possible combinations again.

Claims

1. An antistatic structure for a semiconductor device, characterized in that: The semiconductor device comprises an N-type semiconductor layer, two PIN semiconductor layers formed above the N-type semiconductor layer and spaced apart, a first metal layer formed above the PIN semiconductor layers, and a second metal layer formed above the N-type semiconductor layer and between the two PIN semiconductor layers, wherein the PIN semiconductor layer is composed of an InGaP layer, an N-type GaAs layer, an I layer, and a P-type GaAs layer from bottom to top, the first metal layer has a protruding part extending to the middle of the two PIN semiconductor layers beyond the PIN semiconductor layers in the width direction, the second metal layer has a gap between the two PIN semiconductor layers, the width of the protruding part is equal to the corresponding gap width below it; the first metal layer further has a third metal layer above it, the second metal layer and the third metal layer are made of the same material; the spacing distance between the two PIN semiconductor layers is 1.5-4 μm, the width of the protruding part is 0.5-1 μm, and the width of the second metal layer is the difference between the spacing distance and twice the width of the protruding part.

2. The antistatic structure of a semiconductor device according to claim 1, wherein: The thickness of the second metal layer is to 3. The antistatic structure of a semiconductor device according to Claim 1, wherein: The gap has a width of 0.5-1 μm.

4. The antistatic structure of a semiconductor device according to Claim 1, wherein: The second metal layer is in ohmic contact with the N-type semiconductor layer.

5. The antistatic structure of a semiconductor device according to Claim 1, wherein: The second metal layer and the third metal layer have the same thickness.

6. The antistatic structure of a semiconductor device according to Claim 5, wherein: The second metal layer and the third metal layer are Au / Ge / Ni / Au.

7. A method of fabricating an antistatic structure of a semiconductor device, characterized by: A method for manufacturing the antistatic structure of the semiconductor device as claimed in any one of claims 1-6, comprising the following steps: Step one: growing an InGaP layer, an N-type GaAs layer, an I layer, and a P-type GaAs layer on an N-type semiconductor layer, coating photoresist on the surface of the P-type GaAs layer, exposing, developing, and evaporating to form two spaced first metal layers; Step two: wet etching the P-type GaAs layer, the I layer, the N-type GaAs layer, and the InGaP layer below the first metal layer to expose the N-type semiconductor layer, and forming a PIN semiconductor layer with a width smaller than the first metal layer below the two spaced first metal layers, wherein the PIN semiconductor layer is composed of an InGaP layer, an N-type GaAs layer, an I layer, and a P-type GaAs layer from bottom to top; Step three: coating photoresist to a thickness exceeding the first metal layer, exposing, developing, and opening a window above the first metal layer and between the two first metal layers; Step four: evaporating metal to form a second metal layer with a gap between the two PIN semiconductor layers above the N-type semiconductor layer, and a third metal layer above the first metal layer; high-temperature annealing.

8. The method of claim 7, wherein the semiconductor device is a thin film transistor. Step four further comprises: Step five: depositing a passivation layer above the N-type semiconductor layer, the second metal layer, the third metal layer, the side of the first metal layer, and the side of the PIN semiconductor layer, and etching the passivation layer to form a lead opening above the third metal layer.

9. The method of claim 7, wherein the method further comprises: forming a gate oxide layer on the substrate; forming a gate electrode on the gate oxide layer; and forming a gate insulating layer on the gate electrode. The etching liquid for wet etching the P-type GaAs layer, the I layer, and the N-type GaAs layer is H3PO4:H2O2:H2O=1:1:20, and the etching time is 15-20 s for the P-type GaAs layer, 130-140 s for the I layer, and 7-10 s for the N-type GaAs layer; the etching liquid for wet etching the InGaP layer is H3PO4:HCL=1:3, and the etching time is 50-60 s.

Images