Command Drain Using Host Memory Buffering

Abstract

The present disclosure generally relates to efficiently aborting a command using host memory buffer (HMB). The command includes metrics that direct a data storage device to various locations where associated content is located on the data storage device. Once an abort command is received, the content of the host metrics stored in the data storage device RAM is changed to point to the HMB. The data storage device then waits until any already-started transactions over the interface bus associated with the command have completed. Thereafter, a failed completion command is issued to the host device.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 087,737, filed on October 5, 2020, which is incorporated herein by reference. Background of the Invention Field of the Invention

[0004] Embodiments of the present disclosure generally relate to efficiently aborting commands using a host memory buffer (HMB).

[0005] Description of the Related Art

[0006] In a storage system, a host device or a data storage device sometimes aborts outstanding commands. There are several scenarios where a command should be aborted. One scenario is that the host device issues an abort command, whereby the host device specifies the ID of the command to be aborted and the data storage device should act accordingly. A second scenario is that the host device deletes a queued command that the host device has previously issued. The host device can delete the submission or completion queue, and then the data storage device should abort all associated commands before deleting the queue.

[0007] A third scenario is that the data storage device may need to terminate a command due to command timeout. Termination may be due to recovery from a NAND failure, which involves a recovery mechanism for reconstructing data based on parity information, but the reconstruction takes a long time. Termination may also be due to maintenance starvation, which may arise due to extreme fragmentation of physical space. Fragmentation reduces throughput, and if command and maintenance operations are interleaved, fragmentation can lead to command timeouts. Interleaving of commands and maintenance typically occurs during power management periods where no maintenance time is allowed in an aggressive manner or during dense high queue - depth random write workloads. Termination may also be due to a very high queue depth, where if commands within the device are suspended for the reasons above, unprocessed commands may timeout before the data storage device retrieves the commands.

[0008] A fourth scenario is advanced command retry, where the data storage device decides to fail a command while asking the host device to re - queue the command at a later time. Generally speaking, aborting a command is not a simple process. The challenge is when the command has entered the execution phase. Before aborting a command, the data storage device must first terminate all tasks associated with the command and until then send a completion message to the host device. After sending the completion message, the data storage device must not access the relevant host memory buffer (HMB).

[0009] Previously, before an abort command, the data storage device first terminated all tasks associated with the command by scanning for outstanding activities and did not issue a completion message to the host device until then. Alternatively, before the abort command, the data storage device first waited until tasks that had already started were completed and did not issue a completion message to the host device until then.

[0010] Accordingly, there is a need in the art to more effectively handle abort commands. SUMMARY OF THE INVENTION

[0011] The present disclosure generally relates to efficiently aborting commands using a host memory buffer (HMB). The command includes metrics that direct the data storage device to various locations on the data storage device where the relevant content is located. Once an abort command is received, the content of the host metrics stored in the data storage device's RAM is changed to point to the HMB. Then, the data storage device waits until any outstanding transactions over the interface bus associated with the command have been completed. Thereafter, a failed completion command is issued to the host device.

[0012] In one embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive an original command from a host device; begin executing the original command; receive an abort request command to abort the original command, wherein the abort request command is received from the host device or generated by the data storage device; modify one or more metrics of the original command residing in the data storage device; drain a set of data associated with the original command to a host memory buffer (HMB); and return a failed completion message to the host device, wherein the failed completion message is returned to the host device after a data transfer using the original command metrics that has been issued is completed.

[0013] In another embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive an original command from a host device; determine to complete the original command using advanced command retry (ACR); allocate one or more host memory buffers (HMBs) for holding a set of data associated with the original command; return a completion message to the host device, wherein the completion message requests the host device to retry the original command; execute the original command while transferring data to the one or more allocated buffers within the HMB; receive a reissued original command from the host device; and copy data for the reissued original command from the one or more allocated buffers within the HMB.

[0014] In another embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive an abort command request from a host device; allocate a first host memory buffer (HMB) and a second HMB for holding a series of data associated with the abort command request, wherein: the first HMB is configured to drain a series of data associated with the abort command request; and the second HMB is configured to point to a drain buffer; and return a completion message to the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Accordingly, a more particular description of the above-described features of the disclosure, as well as a better understanding of the disclosure, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings only illustrate typical embodiments of the disclosure and should not be considered as limiting its scope, as the disclosure may admit to other equally effective embodiments.

[0016] Figure 1 is a schematic block diagram showing a storage system according to one embodiment, in which the data storage device can be used as a storage device for a host device.

[0017] Figure 2 is a schematic diagram of an abort request.

[0018] Figure 3 is a flowchart showing an abort request process according to one embodiment.

[0019] Figure 4 is a timing diagram of processing an abort request according to one embodiment.

[0020] Figure 5 is a schematic diagram of a PRP list as described in the NVMe standard.

[0021] Figure 6 is a schematic diagram of two host memory buffers (HMBs) for command draining according to one embodiment.

[0022] Figure 7 is a flowchart showing advanced command retry (ACR) according to one embodiment.

[0023] For the sake of clarity, where possible, the same reference numerals have been used to denote the same elements common to the figures. It is contemplated that elements disclosed in one embodiment may be advantageously utilized in other embodiments without further recitation. DETAILED DESCRIPTION

[0024] In the following text, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements (whether or not associated with different embodiments) is contemplated to implement and practice the present disclosure. Additionally, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a given embodiment achieves a particular advantage is not a limitation of the present disclosure. Accordingly, the following aspects, features, embodiments, and advantages are illustrative only and are not to be considered elements or limitations of the appended claims unless expressly recited therein. Similarly, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered an element or limitation of the appended claims unless expressly recited therein.

[0025] The present disclosure generally relates to efficiently aborting commands using a host memory buffer (HMB). The command includes indicators for guiding a data storage device to various locations where relevant content is located on the data storage device. Once an abort command is received, the content of the host indicators stored in the data storage device's RAM is changed to point to the HMB. Then, the data storage device waits until any ongoing transaction over the interface bus associated with the command has been completed. Thereafter, a failed completion command is issued to the host device.

[0026] Figure 1 FIG. 7 is a schematic block diagram showing a storage system 100 according to an embodiment of the disclosure, where the data storage device 106 can be used as a storage device for the host device 104. For example, the host device 104 can utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host DRAM 138, and a portion of the host DRAM 138 is allocated as a host memory buffer (HMB) 140. The HMB 140 can be used by the data storage device 106 as an additional working area or additional storage area for the data storage device 106. In some examples, the HMB 140 may not be accessible to the host device. In some examples, the storage system 100 can include multiple storage devices that can operate as a storage array, such as the data storage device 106. For example, the storage system 100 can include multiple data storage devices 106 that are configured to collectively operate as a redundant array of inexpensive / independent disks (RAID) for the mass storage device of the host device 104.

[0027] The host device 104 can store data and / or retrieve data from one or more storage devices, such as the data storage device 106. As Figure 1As shown, the host device 104 can communicate with the data storage device 106 via the interface 114. The host device 104 can include any of a variety of devices, including computer servers, network-attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, cellular phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from the data storage device, etc.

[0028] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, and a write buffer 116. In some examples, for clarity, the data storage device 106 may include Figure 1 additional components not shown. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed circuit board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5" data storage devices (e.g., HDDs or SSDs), 2.5" data storage devices, 1.8" data storage devices, Peripheral Component Interconnect (PCI), PCI Extended (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled (e.g., directly soldered) to the motherboard of the host device 104.

[0029] The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The electrical connection(s) of the interface 114 (e.g., data bus, control bus, or both) is / are electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108 and allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, as Figure 1 shown, the power supply 111 may receive power from the host device 104 via the interface 114.

[0030] The NVM 110 may include multiple memory devices or memory cells. The NVM 110 may be configured to store and / or retrieve data. For example, the storage cells of the NVM 110 may receive data and a message from the controller 108 indicating to store the data in the storage cell. Similarly, the storage cells of the NVM 110 may receive a message from the controller 108 indicating to retrieve data from the storage cell. In some examples, each of the storage cells may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple storage cells). In some examples, each storage cell may be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0031] In some examples, each storage cell of the NVM 110 may include any type of non-volatile memory device, such as a flash memory device, a Phase Change Memory (PCM) device, a Resistive Random Access Memory (ReRAM) device, a Magnetoresistive Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0032] The NVM 110 may include multiple flash memory devices or storage cells. The NVM flash memory devices may include NAND- or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In the NVM flash memory devices, the flash memory devices may be partitioned into multiple dies, where each die of the multiple dies includes multiple blocks, and the blocks may be further partitioned into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. The rows of the NVM cells may be electrically connected using word lines to define the pages within the multiple pages. The corresponding cells within each page of the multiple pages may be electrically connected to corresponding bit lines. Additionally, the NVM flash memory devices may be 2D or 3D devices and may be single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), or quad-level cells (QLCs). The controller 108 may write data to and read data from the NVM flash memory devices at the page level and erase data from the NVM flash memory devices at the block level.

[0033] The data storage device 106 includes a power supply 111, which may supply power to one or more components of the data storage device 106. When operating in the standard mode, the power supply 111 may supply power to one or more components using the power provided by an external device such as the host device 104. For example, the power supply 111 may supply power to one or more components using the power received from the host device 104 via the interface 114.

[0034] In some examples, the power supply 111 may include one or more power storage components, which are configured to supply power to one or more components when operating in the off mode, such as in the case of stopping receiving power from an external device. In this way, the power supply 111 may serve as an on-board backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc.

[0035] In some examples, the amount of electrical energy that may be stored by one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of electrical energy stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0036] The data storage device 106 also includes a volatile memory 112 that can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile memory devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 can store the cached information in the volatile memory 112 until the cached information is written to the non-volatile memory 110. As Figure 1 shown, the volatile memory 112 can consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0037] The data storage device 106 includes a controller 108 that can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store the data in the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or a write buffer 116 before sending the data to the NVM 110. In some other embodiments, the HMB 140 can be utilized.

[0038] Figure 2 is a schematic diagram of an abort request. Figure 2 Aspects of can be similar to Figure 1 the storage system 100 of. For example, the host 220 can be the host device 104, the controller 202 can be the controller 108, and the NVM 222 can be the NVM 110. During operation of a data storage device (such as Figure 1 the data storage device 106), the host 220 or the controller 202 can abort a pending command, such as a host-generated read command or a host-generated write command. The abort command can be issued by the host 220 or by the controller 202. For example, the abort command can be generated by the main processor 204 of the controller 202, where the main processor 204 sends the abort command to one or more processors 206a - 206n of the controller 202.

[0039] When a termination command is received by one or more of processors 206a - 206n, the one or more processors may terminate all tasks associated with the termination command or wait to terminate all outstanding commands that have not yet started by scanning the outstanding commands, where outstanding commands that are allowed to start are completed before all other outstanding commands are terminated. After terminating the relevant outstanding commands, a completion message is sent to host 220.

[0040] Regarding Figure 2 , the main processor 204 issues a termination command request to one or more of processors 206a - 206n. The one or more processors 206a - 206n utilize the hardware (HW) accelerator 208 to scan each outstanding command and terminate the relevant outstanding commands. After terminating the relevant outstanding commands, the one or more processors issue a completion message to the data path 210, which may be a failure completion message if the termination command is initiated by the data storage device, where the data path 210 transmits the completion message to the host 220.

[0041] In normal operation, the data path 210 may be used to transfer data to and from the NVM 222 by utilizing the direct memory access (DMA) module 212, encode / decode ECC using the error correction code (ECC) engine 218, generate security protocols by the security engine 214, and manage the storage of data by the RAID module 216. The termination command operation may have a high latency before a completion message or a failure completion message is issued to the host 220. Due to the high latency, the buffers and resources of the data storage device may be utilized inefficiently. In addition, certain cases of the termination command operation may have to be performed separately or have separate programs to complete certain cases of the termination command operation.

[0042] Figure 3 is a flowchart showing a termination request process 300 according to one embodiment. At block 302, one or more processors such as Figure 2 one or more of processors 206a - 206n receive a termination request or a termination command, where the one or more processors may be components of a controller (such as Figure 2 controller 202). In some embodiments, the termination request may be generated by a host such as host 220 and transmitted to the controller via a data bus. In other embodiments, the termination request may be generated by a main processor such as Figure 2 main processor 204, where the main processor sends the termination request to the relevant processor among the one or more processors.

[0043] At block 304, the controller modifies the content of the buffer metrics residing in the internal copy of the command. The internal copy of the command may be a command stored in the volatile memory of the data storage device such as DRAM. The buffer metrics may point to the HMB, such asFigure 1 of HMB 140. In some embodiments, the HMB includes two 4KB HMB buffers. The values listed above are not intended to be limiting, but rather to provide examples of possible embodiments. At block 306, the controller determines whether all current transmissions are complete. A current transmission can be a command that has been executed but not yet completed. If the current transmission is not complete, the controller waits for the current transmission to complete. However, if the current transmission is complete at block 306, then at block 308, the controller issues a completion message or a failed completion message to the host device.

[0044] Figure 4 is a timing diagram of processing an abort request according to one embodiment. Figure 4 Aspects of may be similar to Figure 3 those described. At time 1, a host device (such as Figure 1 host device 104) issues data to a data storage device (such as Figure 1 data storage device 106). The command can be a read command, a write command, etc. At some time after the host issues a command to the data storage device due to transmission latency, etc. (such as time 2), a controller (such as Figure 2 controller 202) initiates a data transfer operation.

[0045] During the execution of the data transfer operation, the data storage device receives an abort command at time 3. In one embodiment, the abort command can be generated by the host device. In another embodiment, the abort command can be generated by the data storage device, where the abort command is generated by a controller or a main processor such as Figure 2 main processor 204. At time 4, the data storage device modifies one or more metrics associated with the abort command residing in the data storage device.

[0046] At time 5, the data storage device sends a failed completion message to the host device, which occurs after the data transfer operation at time 2. At time 6, the data transfer operation has stopped, and the data storage device flushes a set of data associated with the abort request command to the HMB, such as Figure 1 HMB 140. In some embodiments, the flushing of the set of data begins before the failed completion message is issued to the host. In other embodiments, the failed completion message is issued before aborting the data transfer operation to the HMB.

[0047] Figure 5 is a schematic diagram of a PRP list described in the NVMe standard. Command 502 includes a plurality of Physical Region Page (PRP) metrics, such as a first PRP1 504 and a second PRP2 506, where each PRP metric points to a buffer in a plurality of buffers. The plurality of buffers can be the HMB (such as Figure 1a portion of the HMB 140). Additionally, in Figure 5 each page, page 0 518, page 1 520, page 2 522, and page 3 524 represent different buffers. In one example, each in the buffer may have a size aligned with the size of a command or virtual command, such as approximately 4K. The virtual command may be a command generated by the data storage device to set parameters of the size of the buffer in the HMB. The first PRP1 504 and the second PRP2 506 include an offset "xx", where the offset is an index offset from a location such as a header. Each PRP index may be an index pointing to a buffer or an index pointing to a list of entries.

[0048] For example, the first PRP1 504 includes a first index 526 pointing to the first page 0 518. The second PRP2 506 includes a second index 528 pointing to the first entry PRP entry 0 510 of the PRP list 508. The PRP list 508 has an offset of 0 such that the PRP list 508 is aligned with the size of the buffer. For example, the first PRP entry 0 510 includes a third index 530 pointing to the second page 1 520, the second PRP entry 1 512 includes a fourth index 532 pointing to the third page 2 522, and the third PRP entry 2 514 includes a fifth index 534 pointing to the fourth page 3 524. The last entry of the PRP list 508 may include an index pointing to a subsequent or new PRP list.

[0049] Figure 6 is a schematic diagram of two host memory buffers (HMBs) for command draining according to one embodiment. The NVMe command 602 is a stored copy of a command received by the controller, where the NVMe command 602 may be stored in the volatile memory or non-volatile memory of the data storage device. The first PRP1 604a may be Figure 5 the first PRP 504 of Figure 5 and the second PRP2 604b may be

[0050] the second PRP 506 of

[0051] During the initialization phase, the second HMB buffer 606b can be initialized by a controller (such as Figure 1 controller 202) of a data storage device (such as Figure 2 data storage device 106). The initialization phase can be during a wake-up operation of the data storage device, such as when power is supplied to the data storage device. Each index in the plurality of buffers 608a - 608n of the second HMB buffer 606b points to the first HMB buffer 606a. Additionally, the last index 608n does not point to a subsequent or next buffer list, but rather the last index 608n points to the first buffer 608a of the same HMB buffer. By pointing each index of the second HMB buffer 606b to the first HMB buffer 606a, pointing the index of the last buffer 608n of the second HMB buffer 606b to the first buffer 608a, and pointing the index of the first PRP1 to the first HMB buffer 606a, the relevant data associated with a read operation or a write operation will be flushed to the first HMB buffer 606a when an abort command is received.

[0052] Figure 7 is a flowchart 700 showing Advanced Command Retry (ACR) according to one embodiment. When the data storage device receives a command including an ACR request, one or more HMBs can be allocated to hold the set of data for the command. When a failed command has an ACR, the host (such as Figure 1 host device 104) is notified of the failed command, and the host can re-queue the failed command in the command buffer after a delay (such as about 10 seconds). The delay time can be announced by the data storage device such as Figure 1 data storage device 104 via an identified controller command.

[0053] Rather than re-queuing the data associated with the failed command in a host buffer (such as Figure 1 host DRAM 138), the data storage device queues the data associated with the failed command in a host HMB (such as Figure 1 host HMB 140). When an ACR request for a command is received, flowchart 700 is started at block 702. At block 704, an HMB buffer is allocated. The HMB buffer includes a first HMB buffer (such as Figure 6 first HMB buffer 606a) and a second HMB buffer (such as Figure 6 second HMB buffer 606b), where the first HMB buffer is a flush buffer and the second HMB buffer is a list of buffer indices pointing to the first HMB buffer.

[0054] At block 706, the internal versions of the metrics (i.e., PRP1 and PRP2) are modified to point to the allocated HMB buffers. For example, the PRP1 metric may point to the first HMB buffer and the PRP2 metric may point to the second HMB buffer. At block 708, the controller determines whether all current transmissions of commands that have started with the associated target host buffer are complete. If the current transmissions are not complete, the controller waits for the commands to complete.

[0055] At block 710, after all current commands are complete, the controller issues a failure completion message to the host, the failure completion message having an ACR indication for the failed command. At block 712, one or more HMBs are accessed such that the data of the failed command is transferred to a location in one or more HMBs. An indication of the series of transmissions is issued on the interface of the host device, where the series of transmissions are stored in one or more HMBs. When the HMB buffer is accessed, the data associated with the failed command is transferred to the first HMB buffer (i.e., the HMB buffer is drained). At block 714, the host device re-queues the command to the data storage device, where the re-queued command is the original command that has failed. At block 716, the data associated with the re-queued command is copied from the associated location in the HMB (or in some embodiments, one or more HMBs) to the host buffer. The re-queued command is executed by the controller using the data stored in the host buffer.

[0056] By changing the content of the command metrics, aborted commands can be processed more efficiently, thereby improving the performance of the storage device. Aborting commands in a simple way without any latency increase improves efficiency compared to the complex high-latency streams that currently exist. Additionally, using the HMB as a cache buffer for commands that fail with an ACR will speed up the processing.

[0057] In one embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a raw command from a host device; begin execution of the raw command; receive an abort request command to abort the raw command, wherein the abort request command is received from the host device or generated by the data storage device; modify one or more metrics of the raw command residing in the data storage device; drain a set of data associated with the raw command to a host memory buffer (HMB); and return a failure completion message to the host device, wherein the failure completion message is returned to the host device after completion of a data transfer already issued using the raw command metrics. The controller is further configured to continue processing a data transfer associated with the raw command after receiving the abort request. Processing of the data transfer continues after modification of the one or more metrics is complete. Draining the set of data occurs: after returning the failure completion message, before returning the failure completion message begins, or a combination thereof. The failure completion message is delivered while a data transfer associated with the raw command is still being processed, wherein the data transfer occurring after delivery of the failure completion message utilizes the modified one or more metrics. Draining a set of data includes pointing each metric to a drain buffer. The last metric points to the same buffer list in which the last metric resides.

[0058] In another embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a raw command from a host device; determine to complete the raw command using an Advanced Command Retry (ACR); allocate one or more Host Memory Buffers (HMBs) to hold a set of data associated with the raw command; return a completion message to the host device, wherein the completion message requests the host device to retry the raw command; execute the raw command while transferring data to the one or more allocated buffers within the HMB; receive the reissued raw command from the host device; and copy data for the reissued raw command from the one or more allocated buffers within the HMB. When the controller returns the completion message to the host device: a representation of the data is issued on the interface of the host device; and the data is stored in the HMB, where the HMB is not used for draining data, and where the HMB includes a plurality of buffers sized to hold the data to ensure that the data storage device can copy the data from the HMB to the host device when receiving a command to retrieve the data from the host device. The controller is further configured to receive a reissued command of the raw command from the host device. The controller is further configured to copy data from one or more HMBs. The copying includes copying a series of transfers from one or more HMBs to a host buffer for the reissued command. The controller is configured to wait for completion of the current transfer associated with the raw command that has started before returning the completion message, wherein after the controller returns the completion message, the data storage device does not access the raw buffer with the raw command, and wherein after the controller returns the completion message, the data storage device can access one or more HMBs. During the wait and before returning the completion message, the data storage device can access the raw buffer and one or more HMBs in parallel.

[0059] In another embodiment, a data storage device includes: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive an abort command request from a host device; allocate a first Host Memory Buffer (HMB) and a second HMB to hold a series of data associated with the abort command request, wherein: the first HMB is configured to drain a series of data associated with the abort command request; and the second HMB is configured to point to a drain buffer; and return a completion message to the host device. The first HMB is a drain buffer. Data associated with the abort command is drained to the drain buffer during read and write operations. The second HMB is configured to contain a buffer index list. All but the last index in the buffer index list point to the drain buffer. The last index in the buffer index list points to a different index in the buffer index list.

[0060] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be envisioned without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: one or more memory devices; and a controller coupled to the one or more memory devices, wherein the controller is configured to: receive a raw command from a host device; determine to complete the raw command by retrying with an advanced command, i.e., ACR; allocate one or more buffers within one or more host memory buffers, i.e., one or more HMBs, for holding a set of data associated with the raw command; return to the host device a completion message with an ACR indication, wherein the completion message requests the host device to retry the raw command; execute the raw command while transferring data to the one or more allocated buffers within the HMB; receive a reissued raw command from the host device; and copy data for the reissued raw command from the one or more allocated buffers within the HMB.

2. The data storage device according to claim 1, wherein when the controller returns the completion message to the host device: issue a representation of the data on an interface of the host device; and the data is stored in the one or more HMBs, wherein the one or more HMBs are not used for discharging data, and wherein the one or more HMBs include a plurality of buffers sized to hold the data to ensure that the data storage device can copy the data from the one or more HMBs to the host device when receiving a command to retrieve the data from the host device.

3. The data storage device according to claim 1, wherein the controller is further configured to: receive a reissued command of the raw command from the host device.

4. The data storage device according to claim 3, wherein the controller is further configured to copy data from the one or more HMBs.

5. The data storage device according to claim 4, wherein the copying includes copying the data from the one or more HMBs to a host buffer for the reissued command.

6. The data storage device according to claim 1, wherein the controller is configured to wait for completion of a current transfer associated with the raw command that has started before returning the completion message, wherein after the controller returns the completion message, the data storage device does not access a raw buffer having the raw command, and wherein after the controller returns the completion message, the data storage device can access the one or more HMBs.

7. The data storage device according to claim 6, wherein during the waiting period and before returning the completion message, the data storage device can access the raw buffer and the one or more HMBs in parallel.

Images