Passing programmable atomic operators to a memory controller

Abstract

Apparatuses and techniques are described herein for passing programmable atomic operators to a memory controller. A memory controller can receive a memory request and extract from the memory request a command indicator that indicates a programmable atomic operator (PAO) command. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.

Description

[0001] Statement regarding government support

[0002] This invention was developed with the support of the U.S. government under Agreement No. HR00111890003 granted by the Defense Advanced Research Projects Agency (DARPA). The U.S. government holds certain rights to this invention. Technical Field

[0003] This application relates to techniques for passing programmable atomic operators to a memory controller. Background Technology

[0004] Chiplets are an emerging technology for integrating various processing functionalities. Generally, a chiplet system consists of discrete modules (each a "chiplet") integrated on an interposer and, in many instances, interconnected via one or more established networks as needed to provide the desired functionality to the system. The interposer and the contained chiplets may be packaged together to facilitate interconnection with other components of a larger system. Each chiplet may contain one or more individual integrated circuits (ICs) or "chips," potentially combined with discrete circuit components and coupled together to a corresponding substrate to facilitate attachment to the interposer. Most or all chiplets in the system will be individually configured to communicate via one or more established networks.

[0005] Chiplets, as individual modules of a system, differ in configuration from systems implemented on a single chip. They contain different device blocks (e.g., intellectual property (IP) blocks) on a substrate (e.g., a single die), such as a system-on-a-chip (SoC) or multiple discrete packaged devices integrated on a printed circuit board (PCB). Generally, chiplets offer better performance (e.g., lower power consumption, reduced latency) than discrete packaged devices, and offer greater manufacturing benefits than a single die chip. These manufacturing benefits may include higher yields or reduced development costs and time.

[0006] For example, a chiplet system may include one or more application (or processor) chiplets and one or more support chiplets. Here, the distinction between application and support chiplets is merely a reference to possible design scenarios for chiplet systems. Thus, for example, a synthetic vision chiplet system may include (by way of example only) application chiplets for generating synthetic vision output and support chiplets, such as memory controller chiplets, sensor interface chiplets, or communication chiplets. In typical use cases, synthetic vision designers may design the application chiplets and obtain the support chiplets from other sources. Therefore, design costs (e.g., in terms of time or complexity) are reduced because the design and manufacturing of functionality embodied in the support chiplets are avoided. Chipslets also support the tight integration of IP blocks that might otherwise be difficult, such as IP blocks manufactured using different processing technologies or with different feature sizes (or utilizing different contact technologies or spacing). Therefore, multiple ICs or IC assemblies with different physical, electrical, or communication characteristics can be modularly assembled to provide assemblies that offer the desired functionality. Chiplet systems also facilitate adaptation to the needs of different larger systems into which the chiplet system will be incorporated. In practice, ICs or other assemblies can be optimized for power, speed, or heat generation for specific functions—as can occur with sensors—making them easier to integrate with other devices compared to trying to do so on a single die. Furthermore, by reducing the overall size of the die, chiplets tend to have higher yields than more complex single-die devices. Summary of the Invention

[0007] One aspect of this application relates to an apparatus comprising: a network interface that can be coupled to a chiplet in a host or chiplet system and configured to receive a memory request; a packet decoder configured to: retrieve a command indicator from the memory request, the command indicator indicating a programmable atomic operator command; and, in response to the command indicator indicating the programmable atomic operator command, retrieve a programmable atomic operator index from the memory request; and a programmable atomic unit configured to invoke the programmable atomic operator based on the programmable atomic operator index.

[0008] Another aspect of this application relates to a method comprising: obtaining a memory request at a memory controller; retrieving a command indicator from the memory request, the command indicator indicating a programmable atomic operator command; retrieving a programmable atomic operator index from the request in response to the command indicator indicating the programmable atomic operator command; and invoking the programmable atomic operator based on the programmable atomic operator index.

[0009] Another aspect of this application relates to a machine-readable medium containing instructions that, when executed by a circuit system of a memory controller, cause the memory controller to perform operations including: obtaining a memory request; retrieving a command indicator from the memory request, the command indicator indicating a programmable atomic operator command; retrieving a programmable atomic operator index from the request in response to the command indicator indicating the programmable atomic operator command; and invoking the programmable atomic operator based on the programmable atomic operator index.

[0010] Another aspect of this application relates to a system comprising: means for obtaining a memory request; means for retrieving a command indicator from the memory request, the command indicator indicating a programmable atomic operator command; means for retrieving a programmable atomic operator index from the request in response to the command indicator indicating the programmable atomic operator command; and means for invoking the programmable atomic operator based on the programmable atomic operator index. Attached Figure Description

[0011] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are merely for explanation and understanding.

[0012] Figure 1A and 1B An example of a chiplet system according to an embodiment is described.

[0013] Figure 2 This describes the components of an example of a memory controller chiplet according to an embodiment.

[0014] Figure 3 This describes the components of an example of a memory controller chiplet according to an embodiment.

[0015] Figure 4 This describes the components in an example of a programmable atomic unit (PAU) according to an embodiment.

[0016] Figure 5 This describes the chiplet protocol interface request group according to the embodiment.

[0017] Figure 6 This describes the chiplet protocol interface response packets according to the embodiment.

[0018] Figure 7 This is a flowchart illustrating an example of a method for passing programmable atomic operators to a memory controller, according to an embodiment.

[0019] Figure 8This is a block diagram of an example of an embodiment of the present disclosure that can utilize, or operate in, or through the machine. Detailed Implementation

[0020] Figure 1, described below, provides an example of a chiplet system and components operating therein. The illustrated chiplet system includes a memory controller. The chiplet system includes a packet-based network for communication between chiplets. The memory controller includes a programmable atomic unit (PAU) with a processor that executes a custom program (programmable atomic operator) in response to a memory request for a programmable atomic operator (PAO). Additional details about the PAU are described below regarding... Figure 2 and 4 describe.

[0021] Supporting a PAO involves the ability to transmit the operation to be performed and possible arguments from the requesting process or chiplet to the PAU. Once the operation is complete, the requesting process is signaled with any potential return value to indicate completion. In conventional processor systems, memory access is typically supported by read and write operations over dedicated memory connections (e.g., buses, interconnects, etc.). Interconnects are often timing- and content-critical, which can hinder efforts to implement functionalities embodied in PAUs, for example.

[0022] To address the limitations of traditional architectures, this disclosure describes a packet-based request and response technique for specifying a PAO and returning a response to the request. Specifically, a PAO may be initiated from a request process (e.g., on an application chiplet) and routed as a packet to a memory controller. The memory controller decodes the packet, identifies the PAO from among several PAOs supported by a PAU, and invokes the PAO. When the PAO completes, a packet containing a response (e.g., a return code, result data, etc.) is created. The response is then transmitted from the chiplet network to the request process.

[0023] Request and response packets are typically formed like other memory request and response packets in chiplet systems. However, request packets contain additional fields (such as extended headers) to identify which of several PAOs to invoke based on the request. Flexible and efficient PAO invocation can be achieved by using the packet-based PAO invocation method described herein. Additional details and examples are provided below.

[0024] Figure 1A and 1B An example of a chiplet system 110 according to an embodiment is described. Figure 1AThis is an illustration of a chiplet system 110 mounted on a peripheral board 105, which can be connected to a larger computer system via, for example, a peripheral component interconnect (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chips (application chiplet 125, host interface chiplet 135, memory controller chiplet 140, and memory device chiplet 150). As will be apparent from the following discussion, other systems may include numerous additional chipsets to provide additional functionality. The package of the chiplet system 110 is described as having a cap or cover 165, but other packaging technologies and structures used for chiplet systems may be used. Figure 1B This is a block diagram for the purpose of clearly labeling the components in a chiplet system.

[0025] Application chip 125 is described as including a network on-chip (NOC) 130 for supporting inter-chip communication within chiplet network 155. In an exemplary embodiment, NOC 130 may be included on application chiplet 125. In an example, NOC 130 may be defined in response to selected supporting chiplets (e.g., chiplets 135, 140, and 150), allowing designers to select an appropriate number of chiplet network connections or switches for NOC 130. In an example, NOC 130 may be located on a single chiplet or even within intermediary layer 120. In the example discussed herein, NOC 130 implements a chiplet protocol interface (CPI) network.

[0026] CPI is a packet-based network that supports virtual channels for flexible and high-speed interaction between chiplets. CPI bridges the chiplet-internal network to chiplet network 155. For example, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communication. However, the AXI specification covers a wide range of physical design options, such as the number of physical channels, signal timing, and power. Within a single chip, these options are typically selected to meet design goals, such as power consumption and speed. However, to achieve flexibility in chiplet systems, adapters (such as CPI) are used to intersect between various AXI design options that can be implemented in individual chiplets. By enabling physical-to-virtual channel mapping and encapsulating time-based signaling using packetization protocols, CPI bridges the chiplet-internal network across chiplet network 155.

[0027] CPI can use various physical layers to transmit packets. A physical layer may contain simple conductive connections, or it may contain drivers for increasing voltage, or otherwise facilitate signal transmission over longer distances. An example of such a physical layer may include an Advanced Interface Bus (AIB), which in various instances may be implemented in intermediate layer 120. The AIB uses source-synchronous data transfer and forwarding clocks to transmit and receive data. Packets are transmitted across the AIB at Single Data Rate (SDR) or Double Data Rate (DDR) relative to the transmitted clock. Individual channel widths are supported by the AIB. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60, ...), and for DDR mode it is a multiple of 40 bits (40, 80, 120, ...). The AIB channel width includes both transmitted and received signals. Channels can be configured to have a symmetrical number of transmit (TX) and receive (RX) inputs / outputs (I / O), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). Channels can be used as AIB masters or slaves, depending on which chiplet provides the master clock. AIB I / O cells support three timing modes: asynchronous (i.e., non-timing), SDR, and DDR. In various instances, the non-timing mode is used for the clock and some control signals. SDR mode can use dedicated SDR-only I / O cells or dual-use SDR / DDR I / O cells.

[0028] In this example, CPI packet protocols (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O cells within an AIB channel. CPI streaming protocols allow for more flexible use of AIB I / O cells. In this example, AIB channels for streaming mode can be configured with all TX, all RX, or half TX and half RX. CPI packet protocols can use AIB channels in SDR or DDR operating modes. In this example, for SDR mode, AIB channels are configured in increments of 80 I / O cells (i.e., 40 TX and 40 RX), while for DDR mode, it is 40 I / O cells. CPI streaming protocols can use AIB channels in SDR or DDR operating modes. Here, in this example, for both SDR and DDR modes, AIB channels are configured in increments of 40 I / O cells. In this example, each AIB channel is assigned a unique interface identifier. The identifier is used during CPI reset and initialization to identify paired AIB channels across neighboring chiplets. In this example, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. The 20-bit interface identifier is transmitted in both directions across the AIB interface using bits 32 to 51 of the shift register.

[0029] AIB defines a stacked set of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels plus auxiliary channels. The auxiliary channels contain signals used for AIB initialization. All AIB channels within a column (except for the auxiliary channels) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and also have the same number of data I / O signals). In this example, AIB channels are numbered sequentially, starting with the one adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0030] Generally, the CPI interface on an individual chiplet may include serialization-deserialization (SERDES) hardware. SERDES interconnects work well for situations where high-speed signaling with low signal counts is desired. However, SERDES can lead to additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or power consumption is a primary concern for ultra-short-reach chiplet-to-chiplet interconnects, parallel interfaces with clock rates that allow data transmission with minimal latency can be utilized. CPIs contain elements that minimize both latency and power consumption in these ultra-short-reach chiplet interconnects.

[0031] For flow control, CPI employs a credit-based technique. For example, the sender, such as the memory controller chip 140, provides credits indicating available buffers for the receiving side of chip 125. In this example, the CPI receiver contains buffers for each virtual channel within a given transmission time unit. Therefore, if the CPI receiver supports five messages and a single virtual channel in time, the receiver has five buffers arranged in five rows (one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

[0032] As the sender transmits to the receiver, it decrements its available credits based on the transmission. Once all of the receiver's credits have been used up, the sender stops sending packets to the receiver. This ensures that the receiver always has a buffer available for storing transmissions.

[0033] As the receiver processes the received packets and releases the buffer, it passes the available buffer space back to the sender. This credit return can then be used by the sender to allow the transmission of additional information.

[0034] It also describes a chiplet mesh network 160 using direct chiplet-to-chiplet technology without the need for NOC 130. The chiplet mesh network 160 can be implemented using CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 160 typically enables a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chips in the pipeline only interface with themselves.

[0035] Additionally, dedicated device interfaces, such as one or more industry-standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR6), can also be used to interconnect chiplets. Connections from a chiplet system or individual chiplets to external devices (e.g., larger systems) can be made via desired interfaces (e.g., PCIe interfaces). In an example, an external interface may be implemented via a host interface chiplet 135, which, in the depicted example, provides a PCIe interface external to the chiplet system 110. Such dedicated interfaces 145 are typically adopted when industry practice or standards have converged on such interfaces. The illustrated example of connecting a memory controller chiplet 140 to a Double Data Rate (DDR) interface 145 of a dynamic random access memory (DRAM) memory device 150 is precisely such an industry practice.

[0036] Among the various possible supporting chiplets, the memory controller chiplet 140 is likely to be present in the chiplet system 110 due to its ubiquitous use in computer processing for storage and the complex, advanced technologies employed in memory devices. Therefore, using the memory device chiplet 150 and memory controller chiplet 140, both manufactured by others, allows chiplet system designers to utilize robust products from sophisticated manufacturers. Generally, the memory controller chiplet 140 provides a memory device-specific interface for reading, writing, or erasing data. Typically, the memory controller chiplet 140 can provide additional features such as error detection, error correction, maintenance operations, or atomic operator execution. For some types of memory, maintenance operations tend to be memory device 150-specific, such as the collection of discarded items in NAND flash or storage-class memory, or temperature regulation (e.g., cross-temperature management) in NAND flash memory. In instances, maintenance operations may involve logic-to-physical (L2P) mapping or management to provide an indirect level between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled by the host processor of the memory controller at some times, and by the DRAM memory device or by logic associated with one or more DRAM devices, such as an interface chip (in this example, a buffer).

[0037] Atomic operators are data manipulations that can be performed, for example, by memory controller chiplet 140. In other chiplet systems, atomic operators can be performed by other chipsets. For example, the atomic operator "increment" can be specified in a command by application chiplet 125, the command including a memory address and a possible increment value. Upon receiving the command, memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, memory controller chiplet 140 provides a success indication to application chiplet 125. Atomic operators avoid data transfer across chiplet network 160, resulting in lower latency execution of such commands.

[0038] Atomic operators can be classified as built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a finite set of operations that are immutably implemented in hardware. Programmable atoms are applets that can be executed on programmable atomic units (PAUs) (e.g., custom atomic units (CAUs)) of the memory controller chiplet 140. Figure 1 illustrates an example of a memory controller chiplet with a PAU.

[0039] The memory device chiplet 150 may be or may contain any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include (but are not limited to) random access memory (RAM)—such as DRAM, synchronous DRAM (SDRAM), graphics double data rate type 6 SDRAM (GDDR6 SDRAM), etc. Examples of non-volatile memory devices include (but are not limited to) NAND flash memory, memory-class memory (such as phase-change memory or memristor-based technology), ferroelectric RAM (FeRAM), etc. The illustrated example includes memory device 150 as a chiplet; however, memory device 150 may reside elsewhere, such as in a different package on peripheral board 105. Multiple memory device chipslets may be provided for many applications. In the example, each of these memory device chipslets may implement one or more memory technologies. In the example, the memory chiplet may contain multiple stacked memory dies of different technologies, such as one or more static random access memory (SRAM) devices stacked with or otherwise communicating with one or more dynamic random access memory (DRAM) devices. The memory controller 140 can also be used to coordinate the operation between multiple memory chips in the chiplet system 110; for example, utilizing one or more memory chips in one or more cache memory levels, and using one or more additional memory chips as main memory. The chiplet system 110 may also include multiple memory controllers 140, which can be used to provide memory control functionality for individual processors, sensors, networks, etc. For example, the chiplet architecture of the chiplet system 110 offers the advantage of allowing adaptation to different memory storage technologies and different memory interfaces through upgraded chiplet configurations without redesigning the remainder of the system architecture.

[0040] Figure 2The components of an example of a memory controller chiplet 205 according to an embodiment are described below. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with off-die memory 275), a network communication interface 225 (e.g., for interfacing with a chiplet network 285 and communicating with other chiplets), and a set of atom and merging units 250. Members of this set may include, for example, a write merging unit 255, a memory dangerous unit 260, a built-in atom unit 265, or a PAU 270. The components are described logically, not necessarily as they will be implemented. For example, the built-in atom unit 265 may include different means along the path to the off-die memory. For example, the built-in atom unit 265 may be in an interface means / buffer on the memory chiplet, as discussed above. In contrast, the programmable atom unit 270 may be implemented in a separate processor on the memory controller chiplet 205 (but in various instances, it may be implemented elsewhere, such as on the memory chiplet itself).

[0041] The off-die memory controller 220 is directly coupled to the off-die memory 275 (e.g., via a bus or other communication connection) to provide write operations to and read operations from one or more off-die memories (e.g., off-die memory 275 and off-die memory 280). In the depicted example, the off-die memory controller 220 is also coupled for outputs to the atom and merge unit 250 and for inputs to the cache controller 215 (e.g., a memory-side cache controller).

[0042] In the instance configuration, the cache controller 215 is directly coupled to the cache 210 and can be coupled to the network communication interface 225 for input (e.g., incoming read or write requests) and can be coupled to the off-chip memory controller 220 for output.

[0043] Network communication interface 225 includes packet decoder 230, network input queue 235, packet encoder 240, and network output queue 245 to support packet-based chiplet network 285, such as CPI. Chiplet network 285 can provide packet routing between and within processors, memory controllers, mixed-thread processors, configurable processing circuitry, or communication interfaces. In such packet-based communication systems, each packet typically contains destination and source addressing, as well as any data payload or instructions. In examples, chiplet network 285 may be implemented as a collection of crossbar switches with a folded Clos configuration or a mesh network providing additional connectivity depending on said configuration.

[0044] In various instances, the chiplet network 285 may be part of an asynchronous switching configuration. Here, data packets can be routed along any of the various paths, such that the arrival of any selected data packet at its addressed destination may depend on the routing occurring at any of a plurality of different times. Alternatively, the chiplet network 285 may be at least partially implemented as a synchronous communication network, such as a synchronous mesh communication network. Both communication network configurations are considered for use in embodiments according to this disclosure.

[0045] The memory controller chip 205 can receive packets having, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or the cache controller 215 reads data from the specified physical address (which may be in off-die memory 275 or cache 210) and assembles a response packet containing the requested data to the source address. Similarly, the memory controller chip 205 can receive packets having a source address, a write request, and a physical address. In response, the memory controller chip 205 writes data to the specified physical address (which may be in cache 210 or off-die memory 275 or 280) and assembles a response packet containing confirmation that the data has been stored in memory to the source address.

[0046] Therefore, the memory controller chiplet 205 can receive read and write requests via chiplet network 285 and (if possible) process the requests using cache controller 215, which interfaces with cache 210. If the request cannot be processed by cache controller 215, then off-chip memory controller 220 processes the request by communicating with off-chip memory 275 or 280, atom and merging unit 250, or both. As noted above, one or more cache levels may also be implemented in off-chip memory 275 or 280; and in some such instances, they may be directly accessed by cache controller 215. Data read by off-chip memory controller 220 may be cached by cache controller 215 in cache 210 for later use.

[0047] Atom and merging unit 250 is coupled to receive the output (as input) of off-die memory controller 220 and provides the output to cache 210, network communication interface 225, or directly to chiplet network 285. Each of memory hazard unit 260, write merging unit 255, and built-in (e.g., predetermined) atom unit 265 may be implemented as a state machine with another combinational logic system (e.g., adder, shifter, comparator, AND gate, OR gate, XOR gate, or any suitable combination thereof) or other logic system. These components may also include one or more registers or buffers for storing operands or other data. PAU 270 may be implemented as one or more processor cores or control circuitry systems and, together with other combinational logic systems or other logic systems, as various state machines, and may also include one or more registers, buffers, or memories for storing addresses, executable instructions, operands, and other data, or may be implemented as a processor.

[0048] Write merging unit 255 receives read data and request data, and merges the request data and read data to create a single unit having the read data and source address to be used in response or return data packets. Write merging unit 255 provides the merged data to the write port of cache 210 (or equivalently, to cache controller 215 for writing to cache 210). Optionally, write merging unit 255 provides the merged data to network communication interface 225 to encode and prepare response or return data packets for transmission on chiplet network 285.

[0049] When requested data is used for a built-in atomic operator, the built-in atomic unit 265 receives the request and reads the data from the write merging unit 255 or directly from the off-chip memory controller 220. The atomic operator is executed, and the resulting data is written to cache 210 or provided to network communication interface 225 to encode and prepare response or return data packets for transmission on chiplet network 285 using the write merging unit 255.

[0050] Built-in atomic unit 265 handles predefined atomic operators, such as fetch and increment or compare and swap. In examples, these operations perform simple read-modify-write operations on a single memory location of 32 bytes or less. Atomic memory operations are initiated from request packets transmitted via chiplet network 285. The request packet has a physical address, atomic operator type, operand size, and optionally up to 32 bytes of data. The atomic operators perform read-modify-write operations on cache lines of cache 210, filling the cache if necessary. The atomic operator response can be a simple complete response or a response with up to 32 bytes of data. Example atomic memory operators include fetch and AND, fetch and OR, fetch and XOR, fetch and add, fetch and subtract, fetch and increment, fetch and decrement, fetch and minimize, fetch and maximize, fetch and swap, and compare and swap. In various example embodiments, 32-bit and 64-bit operations and operations on 16 or 32 bytes of data are supported. The methods disclosed in this paper are also compatible with hardware that supports larger or smaller operations and more or less data.

[0051] Built-in atomic operators may also involve requests for "standard" atomic operators on the requested data, such as relatively simple single circular integer atoms—e.g., fetch and increment or compare and swap—which will occur with the same amount of processing as regular memory read or write operations that do not involve atomic operators. For these operations, cache controller 215 typically preserves cache lines in cache 210 by setting a danger bit (in hardware) so that the cache line cannot be read by another process during its positive transition. Data is obtained from off-chip memory 275 or cache 210 and provided to built-in atomic unit 265 to execute the requested atomic operator. After the atomic operator, in addition to providing the obtained data to packet encoder 240 to encode outgoing data packets for transmission on chiplet network 285, built-in atomic unit 265 provides the obtained data to write merging unit 255, which also writes the obtained data to cache 210. After the obtained data is written to cache 210, any corresponding danger bits that were set are cleared by memory danger unit 260.

[0052] The PAU 270 implements programmable atomic operators (also known as "custom atomic transactions" or "custom atomic operators") with high performance (high throughput and low latency), comparable to built-in atomic operators. Instead of performing multiple memory accesses, in response to an atomic operator request specifying a programmable atomic operator and a memory address, the circuitry in the memory controller chip 205 transmits the atomic operator request to the PAU 270 and sets a danger bit in a memory danger register corresponding to the memory row used in the atomic operator, ensuring that no other operation (read, write, or atomic) is performed on that memory row. The danger bit is then cleared after the atomic operator completes. Providing an additional direct data path for the PAU 270 to execute programmable atomic operators allows for additional write operations without being limited by the bandwidth of the communication network or increasing network congestion.

[0053] The PAU 270 includes a multi-threaded processor, such as (for example) a RISC-VIS-based multi-threaded processor with one or more processor cores and further having an extended instruction set for executing programmable atomic operators. When equipped with an extended instruction set for executing programmable atomic operators, the PAU 270 can be embodied as one or more hybrid-threaded processors. In some example implementations, the PAU 270 provides barrel-style cyclic transient thread switching to maintain a high instruction-per-clock rate.

[0054] Programmable atomic operators, which can be executed by PAU 270, relate to requests for programmable atomic operators on requested data. Users can prepare programming code to provide such programmable atomic operators. For example, programmable atomic operators can be relatively simple multi-loop operations, such as floating-point addition, or relatively complex multi-instruction operations, such as Bloom filter insertion. Programmable atomic operators can be the same as or different from predetermined atomic operators, as long as they are user-defined rather than system vendor-defined. For these operations, cache controller 215 can preserve cache lines in cache 210 by setting a danger bit (in hardware) so that the cache line cannot be read by another process during its positive transition. Data is obtained from cache 210 or off-chip memory 275 or 280 and provided to PAU 270 to execute the requested programmable atomic operator. After the atomic operator, PAU 270 provides the resulting data to network communication interface 225 to directly encode outgoing data packets containing the resulting data for transmission over chiplet network 285. Additionally, PAU 270 provides the obtained data to cache controller 215, which also writes the obtained data to cache 210. After the obtained data is written to cache 210, any corresponding dangerous bits that were set will be cleared by cache control circuitry 215.

[0055] In the selected example, the approach employed for programmable atomic operators will provide multiple generic custom atomic request types, which can be sent from an originating source, such as a processor or other system component, to the memory controller chiplet 205 via chiplet network 285. Cache controller 215 or off-die memory controller 220 will identify the request as a custom atom and forward it to PAU 270. In a representative embodiment, PAU 270: (1) is a programmable processing element capable of efficiently executing user-defined atomic operators; (2) can perform load and store to memory, arithmetic and logical operations, and control flow decisions; and (3) facilitates interaction with such controllers 215, 220 to atomically execute user-defined operations using a RISC-V ISA with a new set of dedicated instructions. In a desired example, the RISC-V ISA contains a complete set of instructions supporting high-level language operators and data types. The PAU 270 can utilize the RISC-V ISA, but when included within the memory controller chiplet 205, it will typically support a more limited set of instructions and a limited register file size to reduce the die size of the cell.

[0056] To implement flexible and efficient programmable atomic operator requests, network interface 225 is configured to receive (e.g., receive) memory requests. In this example, memory requests are presented in CPI packets, as described below regarding... Figure 5The CPI memory request packet 500 is described. In the context of Figures 1 and 2, a CPI memory request packet is created from a memory request packet originating from, for example, application chip 125 (or from a process operating on application chip 125) or host interface chip 135 and transmitted to memory controller 205 (e.g., memory controller 140) via NOC 285 (e.g., NOC 130).

[0057] Other circuitry systems, including the block decoder 230, cache controller 215, off-chip memory controller, PAU 270, or memory controller 205, are configured to retrieve a command indicator from a memory request. Here, the command indicator identifies a programmable atomic operator command. In an example, when the memory request is a CPI block, the command indicator is in the first thirty-six bits of the CPI block header. This programmable atomic operator command indicates that a programmable atomic operator is requested, but does not identify the specific programmable atomic operator among the possible several programmable atomic operators supported by PAU 270. Specifically, the programmable atomic operator command prompts further verification of the block information to determine the specific PAO and any possible arguments provided for the programmable atomic operator in the request. Figure 5 The CPI memory request, programmable atomic operator command can correspond to CMD field 505.

[0058] In response to the command indicator recognizing the programmable atomic operator command, the programmable atomic operator index is extracted from the request. Here, the extraction of the programmable atomic operator index can be performed by other circuitry of the block decoder 230, cache controller 215, off-chip memory 220, PAU 270, or memory controller 205. In an example, when the memory request is in the form of a CPI block, the programmable atomic operator index is in a field of the extended portion of the CPI extended header. For example, shaded line 4 of block 500 is extended header 510 in block 500. Here, the programmable atomic operator index can be the CaPIdx field of extended header 510. In an example, the extended header includes a second extended portion containing the arguments of the PAO. Referring to request block 500, the extended portion contains any of line 5 and the subsequent DATA field. In an example, the second extended portion contains one to four 64-bit arguments. Here, in the context of request group 500, each of the DATA field rows maintains a 32-bit DATA field, resulting in the described data group containing two arguments, each of which includes two DATA fields.

[0059] PAU 270 is configured to invoke the programmable atomic operator based on the programmable atomic operator index. For example, given PAU 400, processor 405 can use the programmable atomic operator index to locate a partition in atomic instruction 425 and retrieve the kernel of the programmable atomic operator. This kernel can then be executed by processor 405 to execute the programmable atomic operator. Therefore, in this example, invoking a programmable atomic operator based on the programmable atomic operator index involves retrieving the kernel from the programmable atomic operator memory of PAU 270 (e.g., atomic instruction 425 in local memory 410) based on the programmable atomic operator index. The kernel can then be executed by PAU 270. In this example, retrieving the kernel based on the programmable atomic operator index involves reading a partition starting at the PAU index from the programmable atomic operator memory. Here, the index refers to the starting point in the PAU instruction memory (e.g., atomic instruction 425). The starting point can be multiplied by a memory offset to convert a partition number (e.g., 2) into a memory address. To retrieve the kernel, local memory is read from the starting point to the ending point. The endpoint can be specified as multiple words or ranges in memory, a final memory address, or a fixed memory address. In this example, the partition contains a terminating symbol, such that memory is read from the starting point until the terminating symbol is encountered.

[0060] Once the PAU 270 executes a programmable atomic operator, it produces a result. In some instances, the result is simply the return value of the programmable atomic operator, indicating whether the operator succeeded or failed. In others, the result is more complex, containing data generated from the programmable atomic operator.

[0061] PAU 270 can be configured to encapsulate results by generating a memory response and passing it to the requester who provided the memory request. Other components of memory controller 205, such as off-die memory controller 220 or packet encoder 240, may also participate in obtaining results from PAU 270 and generating memory responses. In this example, the memory response is a CPI packet (e.g., CPI response packet 600). In this example, the memory request is obtained from CPI virtual channel one, and the memory response is passed using CPI virtual channel two.

[0062] As mentioned above, before writing read data to cache 210, the set dangerous bits for reserved cache lines are cleared by memory dangerous clearing unit 260. Therefore, when the request and read data are received by write merging unit 255, a reset or clear signal can be transmitted from memory dangerous clearing unit 260 to cache 210 to reset the set memory dangerous bits for reserved cache lines. Furthermore, resetting these dangerous bits also releases pending read or write requests involving designated (or reserved) cache lines, thereby providing the pending read or write requests to the inbound request multiplexer for selection and processing.

[0063] Figure 3 This describes the components of an example of a memory controller chiplet according to an embodiment. Figure 3 It comes from Figure 2 Another representation of the memory controller 205 described herein. Figure 2 Many of the same components shown in the diagram are described here. For example, caches 302 and 385 are instances of cache 210; DRAM 340 is an instance of off-die memory 275 to 280; and atom / write merge 370 and programmable atom unit 380 may be instances of atom and merge unit 250. Figure 3 Other components can be Figure 2 Examples of other components include the die external memory controller 220 and the cache controller 215.

[0064] Other components not explicitly shown in memory controller 205 may include the following: NOC request queue 305 for receiving requests from the on-chip network and providing a small amount of queuing; atomic request queue 310 for receiving requests from programmable atomic units 380 and providing a small amount of queuing; and an inbound request multiplexer (IRM) for selecting among inbound memory request sources. In this example, the priority order of the three memory request sources is: memory danger request, atomic request, and inbound NOC request.

[0065] In this example, cache (read) 325 and cache (write) 375 are single devices implemented as SRAM data caches. The diagram illustrates the cache as two separate blocks (325 and 375), one providing read access and the other providing write access. Latency block 320 provides one or more pipeline stages to mimic the latency of SRAM cache read operations. Generally, a cache miss occurs when accessing off-die memory 340 (e.g., off-die memory 280) to bring the desired data into the cache. While waiting for a memory response (e.g., for access time to DRAM 340), the memory line is unavailable for other requests. Memory danger blocks (set block 315 and clear block 360) maintain a danger bit table indicating which memory lines are unavailable for access. Therefore, inbound requests attempting to access dangerous lines are held by the memory danger blocks until the danger is cleared. Once the danger is cleared, the request is retransmitted via the inbound request multiplexer. In this example, the memory row label address is hashed into a dangerous bit index. The number of dangerous bits can be selected to set the probability of dangerous collisions to a sufficiently low level.

[0066] The inbound DRAM control multiplexer (IDCM) selects from inbound NOC requests and cache eviction requests. For bank request queue 330, each individually managed DRAM bank has a dedicated bank request queue to hold requests until they can be scheduled on the associated DRAM bank.

[0067] Scheduler 335 selects from memory bank request queues 330 to select a request for an available DRAM memory bank. Request hit data queue 360 ​​holds request data from cache hits until selected. Request miss data queue 355 holds data read from DRAM until selected. Missed request queue 350 holds cache miss request packets until selected. Hit request queue 345 holds cache hit request packets until selected. Data selection multiplexer (DSM) selects between DRAM read data and cache hit read data. The selected data is written to the SRAM cache. Request selection multiplexer (RSM) selects between hit and miss request queues 345 and 355.

[0068] Atom / Write Merge 370 merges the requested data with DRAM read data, or, if the request is a built-in atom (e.g., built-in atom operation block 265), the memory data and the requested data are used as inputs for the atom operation. Cache (Write) Block 375 represents a write port for the SRAM cache. Data from the NOC write request and data from the DRAM read operation are written to the SRAM cache. Memory Danger (Clear) Block 365 represents a danger clearing operation for a memory danger structure. Clearing the danger releases the pending NOC request and sends it to the inbound request multiplexer. Programmable Atom Cell 380 processes programmable atom operations (e.g., transactions). The NOC Outbound Response Multiplexer (ORM) selects between a memory controller response and a custom atom cell response and sends the selection to the NOC.

[0069] Figure 4 This describes components in an example of the programmable atom unit 400 (PAU) according to an embodiment, such as those described above with respect to FIG1 (e.g., in memory controller 140) and Figure 2 (e.g., the components mentioned in PAU 270). As described, PAU 400 includes a processor 405, local memory 410 (e.g., SRAM), and a controller 415 for the local memory 410.

[0070] In this example, processor 405 is pipelined, enabling multiple levels of different instructions to execute together per clock cycle. Processor 405 is also a bucket multithreaded processor, having circuitry that switches between different register files (e.g., register sets containing the current processing state) per clock cycle of processor 405. This allows for efficient context switching between currently executing threads. In this example, processor 405 supports eight threads, resulting in eight register files. In this example, some or all of the register files are not integrated into processor 405 but reside in local memory 410 (register 420). This reduces the circuitry complexity in processor 405 by eliminating conventional flip-flops used for these registers 420.

[0071] Local memory 410 may also house cache 430 and instructions 425 for atomic operators. Atomic instructions 425 include an instruction set for supporting atomic operators loaded by various applications. When an atomic operator is requested, for example, by application chip 125, a set of instructions (e.g., kernel) corresponding to the atomic operator is executed by processor 405. In this example, atomic instructions 425 are partitioned to establish the instruction set. In this example, a specific programmable atomic operator requested by the requesting process can be identified by a partition number. The partition number can be established when the programmable atomic operator is registered with (e.g., loaded onto) PAU 400. Additional metadata for programmable atomic instructions 425 may also be stored in local memory 410, such as a partition table.

[0072] Atomic operators manipulate cache 430, which is typically synchronized (e.g., flushed) when the thread of the atomic operator completes. Therefore, latency is reduced for most memory operations during the execution of the programmable atomic operator thread, except for initial loads from external memory such as die-off memory 275 or 280.

[0073] Figure 5 This describes the chiplet protocol interface request packet 500 according to the embodiment. The following is a table of examples of CPI field descriptions and bit lengths corresponding to CPI request packet 500.

[0074]

[0075]

[0076] As explained, the shaded line in line 4 is the extended header 510. Command field 505 indicates that request 500 is for a PAO. However, an entity that decodes request 500 and provides PAO parameters to a PAU (e.g., PAU 270) will either pass the extended header 510 information to the PAU or decode the extended header 510 and provide the constituent fields as input to the PAU.

[0077] Figure 6 This describes the chiplet protocol interface response packet 600 according to an embodiment. Below is a table of examples of CPI field descriptions and bit lengths corresponding to the CPI response packet 600.

[0078]

[0079]

[0080] Figure 7This is a flowchart illustrating an example of a method 700 for passing a programmable atomic operator (PAO) to a memory controller according to an embodiment. The operation of method 700 is performed by computer hardware, such as reference to FIG1 (e.g., memory controller chiplet 140). Figure 2 (e.g., memory controller 205) Figure 3 or Figure 8 (e.g., description of processing circuit systems).

[0081] In operation 705, the memory controller receives (e.g., receives or retrieves) a memory request. In this example, the memory request is in the form of a CPI group (e.g., CPI request 500).

[0082] In operation 710, a command indicator is retrieved from the memory request. Here, the command indicator identifies the PAO command. In this example, when the memory request is a CPI packet, the command indicator is in the first 36 bits of the CPI packet's header. In this example, the header is an extended header.

[0083] In operation 715, in response to the command indicator recognizing the PAO command, the PAO index is retrieved from the request. In an example, when the memory request is in the form of a CPI group, the PAO index is in a field within the extended portion of the CPI extended header. In an example, the extended header includes a second extended portion containing the arguments of the PAO. In an example, the second extended portion contains between one and four arguments.

[0084] In operation 720, a PAO is invoked based on a PAO index. In an example, invoking a PAO based on a PAO index includes retrieving the kernel from the PAO memory of the memory controller based on the PAO index and executing the kernel on the PAU of the memory controller. In an example, retrieving the kernel based on the PAO index includes reading a partition from the PAO memory that starts at the PAO index.

[0085] In this example, the operation of method 700 can be extended to include generating a memory response and passing it to the requester who provided the memory request. Here, the memory response is generated in response to PAO completion, and the memory response includes the output from the PAO in its data field. In this example, generating the memory response includes creating a CPI packet (e.g., CPI response packet 600). In this example, the memory request is obtained from CPI virtual channel one, and the memory response is passed using CPI virtual channel two.

[0086] Figure 8This document illustrates a block diagram of an instance machine 800 in which any or more of the techniques (e.g., methods) discussed herein can be utilized, implemented, or carried out. As described herein, an instance may contain or be operable by logic or components or mechanisms in machine 800. A circuit system (e.g., a processing circuit system) is a collection of circuits implemented in a tangible entity of machine 800 containing hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system may be flexible over time. A circuit system contains members that can perform a specified operation individually or in combination during operation. In an instance, the hardware of the circuit system may be designed immutably to perform a specific operation (e.g., hardwiring). In an instance, the hardware of the circuit system may contain dynamically connected physical components (e.g., execution units, transistors, simple circuits, etc.) and machine-readable media that are physically modified (e.g., the magnetism, electricity, movable placement, etc. of particles with invariant mass) to encode instructions for the specific operation. In connecting the physical components, the underlying electrical properties of the hardware configuration (e.g.,) are changed from an insulator to a conductor or vice versa. Instructions enable embedded hardware (e.g., an execution unit or a loading mechanism) to create members of a circuit system within the hardware via variable connections to perform specific operations in operation. Thus, in an example, a machine-readable media element is either part of a circuit system or another component communicatively coupled to the circuit system when the device operates. In an example, any of the physical components can be used in more than one member of more than one circuit system. For example, in operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and reused at different times by a second circuit in the first circuit system or by a third circuit in the second circuit system. Additional examples of these components of machine 800 are as follows.

[0087] In alternative embodiments, machine 800 may operate as a standalone device or be connected (e.g., networked) to other machines. In a networked deployment, machine 800 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 800 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 800 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein, such as cloud computing, Software as a Service (SaaS), and other computer cluster configurations.

[0088] Machine (e.g., computer system) 800 may include a hardware processor 802 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 804, static memory (e.g., memory or storage device for firmware, microcode, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.) 806, and mass storage device 808 (e.g., hard disk drive, tape drive, flash memory, or other block device), some or all of which may communicate with each other via an interconnect (e.g., bus) 830. Machine 800 may further include a display unit 810, an alphanumeric input device 812 (e.g., keyboard), and a user interface (UI) navigation device 814 (e.g., mouse). In an example, the display unit 810, input device 812, and UI navigation device 814 may be a touchscreen display. Machine 800 may additionally include a storage device (e.g., a drive unit) 808, a signal generating device 818 (e.g., a speaker), a network interface device 820, and one or more sensors 816 (e.g., a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors). Machine 800 may include an output controller 828, for example, for communicating or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.) via serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connections.

[0089] The registers of processor 802, main memory 804, static memory 806, or mass storage device 808 may be or contain machine-readable medium 822, on which one or more sets of data structures or instructions 824 (e.g., software) embodying or utilized by any or more of the techniques or functions described herein. Instructions 824 may also reside wholly or at least partially in any of the registers of processor 802, main memory 804, static memory 806, or mass storage device 808 during execution by machine 800. In an example, one or any combination of hardware processor 802, main memory 804, static memory 806, or mass storage device 808 may constitute machine-readable medium 822. Although machine-readable medium 822 is described as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database or associated cache and server) configured to store one or more instructions 824.

[0090] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions executable by machine 800 and causing machine 800 to perform any or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable media may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In examples, non-transitory machine-readable media includes machine-readable media having a plurality of particles with invariant (e.g., rest) mass, and thus being a composition of matter. Therefore, non-transitory machine-readable media is machine-readable media that does not contain transiently propagating signals. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0091] In an example, information stored or otherwise provided on machine-readable medium 822 may represent instructions 824, such as instructions 824 itself or a format from which instructions 824 can be derived. This format from which instructions 824 can be derived may contain source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., divided into multiple packages), or the like. Information representing instructions 824 in machine-readable medium 822 may be processed by a processing circuitry system into instructions for performing any of the operations discussed herein. For example, deriving instructions 824 from information (e.g., processed by a processing circuitry system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamic or static linking), encoding, decoding, encrypting, decrypting, packaging, depackaging, or otherwise manipulating the information into instructions 824.

[0092] In an example, the derivation of instruction 824 may involve the assembly, compilation, or interpretation (e.g., by processing a circuit system) of information to create instruction 824 from some intermediate or preprocessed format provided by machine-readable media 822. Information provided in multiple parts may be combined, unpacked, and modified to create instruction 824. For example, the information may be in multiple compressed source code packages (or object code or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted during transmission over a network and, if necessary, decrypted, decompressed, assembled (e.g., linked), and compiled or interpreted (e.g., into a library, a standalone executable, etc.) on a local machine and executed by the local machine.

[0093] Instruction 824 may further use a transmission medium to transmit or receive via a communication network 826 through a network interface device 820 that utilizes any of several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include Local Area Networks (LANs), Wide Area Networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone networks (POTS), and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series standards, referred to as...). ), IEEE 802.16 series standards (referred to as IEEE 802.15.4 series standards, peer-to-peer (P2P) networks, etc. In an example, network interface device 820 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 826. In an example, network interface device 820 may include multiple antennas to perform wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions executable by machine 800, and includes digital or analog communication signals or other intangible media used to facilitate communication of this software. The transmission medium is a machine-readable medium. To better illustrate the methods and apparatus described herein, a set of non-limiting example embodiments are denoted as digitally identified examples below.

[0094] Example 1 is a memory controller for passing programmable atomic operators (PAOs) to a memory controller, the memory controller comprising: a network interface configured to receive a memory request; a block decoder configured to: retrieve a command indicator from the memory request, the command indicator indicating a PAO command; and retrieve a PAO index from the memory request in response to the command indicator indicating the PAO command; and a programmable atomic unit (PAU) configured to invoke the PAO based on the PAO index.

[0095] In Example 2, based on the subject matter described in Example 1, the memory request is in the form of a Chipset Packet Interface (CPI) packet.

[0096] In Example 3, based on the subject described in Example 2, the command indicator is in the first thirty-six bits of the header of the CPI group.

[0097] In Example 4, based on the topic described in Example 3, the header is an extended header; and the PAO index is in a field in the extended portion of the extended header.

[0098] In Example 5, based on the subject described in Example 4, the extended header includes a second extended portion containing the arguments of the PAO.

[0099] In Example 6, based on the subject described in Example 5, the second extension includes one to four arguments.

[0100] In Example 7, based on the subject described in any of Examples 1 to 6, wherein in order to invoke the PAO based on the PAO index, the PAU is configured to: retrieve the kernel from the PAO memory in the PAU based on the PAO index; and execute the kernel.

[0101] In Example 8, following the theme described in Example 7, the PAU is configured to read a partition starting from the PAO index from the PAO memory in order to retrieve the kernel based on the PAO index.

[0102] In Example 9, based on the subject matter described in any of Examples 1 to 8, it includes: a block encoder configured to generate a memory response in response to the completion of the PAO, the memory response containing output from the PAO in a data field; and wherein the network interface is configured to pass the memory response to a requester who provided the memory request.

[0103] In Example 10, based on the subject matter described in Example 9, the packet encoder is configured to create a chiplet packet interface (CPI) packet in order to generate the memory response.

[0104] In Example 11, based on the subject matter of Example 10, the memory request is obtained from CPI virtual channel one; and the network interface is configured to use CPI virtual channel two in order to deliver the memory response.

[0105] Example 12 is a method comprising: obtaining a memory request at the memory controller; retrieving a command indicator from the memory request, the command indicator indicating a PAO command; retrieving a PAO index from the request in response to the command indicator indicating the PAO command; and invoking the PAO based on the PAO index.

[0106] In Example 13, based on the subject matter described in Example 12, the memory request is in the form of a Chipset Packet Interface (CPI) packet.

[0107] In Example 14, based on the subject described in Example 13, the command indicator is in the first thirty-six bits of the header of the CPI group.

[0108] In Example 15, based on the subject described in Example 14, the header is an extended header; and the PAO index is in a field in the extended portion of the extended header.

[0109] In Example 16, based on the subject described in Example 15, the extended header includes a second extended portion containing the arguments of the PAO.

[0110] In Example 17, based on the subject described in Example 16, the second extension contains one to four arguments.

[0111] In Example 18, based on the subject matter described in any of Examples 12 to 17, invoking the PAO based on the PAO index comprises: the programmable atomic unit (PAU) of the memory controller retrieving the kernel from the PAO memory in the PAO based on the PAO index; and executing the kernel.

[0112] In Example 19, based on the subject described in Example 18, the kernel is retrieved based on the PAO index, which includes reading a partition from the PAO memory that starts at the PAO index.

[0113] In Example 20, based on the subject matter described in any of Examples 12 to 19, it includes: generating a memory response that is generated in response to the completion of the PAO, the memory response including output from the PAO in a data field; and passing the memory response to the requester who provided the memory request.

[0114] In Example 21, based on the subject matter described in Example 20, generating the memory response includes: creating a chiplet grouping interface (CPI) group.

[0115] In Example 22, based on the subject matter of Example 21, the memory request is obtained from CPI virtual channel one; and the delivery of the memory response includes using CPI virtual channel two.

[0116] Example 23 is a machine-readable medium containing instructions that, when executed by the circuitry of a memory controller, cause the memory controller to perform operations including: obtaining a memory request; retrieving a command indicator from the memory request, the command indicator indicating a PAO command; retrieving a PAO index from the request in response to the command indicator indicating the PAO command; and invoking the PAO based on the PAO index.

[0117] In Example 24, based on the subject matter described in Example 23, the memory request is in the form of a Chipset Packet Interface (CPI) packet.

[0118] In Example 25, based on the subject described in Example 24, the command indicator is in the first thirty-six bits of the header of the CPI group.

[0119] In Example 26, based on the subject described in Example 25, the header is an extended header; and the PAO index is in a field in the extended portion of the extended header.

[0120] In Example 27, based on the subject described in Example 26, the extended header includes a second extended portion containing the arguments of the PAO.

[0121] In Example 28, based on the subject described in Example 27, the second extension contains one to four arguments.

[0122] In Example 29, based on the subject matter of any of Examples 23 to 28, invoking the PAO based on the PAO index comprises: the programmable atomic unit (PAU) of the memory controller retrieving the kernel from the PAO memory in the PAO based on the PAO index; and executing the kernel.

[0123] In Example 30, based on the subject described in Example 29, the kernel is retrieved based on the PAO index, which includes reading a partition from the PAO memory that starts at the PAO index.

[0124] In Example 31, based on the subject matter of any of Examples 23 to 30, the operation includes: generating a memory response that is generated in response to the completion of the PAO, the memory response including output from the PAO in a data field; and passing the memory response to the requester who provided the memory request.

[0125] In Example 32, based on the subject matter described in Example 31, generating the memory response includes: creating a chiplet grouping interface (CPI) group.

[0126] In Example 33, based on the subject matter of Example 32, the memory request is obtained from CPI virtual channel one; and the delivery of the memory response includes using CPI virtual channel two.

[0127] Example 34 is a system comprising: components for obtaining a memory request; components for retrieving a command indicator from the memory request, the command indicator indicating a PAO command; components for retrieving a PAO index from the request in response to the command indicator indicating the PAO command; and components for invoking the PAO based on the PAO index.

[0128] In Example 35, based on the subject matter described in Example 34, the memory request is in the form of a Chipset Packet Interface (CPI) packet.

[0129] In Example 36, based on the subject described in Example 35, the command indicator is in the first thirty-six bits of the header of the CPI group.

[0130] In Example 37, based on the subject described in Example 36, the header is an extended header; and the PAO index is in a field in the extended portion of the extended header.

[0131] In Example 38, based on the subject described in Example 37, the extended header includes a second extended portion containing the arguments of the PAO.

[0132] In Example 39, based on the subject described in Example 38, the second extension includes one to four arguments.

[0133] In Example 40, according to the subject matter of any of Examples 34 to 39, the system includes a programmable atomic unit comprising: a component for retrieving a kernel from a PAO memory in the PAU based on the PAO index; and a component for executing the kernel.

[0134] In Example 41, according to the subject matter described in Example 40, the component for retrieving the kernel based on the PAO index includes a component for reading a partition starting from the PAO index from the PAO memory.

[0135] In Example 42, the subject matter according to any of Examples 34 to 41 includes: a component for generating a memory response, the memory response being generated in response to the completion of the PAO, the memory response including output from the PAO in a data field; and a component for passing the memory response to a requester who provided the memory request.

[0136] In Example 43, according to the subject matter described in Example 42, the components for generating the memory response include components for creating chiplet packet interface (CPI) packets.

[0137] In Example 44, based on the subject matter of Example 43, the memory request is obtained from CPI virtual channel one; and the component for transmitting the memory response includes a component for using CPI virtual channel two.

[0138] Example 45 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform any of the operations described in Examples 1 to 44.

[0139] Example 46 is a device that includes components for implementing any of Examples 1 to 44.

[0140] Example 47 is a system for implementing any of Examples 1 through 44.

[0141] Example 48 is a method for implementing any of Examples 1 through 44.

[0142] The detailed description above includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors also contemplate examples (or examples) using any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0143] In this document, as is common in patent documents, the term "a / an" is used to include one or more, independent of any other example or use of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive "or", such that "A or B" may include "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "comprising" and "in which" are used as their common English equivalents to the corresponding terms "including" and "wherein". Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after this term in a claim is still considered to fall within the scope of the claim. Additionally, in the appended claims, the terms "first", "second", and "third", etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0144] The foregoing description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the foregoing description. It should be understood that the foregoing description is not intended to interpret or limit the scope or meaning of the claims. Moreover, various features may be combined in the detailed description above to simplify this disclosure. This should not be interpreted as an intention that any unclaimed disclosed features are necessary for any claim. Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim is itself an individual embodiment, and such embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined with reference to the appended claims together with the full scope of their equivalents.

Claims

1. An apparatus comprising: A network interface that can be coupled to a chiplet in a host or chiplet system and configured to receive memory requests; The block decoder is configured to: A fetch command indicator is requested from the memory, the command indicator indicating a programmable atomic operator command; and In response to the command indicator instructing the programmable atomic operator command, a programmable atomic operator index is requested to be retrieved from the memory, the programmable atomic operator index indicating the location of the kernel of the programmable atomic operator command, the kernel including instructions for implementing the programmable atomic operator command; and Programmable atomic units, configured to invoke the programmable atomic operators based on the programmable atomic operator index.

2. The device of claim 1, wherein the memory request is in the form of a Chipset Packet Interface (CPI) packet.

3. The device of claim 2, wherein the command indicator is in the first thirty-six bits of the header of the CPI group.

4. The device according to claim 3, wherein the header is an extended header; and The programmable atomic operators are indexed in fields within the extended portion of the extended header.

5. The device of claim 4, wherein the extended header includes a second extended portion, the second extended portion including the arguments of the programmable atomic operator.

6. The device of claim 5, wherein the second extension portion comprises one to four independent variables.

7. The apparatus of claim 1, wherein, in order to invoke the programmable atomic operator based on the programmable atomic operator index, the programmable atomic unit is configured to: The kernel is retrieved from the programmable atomic operator memory in the programmable atomic unit based on the programmable atomic operator index; and Execute the kernel.

8. The device of claim 7, wherein, in order to retrieve the kernel based on the programmable atomic operator index, the programmable atomic unit is configured to read a partition starting from the programmable atomic operator index from the programmable atomic operator memory.

9. The device according to claim 1, comprising: A group encoder configured to generate a memory response in response to the completion of the programmable atomic operator, the memory response containing the output from the programmable atomic operator in a data field; and The network interface is configured to pass the memory response to the requester who made the memory request.

10. The device of claim 9, wherein in order to generate the memory response, the packet encoder is configured to create a Chipset Packet Interface (CPI) packet.

11. The device of claim 10, wherein the memory request is obtained from CPI virtual channel one; and In order to transmit the memory response, the network interface is configured to use CPI virtual channel two.

12. A method comprising: Obtain a memory request from the memory controller; A fetch command indicator is requested from the memory, the command indicator indicating a programmable atomic operator command; In response to the command indicator instructing the programmable atomic operator command, a programmable atomic operator index is extracted from the request, the programmable atomic operator index indicating the location of the kernel of the programmable atomic operator command, the kernel including instructions for implementing the programmable atomic operator command; and The programmable atomic operator is invoked based on the programmable atomic operator index.

13. The method of claim 12, wherein the memory request is in the form of a Chipset Packet Interface (CPI) packet.

14. The method of claim 13, wherein the command indicator is in the first thirty-six bits of the header of the CPI group.

15. The method of claim 14, wherein the header is an extended header; and The programmable atomic operators are indexed in fields within the extended portion of the extended header.

16. The method of claim 15, wherein the extended header includes a second extended portion, the second extended portion including the arguments of the programmable atomic operator.

17. The method of claim 16, wherein the second extension comprises one to four independent variables.

18. The method of claim 12, wherein invoking the programmable atomic operator based on the programmable atomic operator index comprises a programmable atomic unit of the memory controller: The kernel is retrieved from the programmable atomic operator memory in the programmable atomic unit based on the programmable atomic operator index; and Execute the kernel.

19. The method of claim 18, wherein retrieving the kernel based on the programmable atomic operator index comprises: reading a partition starting from the programmable atomic operator index from the programmable atomic operator memory.

20. The method of claim 12, further comprising: A memory response is generated in response to the completion of the programmable atomic operator, and the memory response contains the output from the programmable atomic operator in a data field; and The memory response is passed to the requester who made the memory request.

21. The method of claim 20, wherein generating the memory response comprises: creating a Chipset Packet Interface (CPI) packet.

22. The method of claim 21, wherein the memory request is obtained from CPI virtual channel one; and The transmission of the memory response includes the use of CPI virtual channel two.

23. A machine-readable medium containing instructions that, when executed by a circuitry of a memory controller, cause the memory controller to perform operations including: Obtain a memory request; A fetch command indicator is requested from the memory, the command indicator indicating a programmable atomic operator command; In response to the command indicator instructing the programmable atomic operator command, a programmable atomic operator index is extracted from the request, the programmable atomic operator index indicating the location of the kernel of the programmable atomic operator command, the kernel including instructions for implementing the programmable atomic operator command; and The programmable atomic operator is invoked based on the programmable atomic operator index.

24. The machine-readable medium of claim 23, wherein the memory request is in the form of a Chipset Packet Interface (CPI) packet.

25. The machine-readable medium of claim 24, wherein the command indicator is in the first thirty-six bits of the header of the CPI group.

26. The machine-readable medium of claim 25, wherein the header is an extended header; and The programmable atomic operators are indexed in fields within the extended portion of the extended header.

27. The machine-readable medium of claim 26, wherein the extended header includes a second extension portion that includes the arguments of the programmable atomic operator.

28. The machine-readable medium of claim 27, wherein the second extension portion comprises one to four arguments.

29. The machine-readable medium of claim 23, wherein invoking the programmable atomic operator based on the programmable atomic operator index comprises a programmable atomic unit of the memory controller: The kernel is retrieved from the programmable atomic operator memory in the programmable atomic unit based on the programmable atomic operator index; and Execute the kernel.

30. The machine-readable medium of claim 29, wherein retrieving the kernel based on the programmable atomic operator index comprises: reading a partition starting at the programmable atomic operator index from the programmable atomic operator memory.

31. The machine-readable medium of claim 23, wherein the operation comprises: A memory response is generated in response to the completion of the programmable atomic operator, and the memory response contains the output from the programmable atomic operator in a data field; and The memory response is passed to the requester who made the memory request.

32. The machine-readable medium of claim 31, wherein generating the memory response comprises: creating a Chipset Packet Interface (CPI) packet.

33. The machine-readable medium of claim 32, wherein the memory request is obtained from CPI virtual channel one; and The transmission of the memory response includes the use of CPI virtual channel two.

34. A system comprising: Components used to obtain memory requests; A component for requesting a command indicator to be retrieved from the memory, the command indicator indicating a programmable atomic operator command; A component for retrieving a programmable atomic operator index from a request in response to a command indicator instructing the programmable atomic operator command, the programmable atomic operator index indicating the location of a kernel for the programmable atomic operator command, the kernel including instructions for implementing the programmable atomic operator command; and A component for invoking the programmable atomic operator based on the programmable atomic operator index.

35. The system of claim 34, wherein the memory request is in the form of a Chipset Packet Interface (CPI) packet.

36. The system of claim 35, wherein the command indicator is in the first thirty-six bits of the header of the CPI group.

37. The system of claim 36, wherein the header is an extended header; and The programmable atomic operators are indexed in fields within the extended portion of the extended header.

38. The system of claim 37, wherein the extended header includes a second extended portion, the second extended portion including the arguments of the programmable atomic operator.

39. The system of claim 38, wherein the second extension portion comprises one to four independent variables.

40. The system of claim 34, wherein the system comprises programmable atomic units, the programmable atomic units comprising: Components for retrieving the kernel from the programmable atomic operator memory in the programmable atomic unit based on the programmable atomic operator index; and The components used to execute the kernel.

41. The system of claim 40, wherein the component for retrieving the kernel based on the programmable atomic operator index comprises: a component for reading a partition starting from the programmable atomic operator index from the programmable atomic operator memory.

42. The system of claim 34, comprising: A component for generating a memory response, the memory response being generated in response to the completion of the programmable atomic operator, the memory response containing the output from the programmable atomic operator in a data field; and A component for passing the memory response to the requester who made the memory request.

43. The system of claim 42, wherein the component for generating the memory response includes a component for creating a Chipset Packet Interface (CPI) packet.

44. The system of claim 43, wherein the memory request is obtained from CPI virtual channel one; and The component used to transmit the memory response includes a component for using CPI virtual channel two.

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