Memory device and method of operating a memory device

Abstract

The technology includes a memory device and a method of operating a memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause threshold voltages of selected memory cells included in selected pages in the memory cells to reach a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying normal programming or dual programming to the program loops.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0128804, filed on October 6, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The disclosure relates to a memory device and a method of operating a memory device, and more particularly, to a memory device capable of performing a program operation. BACKGROUND

[0004] A memory device can include a volatile memory device in which stored data is destroyed when a power is cut off, and a non-volatile memory device in which stored data is maintained even if a power is cut off.

[0005] The volatile memory device can include a dynamic random access memory (DRAM) and a static random access memory (SRAM). The non-volatile memory device can include a read only memory (ROM), a programmable read only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a NAND FLASH, etc.

[0006] The memory device can include a memory cell array, a peripheral circuit, and a control logic circuit.

[0007] The memory cell array can include a plurality of memory cells, and the plurality of memory cells can store data. A method of storing one bit of data in one memory cell is referred to as a single level cell (SLC) method, and a method of storing two or more bits of data in one memory cell is referred to as a multi-level cell (MLC) method. According to the number of bits stored in the memory cell, the program operation of the MLC method can be divided into a triple level cell (TLC) method or a quad level cell (QLC) method. In the TLC method, three bits of data can be stored in one memory cell, and in the QLC method, four bits of data can be stored in one memory cell. SUMMARY

[0008] A memory device according to an embodiment of the present disclosure can include a memory block including memory cells, a peripheral circuit configured to perform a plurality of programming loops to cause a threshold voltage of a selected memory cell included in a selected page among the memory cells to reach a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the programming loops by selectively applying a normal programming or a double programming to the programming loops and changing a maximum number of times the double programming is applied according to an operating condition of the programming loops. The normal programming can increase the threshold voltage of the selected memory cell by a first change amount. The double programming can increase the threshold voltage by a second change amount, which is lower than the first change amount.

[0009] A method of operating a memory device according to an embodiment of the present disclosure can include performing a plurality of programming loops to program a selected memory cell by applying an increasing programming voltage to a selected word line to which the selected memory cell is connected. A maximum number of times a double programming is used to increase a threshold voltage between a target voltage and a sub-verify voltage lower than the target voltage more slowly than a reference is set to a first number when the programming voltage is equal to or lower than a reference level, and is set to a second number greater than the first number when the programming voltage is higher than the reference level.

[0010] A method of operating a memory device according to an embodiment of the present disclosure can include performing a programming operation of a selected memory cell by applying an increasing programming voltage to a selected word line to which the selected memory cell is connected. A maximum number of times a double programming is used to increase a threshold voltage between a target voltage and a sub-verify voltage lower than the target voltage more slowly than a reference is set to a first number in an initial period of the programming operation, and is increased to a second number greater than the first number as the programming operation proceeds.

[0011] A method of operating a memory device according to an embodiment of the present disclosure can include performing a plurality of programming loops to program a selected memory cell by applying an increasing programming voltage to a selected word line to which the selected memory cell is connected. A maximum number of times a double programming is used to increase a threshold voltage between a target voltage and a sub-verify voltage lower than the target voltage more slowly than a reference is set to a first number when the target voltage of the memory cell is equal to or lower than a reference level, and is set to a second number greater than the first number when the target voltage of the memory cell is higher than the reference level. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 This is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0015] Figure 4 This is a diagram illustrating a page buffer group according to an embodiment of the present disclosure.

[0016] Figure 5 This is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0017] Figure 6 This is a diagram illustrating the threshold voltage distribution of a memory cell.

[0018] Figure 7 This is a diagram illustrating programming operations according to embodiments of the present disclosure.

[0019] Figure 8 This is a diagram illustrating the programming operations of a dual programming method according to an embodiment of the present disclosure.

[0020] Figure 9 This is a diagram illustrating a programming loop according to an embodiment of the present disclosure.

[0021] Figure 10A and Figure 10B This is a diagram illustrating a method of applying voltage to a bit line according to an embodiment of the present disclosure.

[0022] Figure 11 This is a diagram illustrating programming operations according to a first embodiment of the present disclosure.

[0023] Figure 12 This is a diagram illustrating a programming loop of programming operations performed according to a first embodiment of the present disclosure.

[0024] Figure 13A and Figure 13B This is a diagram illustrating the maximum number of sub-programming operations during programming operations according to a first embodiment of the present disclosure, based on dual programming.

[0025] Figure 14 This is a diagram illustrating programming operations according to a second embodiment of the present disclosure.

[0026] Figure 15A , Figure 15B and Figure 15C This is a diagram illustrating a programming loop of programming operations performed according to a second embodiment of the present disclosure.

[0027] Figure 16is a diagram illustrating a programming operation according to a third embodiment of the present disclosure.

[0028] Figure 17 is a diagram illustrating a programming cycle of a programming operation performed according to a third embodiment of the present disclosure.

[0029] Figure 18A and Figure 18B is a diagram illustrating a programming operation according to a fourth embodiment of the present disclosure.

[0030] Figure 19 is a diagram illustrating a memory card system to which a memory device of the present disclosure is applied.

[0031] Figure 20 is a diagram illustrating a solid state drive (SSD) system to which a memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0032] Embodiments of the present disclosure provide a memory device capable of improving a threshold voltage distribution of a memory cell during a programming operation, and a method of operating the memory device.

[0033] The present technology can improve a threshold voltage distribution of a memory cell during a programming operation.

[0034] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0035] Referring to Figure 1 , the memory system 1000 can include a storage device 1100 and a controller 1200. The storage device 1100 can include a plurality of memory devices MD, and the memory devices MD can be connected to the controller 1200 through input / output lines.

[0036] The controller 1200 can communicate between the host 1500 and the memory devices MD. The controller 1200 can generate a command CMD for controlling the memory devices MD according to a request RQ of the host 1500, and can perform a background operation to improve the performance of the memory system 1000 even if there is no request RQ of the host 1500.

[0037] The host 1500 can generate a request RQ for various operations, and can output the generated request RQ to the memory system 1000. For example, the request RQ can include a program request that can control a programming operation, a read request that can control a read operation, an erase request that can control an erase operation, and the like.

[0038] The host 1500 can communicate with the memory system 1000 through various interfaces such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0039] The memory device MD according to the present embodiment can perform a program operation. The program operation can be performed in an incremental step pulse programming (ISPP) method in which a program voltage is gradually increased. In the present embodiment, the memory device MD can perform a program operation of the ISPP method in which a normal program method and a double program method are selectively applied, or the normal program method and the double program method are selectively mixed.

[0040] The normal program method is a method in which, when a program voltage is applied to a selected word line, a program enable voltage is applied to the selected word line, and a program inhibit voltage is applied to an unselected bit line. The selected word line refers to a word line connected to a memory cell which is a target of programming. The selected bit line refers to a bit line connected to a memory cell whose threshold voltage is lower than a target voltage, and the unselected bit line refers to a bit line connected to a memory cell whose threshold voltage is increased to be equal to or higher than the target voltage. The program enable voltage can be a voltage having a large potential difference from the program voltage applied to the selected word line, and can be, for example, 0 V. The program inhibit voltage can be a voltage having a small potential difference from the program voltage, and can be, for example, a positive voltage of 18 V or more.

[0041] The double program method is a method in which, when a program voltage is applied to a selected word line, a program enable voltage is applied to a bit line connected to a memory cell having a large difference between a threshold voltage and a target voltage among selected bit lines, a program step-down voltage is applied to a bit line connected to a memory cell having a small difference between the threshold voltage and the target voltage, and a program inhibit voltage is applied to an unselected bit line. For convenience of description, the bit line connected to the memory cell having a large difference between the threshold voltage and the target voltage can be defined as a first state bit line, and the bit line connected to the memory cell having a relatively small difference between the threshold voltage and the target voltage can be defined as a second state bit line. The program step-down voltage can be a voltage for slowly increasing the threshold voltage of the memory cell connected to the second state bit line than the threshold voltage of the memory cell connected to the first state bit line. For example, the program step-down voltage can be set to a positive voltage between the program inhibit voltage and the program enable voltage.

[0042] Figure 2 is a diagram illustrating a memory device according to an embodiment of the disclosure.

[0043] Referring to Figure 2 , the memory device MD can include an array 110 of memory cells in which data is stored, a peripheral circuit 200 that performs a program operation, a read operation, or an erase operation, and a control logic circuit 160 that controls the peripheral circuit 200.

[0044] The array 110 of memory cells can include a plurality of memory blocks BLK1 to BLKi in which data is stored. Each of the memory blocks BLK1 to BLKi can include a plurality of memory cells, and the memory cells can be implemented in a two-dimensional structure arranged in parallel with a substrate or a three-dimensional structure stacked in a vertical direction on the substrate.

[0045] The peripheral circuit 200 can include a voltage generator 120, a row decoder 130, a page buffer group 140, and an input / output circuit 150.

[0046] The voltage generator 120 can generate and output an operating voltage Vop required for various operations in response to a voltage code VCD. For example, the voltage generator 120 can generate and output a program voltage, a verify voltage, a read voltage, a pass voltage, an erase voltage, etc. having various levels.

[0047] The row decoder 130 can select one memory block among the memory blocks BLK1 to BLKi included in the array 110 of memory cells according to a row address RADD and transmit the operating voltage Vop to the selected memory block.

[0048] The page buffer group 140 can be connected to the array 110 of memory cells through a bit line. For example, the page buffer group 140 can include page buffers connected to respective bit lines. The page buffers can operate simultaneously in response to a page buffer control signal PBSIG and can temporarily store data during a program or read operation. A verify operation performed during a program operation and a verify operation performed during an erase operation can be performed in the same method as a read operation.

[0049] During a read operation or a verify operation, the page buffer can sense the voltage of the bit line, which varies according to the threshold voltage of the memory cell. That is, it can be determined whether the threshold voltage of the memory cell is lower or higher than the read voltage or the verify voltage according to the result of the sensing operation performed in the page buffer. During a program operation of the normal programming method, the page buffer can apply the program enable voltage to the selected bit line and the program inhibit voltage to the unselected bit line. During a program operation of the dual programming method, the page buffer can apply the program enable voltage to the first state bit line, the program lower voltage to the second state bit line, and the program inhibit voltage to the unselected bit line.

[0050] The input / output circuit 150 can be connected to the controller 1200 through an input / output line. Figure 1 The input / output circuit 150 can input / output a command CMD, an address ADD, and data DATA through the input / output line. For example, the input / output circuit 150 can transmit the command CMD and the address ADD received through the input / output line to the control logic circuit 160, and transmit the data DATA received through the input / output line to the page buffer group 140. The input / output circuit 150 can output the data DATA received from the page buffer group 140 to the controller 1200 through the input / output line.

[0051] The control logic circuit 160 can output a voltage code VCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, the control logic circuit 160 can include software that performs an algorithm in response to the command CMD, and hardware configured to output various signals according to the address ADD and the algorithm.

[0052] The control logic circuit 160 can adjust the number of times that the dual programming is applied according to an operating condition during a program operation of a selected page included in a plurality of pages in a selected memory block. In an embodiment, the operating condition can include at least one of a program voltage, a step voltage, a segmentation of a program cycle (i.e., see Figure 16 ), and a target voltage.

[0053] Figure 3 is a diagram illustrating a memory block according to an embodiment of the disclosure, and illustrates an i-th memory block BLKi among a plurality of memory blocks BLK1 to BLKi. Figure 2

[0054] Referring to Figure 3 ​The i-th memory block BLKi can include a plurality of strings ST1 to STj (j is a positive integer). The first to j-th strings ST1 to STj can be connected between bit lines BL1 to BLj and a source line SL. For example, the first string ST1 can be connected between a first bit line BL1 and the source line SL, the second string ST2 can be connected between a second bit line BL2 and the source line SL, and the j-th string STj can be connected between a j-th bit line BLj and the source line SL.

[0055] Each of the first to j-th strings ST1 to STj can include a source select transistor SST, a plurality of memory cells C1 to Cn, and a drain select transistor DST. Although not shown in the drawing, a dummy cell can be further included between the memory cells C1 to Cn and the source or drain select transistor SST or DST. The configuration of the string is specifically described below with the j-th string STj as an example.

[0056] The source select transistor SST included in the j-th string STj can be electrically connected or disconnected between the source line SL and the first memory cell C1 according to a voltage applied to a source select line SSL. The gates of the first to n-th memory cells C1 to Cn can be connected to first to n-th word lines WL1 to WLn, respectively. The drain select transistor DST can be electrically connected or disconnected between the j-th bit line BLj and the n-th memory cell Cn according to a voltage applied to a drain select line DSL. The gates of the source select transistors SST included in different strings ST1 to STj can be commonly connected to the source select line SSL, and the gates of the first to n-th memory cells C1 to Cn can be connected to the first to n-th word lines WL1 to WLn, and the gates of the drain select transistors DST can be commonly connected to the drain select line DSL. A group of memory cells connected to the same word line is called a page PG, and a program and a read operation can be performed in units of the page PG.

[0057] The programming operation according to the present embodiment can be performed in an incremental step pulse programming (ISPP) method in which a programming voltage is gradually increased in increments. In the programming operation of the ISPP method, a plurality of programming loops can be performed until the threshold voltage of the selected memory cell increases to a target voltage, and the programming voltage can be gradually increased each time a programming loop is performed. In each programming loop, a sub-programming operation for increasing the threshold voltage of the selected memory cell and a verify operation for determining whether the threshold voltage of the selected memory cell increases to the target voltage can be performed. In the sub-programming operation, a programming voltage can be applied to the selected word line, and in the verify operation, a verify voltage can be applied to the selected word line. An operation of determining whether the verify operation passes or fails according to the data of the memory cell sensed in the verify operation can be performed in the sub-programming operation of the next programming loop. The operation of determining whether the verify operation passes or fails during the sub-programming operation can be a current sense check operation.

[0058] Figure 4 is a diagram illustrating a page buffer group according to an embodiment of the present disclosure.

[0059] Referring to Figure 4 , the page buffer group 140 can include first to jth page buffers PB1 to PBj. The first to jth page buffers PB1 to PBj can be connected to first to jth bit lines BL1 to BLj, respectively. When a programming operation starts, the first to jth page buffers PB1 to PBj can store data output from the controller 1200 of the memory device 1000, and can apply a program enable voltage, a program down voltage, or a program inhibit voltage to the first to jth bit lines BL1 to BLj according to the stored data. After the programming operation starts, the first to jth page buffers PB1 to PBj can selectively apply the program enable voltage, the program down voltage, or the program inhibit voltage to the first to jth bit lines BL1 to BLj according to data stored during a verify operation and data sensed from a selected memory cell. For example, the program enable voltage can be 0 V, and the program down voltage can be a positive voltage higher than the program enable voltage. The program inhibit voltage can be a positive voltage higher than the program down voltage. Figure 1

[0060] Figure 5 is a diagram illustrating a page buffer according to an embodiment of the present disclosure, and as shown in Figure 4 , a jth page buffer PBj is shown as an example.

[0061] Referring to Figure 5 ​The jth page buffer PBj can include a plurality of latches LAT1 to LATk. Some of the plurality of latches LAT1 to LATk can store data received from the controller, and other latches can store data sensed during the verify operation. The jth page buffer PBj can apply the program enable voltage, the program down voltage, or the program inhibit voltage to the jth bit line BLj according to the data sensed during the verify operation and the data received from the controller.

[0062] Figure 6 is a graph illustrating a threshold voltage distribution of a memory cell.

[0063] Referring to Figure 6 A program operation can be divided into various methods according to the number of bits stored in a memory cell. For example, a method of storing three-bit data in one memory cell is referred to as a triple-level cell (TLC) method, and a method of storing four-bit data in one memory cell is referred to as a quad-level cell (QLC) method.

[0064] In the TLC method, a state of a memory cell can have one erase state ER and any one of seven program states P1 to P7. In the QLC method, a state of a memory cell can have one erase state ER and any one of fifteen program states P1 to P15.

[0065] When described by way of example of the TLC method, the first to seventh program states P1 to P7 can be divided into different first to seventh target voltages PV1 to PV7. As the number of target voltages increases, the interval between threshold voltage distributions of memory cells to be programmed to different program states decreases. Accordingly, in the present embodiment, a program operation for preventing an increase in the distribution width of threshold voltages is proposed.

[0066] Figure 7 is a graph illustrating a program operation according to an embodiment of the disclosure.

[0067] Referring to Figure 7 A program operation of a memory cell included in a selected page can be performed in an incremental step pulse programming (ISPP) method. The program operation of the ISPP method can increase a threshold voltage of a memory cell by performing a plurality of program loops. For example, each time a program loop is performed, a program voltage applied to a selected word line can be gradually increased. The threshold voltage of the memory cell can also be gradually increased by gradually increasing the program voltage.

[0068] As Figure 7 described below, a case where first to kth program loops LP1 to LPk are performed is described.

[0069] In the first programming cycle LP1, a sub-programming operation of applying a first program voltage 1Vpgm to the selected word line can be performed, and a verify operation for determining whether the threshold voltages of the memory cells connected to the selected word line are increased to target voltages can be performed. In the present embodiment, the verify operation using a first verify voltage 1Vf is defined as a first verify operation. In the sub-programming operation of the first programming cycle LP1, the lowest first program voltage 1Vpgm can be used; and in the first verify operation, the lowest first verify voltage 1Vf among the verify voltages applied to the selected word line can be used. During the sub-programming operation, the threshold voltages of the memory cells can be increased by the first program voltage 1Vpgm applied to the selected word line. Since the electrical characteristics of the memory cells can differ from each other, the memory cells whose threshold voltages are increased to the first target voltages and the memory cells whose threshold voltages are lower than the first target voltages can be distinguished when the first verify operation is performed. The voltage to be applied to the bit line for the next programming cycle can be set according to the sensing result of the first verify operation.

[0070] When the second programming cycle LP2 starts, a sub-programming operation using a second program voltage 2Vpgm higher than the first program voltage 1Vpgm can be performed. In the sub-programming operation, the voltage set in the first programming cycle LP1 can be applied to the bit line, and the second program voltage 2Vpgm can be applied to the selected word line. In the sub-programming operation performed from the second programming cycle LP2, a current-sensing check operation for determining whether the first verify operation performed in the first programming cycle LP1 as the previous cycle is passed or failed can be performed. For example, in the verify operation, the data of the memory cells can be sensed to distinguish the memory cells whose threshold voltages are increased to the target voltages and the memory cells whose threshold voltages are lower than the target voltages; and in the current-sensing check operation, it can be determined whether all of the threshold voltages of the selected memory cells reach the corresponding target voltages. Accordingly, the verify operation to be performed in the programming cycle can be determined according to the result of the current-sensing check operation. For example, in the current-sensing check operation performed during the sub-programming operation performed in the second programming cycle LP2, when it is determined that the first verify operation performed in the first programming cycle LP1 is failed, the first verify operation can be performed again in the second programming cycle LP2. In addition, after the first verify operation is performed, a second verify operation for determining a second program state can be sequentially performed. The second verify operation can be a verify operation using a second verify voltage 2Vf higher than the first verify voltage 1Vf, and can be performed to verify the memory cells to be programmed to the second program state higher than the first program state. In the second verify operation, the second program voltage 2Vpgm higher than the first program voltage 1Vpgm can be applied to the selected word line, and the second verify voltage 2Vf higher than the first verify voltage 1Vf can be applied to the selected word line. In the second verify operation, the threshold voltages of the memory cells can be increased by the second program voltage 2Vpgm applied to the selected word line. Since the electrical characteristics of the memory cells can differ from each other, the memory cells whose threshold voltages are increased to the second target voltages and the memory cells whose threshold voltages are lower than the second target voltages can be distinguished when the second verify operation is performed. The voltage to be applied to the bit line for the next programming cycle can be set according to the sensing result of the second verify operation. Figure 7In the illustrated drawing, the second verify operation starts from the second programming loop LP2. However, since this is an example of a programming operation for describing the ISPP method, the timing of the verify operation corresponding to each programming state can be different depending on the memory device.

[0071] When the first and second verify operations are also performed in the second programming loop LP2, the voltage to be applied to the bit line for the next programming loop can be set according to the results of the first and second verify operations.

[0072] When all the threshold voltages of the selected memory cells included in the selected page are increased to the target voltage in this method, the programming operation of the selected page can be ended. For example, when the result of the current sensing check operation for the nth verify operation performed in the kth programming loop LPk is determined to pass, the programming operation of the selected page can be ended.

[0073] Figure 8 is a drawing illustrating a programming operation of a dual programming method according to an embodiment of the disclosure.

[0074] Referring to Figure 8 In the dual programming method, two or more verify voltages Vs and Vt can be set for each target voltage PV, and the selected memory cell can be programmed until the threshold voltage 81 of the selected memory cell is higher than the target verify voltage Vt. In the present embodiment, a programming operation using a sub-verify voltage Vs and a target verify voltage Vt as verify voltages is described. The sub-verify voltage Vs can be set to a level lower than the target verify voltage Vt.

[0075] In the programming operation of the dual programming method, after the sub-verify operation using the sub-verify voltage Vs is performed, the main verify operation using the target verify voltage Vt can be performed. Accordingly, the selected memory cell can be included in the normal segment NRG in which the threshold voltage is lower than the sub-verify voltage Vs, the slow segment SRG in which the threshold voltage is between the sub-verify voltage Vs and the target verify voltage Vt, and the final segment FRG in which the threshold voltage is equal to or higher than the target verify voltage Vt.

[0076] Since the normal segment NRG is a segment in which the difference between the threshold voltage of the memory cell and the target verify voltage Vt is large, in the sub-programming operation, the program enable voltage can be applied to the bit line connected to the memory cell included in the normal segment NRG.

[0077] Since the slow segment SRG is a segment in which the difference between the threshold voltage of the memory cell and the target verify voltage Vt is relatively smaller than the difference between the threshold voltage of the memory cell and the target verify voltage Vt included in the normal segment NRG, a program lowering voltage higher than the program enable voltage can be applied to the bit line connected to the memory cell included in the slow segment SRG during the sub-programming operation.

[0078] Since the fast segment FRG is a segment in which the threshold voltage of the memory cell is higher than the target verify voltage Vt, a program inhibit voltage higher than the program lowering voltage can be applied to the bit line connected to the memory cell included in the fast segment FRG during the sub-programming operation.

[0079] In the above-described segments, in the slow segment SRG, since the program lowering voltage higher than the program enable voltage is applied to the bit line, the threshold voltage of the memory cell can be increased with a voltage difference smaller than the voltage difference of the threshold voltage of the memory cell included in the normal segment NRG. For example, in the case where the same program voltage is applied to the memory cell included in each segment of the normal segment NRG and the slow segment SRG, when the threshold voltage of the memory cell included in the normal segment NRG is increased by a first level 1L, the threshold voltage of the memory cell included in the slow segment SRG can be increased by a second level 2L lower than the first level 1L.

[0080] In the slow segment SRG, since the increase of the threshold voltage of the memory cell is slower than that in the normal segment NRG, as the number of the memory cells included in the slow segment SRG increases, the time required for the program operation can increase. Therefore, in the present embodiment, the number of times of the program operation of the double program method in which the program lowering voltage is applied to the bit line of the memory cell included in the slow segment SRG can be changed according to the condition of the program operation.

[0081] In the operation in which the double program method is not applied, the normal program method can be applied.

[0082] The program cycle performed in the program operation will be described in more detail below.

[0083] Figure 9 is a diagram illustrating a program cycle according to an embodiment of the present disclosure.

[0084] Referring to Figure 9As an example, the (k-4)th program loop LP(k-4) and the (k-3)th program loop LP(k-3) are shown. In the (k-4)th program loop LP(k-4), a sub-program operation in which the (k-4)th program voltage (k-4)Vpgm is applied to the selected word line can be performed. Subsequently, the (n-2)th and (n-1)th verify operations using the (n-2)th and (n-1)th verify voltages (n-2)Vf and (n-1)Vf, respectively, can be sequentially performed. During the sub-program operation of the (k-4)th program loop LP(k-4), a current-sense check CSC operation for determining the result of each verify operation performed in the previous program loop can be performed. When it is determined that both the (n-2)th and (n-1)th verify operations fail due to the current-sense check CSC operation, the (n-2)th and (n-1)th verify operations can be performed in the (k-4)th program loop LP(k-4). After the (n-2)th and (n-1)th verify operations are performed, a bit line set operation BLS for the next program loop can be performed according to the results of the (n-2)th and (n-1)th verify operations. For example, the bit line to which the program enable voltage, the program down voltage, and the program inhibit voltage are applied can be selected.

[0085] When the (k-3)th program loop LP(k-3) starts, a sub-program operation can be performed. During the sub-program operation, the voltage set in the (k-4)th program loop LP(k-4) can be applied to the bit line, and the (k-3)th program voltage (k-3)Vpgm higher than the (k-4)th program voltage (k-4)Vpgm can be applied to the selected word line. During the sub-program operation, a current-sense check CSC operation for each of the (n-2)th and (n-1)th verify operations performed in the (k-4)th program loop LP(k-4) can be performed. For example, when the (n-2)th verify operation using the (n-2)th verify voltage (n-2)Vf passes and the (n-1)th verify operation using the (n-1)th voltage (n-1)Vf fails, the (n-2)th verify operation can be omitted, and the (n-1)th verify operation and the nth verify operation can be performed from the (k-3)th program loop LP(k-3). The nth verify operation can be an operation using the nth verify voltage nVf. After the (n-1)th verify operation and the nth verify operation are performed, a bit line set operation BLS can be performed according to the sensing results of the (n-1)th verify operation and the nth verify operation.

[0086] Figure 10A and Figure 10B is a diagram illustrating a method of applying a voltage to a bit line according to an embodiment of the disclosure. Figure 10A illustrates a voltage applied to a bit line in a double program DPGM, while Figure 10BA voltage applied to a bit line in a normal programming operation NPGM is illustrated.

[0087] Referring to Figure 10A During a sub-programming operation in which the double programming DPGM method is applied, a program enable voltage Val, a program down voltage Vde, and a program inhibit voltage Vin can be selectively applied to a bit line. For example, assuming that memory cells connected to the first and second page buffers PB1 and PB2 are memory cells included in the normal segment NRG, memory cells connected to the third and fifth page buffers PB3 and PB5 are memory cells included in the slow segment SRG, and memory cells connected to the fourth and jth page buffers PB4 and PBj are memory cells included in the footer segment FRG.

[0088] The program enable voltage Val can be applied to a bit line connected to a memory cell included in the normal segment NRG, the program down voltage Vde can be applied to a bit line connected to a memory cell included in the slow segment SRG, and the program inhibit voltage Vin can be applied to a bit line connected to a memory cell included in the footer segment FRG.

[0089] Referring to Figure 10B During a sub-programming operation in which the normal programming NPGM method is applied, a program enable voltage Val and a program inhibit voltage Vin can be selectively applied to a bit line. For example, when the double programming DPGM method is applied as shown in Figure 10A and the normal programming NPGM method is applied as shown in Figure 10B a program enable voltage Val can be applied to a bit line connected to a memory cell included in the slow segment SRG.

[0090] In the present embodiment, the number of times the double programming DPGM is applied can be adjusted according to a program operation. Thus, a program operation time can be shortened, and a threshold voltage distribution of memory cells can be improved.

[0091] Figure 11 is a diagram illustrating a program operation according to a first embodiment of the present disclosure.

[0092] Referring to Figure 11 In the first embodiment, the maximum number of times MAXn the double programming DPGM is applied can be determined according to a program voltage Vpgm. When the program voltage Vpgm is equal to or lower than a reference level, the maximum number of times MAXn the double programming DPGM is applied can be set to be small; and when the program voltage Vpgm is higher than the reference level, the maximum number of times MAXn the double programming DPGM is applied can be set to be large. Here, one or more reference levels can be set.

[0093] For example, when the reference level is set to the E-th programming voltage EVpgm and the F-th programming voltage FVpgm, the maximum number MAXn of double programming DPGM can be set to L times in a programming cycle using the programming voltages from the first programming voltage 1Vpgm, which is the lowest voltage, to the E-th programming voltage EVpgm. The maximum number MAXn of double programming DPGM can be set to M times, which is more than L times, in a programming cycle using the programming voltages from the (E+1)-th programming voltage (E+1)Vpgm to the F-th programming voltage FVpgm as the voltage levels. The maximum number MAXn of double programming DPGM can be set to N times, which is more than M times, in a programming cycle using the programming voltages from the (F+1)-th programming voltage (F+1)Vpgm to the G-th programming voltage GVpgm as the voltage levels. Thus, the (E+1)-th programming voltage (E+1)Vpgm is higher than the E-th programming voltage EVpgm, and the (F+1)-th programming voltage (F+1)Vpgm is higher than the F-th programming voltage FVpgm. F is a positive integer larger than E, and G is a positive integer larger than F. M is a positive integer larger than L, and N is a positive integer larger than M. The values set according to the first embodiment can be stored in the control logic circuit 160 of Figure 2 , and the control logic circuit 160 can control the programming cycle to which double programming DPGM is applied according to the stored set values.

[0094] The programming operation to which the first embodiment is applied is specifically described below.

[0095] Figure 12 is a diagram illustrating a programming cycle of a programming operation performed according to the first embodiment of the present disclosure.

[0096] Referring to Figure 12When the first to twelfth programming loops LP1 to LP12 are executed in the programming operation on the selected page, the maximum number MAXn of double programming DPGM can be set to 1 in the first to fourth programming loops LP1 to LP4 having relatively low voltage levels; the maximum number MAXn of double programming DPGM can be set to 2 in the fifth to eighth programming loops LP5 to LP8 having intermediate voltage levels; and the maximum number MAXn of double programming DPGM can be set to 3 in the ninth to twelfth programming loops LP9 to LP12 having relatively high voltage levels. In other words, in the programming loops in which the programming voltage within the first voltage difference 1Vdiff from the first programming voltage 1Vpgm having the lowest voltage level is applied, the maximum number MAXn of double programming DPGM can be set to 1; in the programming loops in which the programming voltage between the first voltage difference 1Vdiff and the second voltage difference 2Vdiff from the first programming voltage 1Vpgm having the lowest voltage level is applied, the maximum number MAXn of double programming DPGM can be set to 2; and in the programming loops in which the programming voltage between the second voltage difference 2Vdiff and the third voltage difference 3Vdiff from the first programming voltage 1Vpgm having the lowest voltage level is applied, the maximum number MAXn of double programming DPGM can be set to 3. That is, in the case where the number of double programming DPGM applied when the level of the programming voltage is low is increased, the programming operation time is correspondingly increased. Therefore, in the first embodiment, the maximum number MAXn of double programming DPGM can be reduced when the level of the programming voltage is low, and the maximum number MAXn of double programming DPGM can be increased as the level of the programming voltage is increased, so that the distribution of threshold voltages is not widened.

[0097] The embodiment in which the maximum number MAXn of double programming DPGM is determined is described more specifically below.

[0098] Figure 13A and Figure 13B is a diagram illustrating the sub-programming operation according to the maximum number of double programming during the programming operation according to the first embodiment of the present disclosure.

[0099] Referring to Figure 13AWhen the maximum number of double programming MAXn is set to one in the first to fourth programming loops LP1 to LP4, the double programming DPGM operation corresponding to each verify operation using different verify voltages can be performed at most once. For example, when the first to fourth programming loops LP1 to LP4 are performed, the double programming DPGM reflecting the sensing result of the first verify operation 1OPv can be set to be performed in the second programming loop LP2, and not performed in the remaining first, third, and fourth programming loops LP1, LP3, and LP4. When the first to fourth programming loops LP1 to LP4 are performed, the double programming DPGM reflecting the sensing result of the second verify operation 2OPv can be set to be performed in the second programming loop LP2, and not performed in the remaining first, third, and fourth programming loops LP1, LP3, and LP4. When the first to fourth programming loops LP1 to LP4 are performed, the double programming DPGM reflecting the sensing result of the third verify operation 3OPv can be set to be performed in the third programming loop LP3, and not performed in the remaining first, second, and fourth programming loops LP1, LP2, and LP4. When the first to fourth programming loops LP1 to LP4 are performed, the double programming DPGM reflecting the sensing result of the fourth verify operation 4OPv can be set to be performed in the fourth programming loop LP4, and not performed in the remaining first to third programming loops LP1 to LP3.

[0100] More specifically, it is assumed that the first sub-programming operation 1Ops using the first program voltage 1Vpgm, the first verify operation 1OPv using the first verify voltage 1Vf, and the second verify operation 2OPv using the second verify voltage 2Vf are performed in the first programming loop LP1, and the second sub-programming operation 2Ops using the second program voltage 2Vpgm, the first verify operation 1OPv using the first verify voltage 1Vf, the second verify operation 2OPv using the second verify voltage 2Vf, and the third verify operation 3OPv using the third verify voltage 3Vf are sequentially performed in the second programming loop LP2.

[0101] The voltage applied to the bit line during the second sub-programming operation 2OPs can be set according to the sensing results of the first verify operation 1OPv and the second verify operation 2OPv performed in the first programming loop LP1, and the set voltage can be applied to the bit line during the second sub-programming operation 2OPs of the second programming loop LP2. When double programming DPGM is applied to the second sub-programming operation 2Ops, the double programming DPGM according to the sensing result of the first verify operation 1OPv and the double programming DPGM according to the sensing result of the second verify operation 2OPv can be applied once, respectively.

[0102] Since the double programming DPGM corresponding to the first verify operation 1OPv is applied in the second programming loop LP2, the double programming DPGM corresponding to the first verify operation 1OPv is not applied even if the first verify operation 1OPv is performed in the remaining third and fourth programming loops LP3 and LP4.

[0103] Since the double programming DPGM corresponding to the second verify operation 2OPv is applied in the second programming loop LP2, the double programming DPGM corresponding to the second verify operation 2OPv is not applied even if the second verify operation 2OPv is performed in the remaining third and fourth programming loops LP3 and LP4.

[0104] When the first to third verify operations 1OPv to 3OPv using the first to third verify voltages 1Vf to 3Vf are performed in the second programming loop LP2, the memory cells on which the first to third verify operations 1OPv to 3OPv are performed become targets of the double programming DPGM in the third programming loop LP3. However, in the present embodiment, since the double programming DPGM corresponding to each of the first verify operation 1OPv and the second verify operation 2OPv has been applied once (which is the maximum number MAXn) in the second programming loop LP2, in the third programming loop LP3, the double programming DPGM corresponding to the first verify operation 1OPv and the second verify operation 2OPv can not be applied, and only the double programming DPGM corresponding to the third verify operation 3OPv can be applied.

[0105] When the second to fourth verify operations 2OPv to 4OPv using the second to fourth verify voltages 2Vf to 4Vf, respectively, are performed in the third programming loop LP3, the memory cells on which the second to fourth verify operations 2OPv to 4OPv are performed become targets of the double programming DPGM in the fourth programming loop LP4. However, in the present embodiment, since the double programming DPGM corresponding to each of the second and third verify operations 2OPv and 3OPv has been applied once (which is the maximum number MAXn) in the previous loops, in the fourth programming loop LP4, only the double programming DPGM corresponding to the fourth verify operation 4OPv can be applied.

[0106] Figure 13B A case in which the maximum number MAXn of double programming is set to twice in the first to fourth programming loops LP1 to LP4 is illustrated.

[0107] Referring to Figure 13BIn the case of the embodiment illustrated in FIG. 6, since the first verification operation 1OPv is performed only in the first programming loop LP1, the first verification operation 1OPv can be applied only once in the second programming loop LP2. That is, when the maximum number of times MAXn of the double programming DPGM is set to two times, the double programming DPGM corresponding to each verification operation can be applied once or twice. Figure 13B

[0108] Figure 14 is a diagram illustrating a programming operation according to a second embodiment of the present disclosure.

[0109] Referring to Figure 14 In the second embodiment, the maximum number of times MAXn of the double programming DPGM can be determined according to a step voltage Vst. Here, the step voltage Vst refers to an increase amount of a programming voltage that is gradually increased each time a programming loop is performed. For example, in a programming operation in which an A step voltage A Vst is provided, the maximum number of times MAXn of the double programming DPGM can be set to L times; in a programming operation in which a B step voltage B Vst higher than the A step voltage A Vst is provided, the maximum number of times MAXn of the double programming DPGM can be set to M times greater than L times; and in a programming operation in which a C step voltage C Vst higher than the B step voltage B Vst is provided, the maximum number of times MAXn of the double programming DPGM can be set to N times greater than M times. Here, L, M, and N can be different positive integers.

[0110] That is, the maximum number of times MAXn of the double programming DPGM used in the programming operation can be proportional to the level of the step voltage. The programming operation to which the second embodiment is applied is specifically described below. Figure 15A to Figure 15C is a diagram illustrating a programming loop of a programming operation performed according to the second embodiment of the present disclosure.

[0111] Referring to Figure 15A ​In the programming operation in which the programming voltage is gradually increased by a constant A-step voltage AVst, it is assumed that the maximum number of double programming DPGM is L times. In the programming cycles LP1 to LP12,... performed in this programming operation, since the maximum number of double programming DPGM is limited to L times, the double programming DPGM can be performed even less than L times depending on the programming cycle.

[0112] Referring to Figure 15B In the programming operation in which the programming voltage is gradually increased by a constant A-step voltage AVst, it is assumed that the maximum number of double programming DPGM is L times. In the programming cycles LP1 to LP12,... performed in this programming operation, since the maximum number of double programming DPGM is limited to L times, the double programming DPGM can be performed even less than L times depending on the programming cycle.

[0113] Referring to Figure 15C In the programming operation in which the programming voltage is gradually increased by a constant A-step voltage AVst, it is assumed that the maximum number of double programming DPGM is L times. In the programming cycles LP1 to LP12,... performed in this programming operation, since the maximum number of double programming DPGM is limited to L times, the double programming DPGM can be performed even less than L times depending on the programming cycle.

[0114] Figure 16 is a diagram illustrating a programming operation according to a third embodiment of the present disclosure.

[0115] Referring to Figure 16 In the third embodiment, the maximum number of double programming DPGM can be determined according to a segmentation RG of the programming cycle. Here, the segmentation RG refers to segmentation according to the order of the programming cycle. For example, a first segmentation 1RG can correspond to an initial period of the programming operation, a second segmentation 2RG can correspond to an intermediate period of the programming operation, and a third segmentation 3RG can correspond to a late period of the programming operation.

[0116] In the programming cycles performed in the first segmentation 1RG, the maximum number of double programming DPGM can be set to L times; in the programming cycles performed in the second segmentation 2RG, the maximum number of double programming DPGM can be set to M times; and in the programming cycles performed in the third segmentation 3RG, the maximum number of double programming DPGM can be set to N times. Here, M can be a positive integer greater than L, and N can be a positive integer greater than M.

[0117] That is, since there are many memory cells in the erased state in the initial period of the programming operation, the number of times of applying double programming DPGM, which slowly increases the threshold voltage of the memory cell, can be set to be smaller than that of the other segments so as to quickly increase the threshold voltage of the memory cell. Since the threshold voltage of the memory cell is increased to be close to the target voltage in the later period of the programming operation, the number of times of applying double programming DPGM can be set to be larger than that of the other segments so as to slowly increase the threshold voltage of the memory cell.

[0118] The programming operation to which the third embodiment is applied is specifically described below.

[0119] Figure 17 is a diagram illustrating a programming cycle of a programming operation performed according to the third embodiment of the present disclosure.

[0120] Referring to Figure 17 When the first to twelfth programming cycles LP1 to LP12 are executed in the programming operation on the selected page, the first to fourth programming cycles LP1 to LP4 can be executed in the first segment 1RG, which is the initial period of the programming operation, the fifth to eighth programming cycles LP5 to LP8 can be executed in the second segment 2RG, which is the middle period of the programming operation, and the ninth to twelfth programming cycles LP9 to LP12 can be executed in the third segment 3RG, which is the later period of the programming operation. In the first to fourth programming cycles LP1 to LP4 executed in the first segment 1RG, the maximum number of double programming DPGM can be set to 1; in the fifth to eighth programming cycles LP5 to LP8 executed in the second segment 2RG, the maximum number of double programming DPGM can be set to 2; and in the ninth to twelfth programming cycles LP9 to LP12 executed in the third segment 3RG, the maximum number of double programming DPGM can be set to 2. In other words, in the programming cycle in which there are relatively many memory cells in the erased state, the maximum number MAXn of double programming DPGM can be set to be small, and in the programming cycle in which there are relatively few memory cells in the erased state, the maximum number MAXn of double programming DPGM can be set to be large.

[0121] In addition, since there are many memory cells in the erased state in the first segment 1RG, the programming voltage can be set to be gradually increased by a first step voltage 1Vst. Since the number of memory cells in the erased state in the second segment 2RG is smaller than the number of memory cells in the erased state in the first segment 1RG, the programming voltage can be set to be gradually increased by a second step voltage 2Vst which is lower than the first step voltage 1Vst. Since the number of memory cells in the erased state in the third segment 3RG is smaller than the number of memory cells in the erased state in the second segment 2RG, the programming voltage can be set to be gradually increased by a third step voltage 3Vst which is lower than the second step voltage 2Vst. That is, the slope GDR of the increase in the programming voltage can be determined in accordance with the step voltage Vst, and the maximum number of double programming DPGM can be changed in accordance with the slope GDR of the programming voltage.

[0122] Figure 18A and Figure 18B is a diagram illustrating a programming operation according to a fourth embodiment of the present disclosure.

[0123] Referring to Figure 18A and Figure 18B In the fourth embodiment, the maximum number of double programming DPGM can be set differently in accordance with the target voltage PV. For example, when the target voltage PV is equal to or lower than a reference level, the maximum number of double programming DPGM applied MAXn can be set to be small; and when the target voltage PV is higher than the reference level, the maximum number of double programming DPGM applied MAXn can be set to be large. Here, one or more reference levels can be set. Alternatively, as the level of the target voltage decreases, the maximum number of double programming DPGM applied MAXn can be set to be small; and as the level of the target voltage increases, the maximum number of double programming DPGM applied MAXn can be set to be large. For example, assuming that the fourth target voltage PV4 is a reference level, during the programming operation of the first to fourth target voltages PV1 to PV4, the maximum number of double programming DPGM MAXn can be set to L times; and during the programming operation of the fifth to seventh target voltages PV5 to PV7, the maximum number of double programming DPGM MAXn can be set to N times which is larger than L times (refer to Figure 18A ).

[0124] Alternatively, assuming that the first, third, and fifth target voltages PV1, PV3, and PV5 are reference levels, the maximum number MAXn of double programming DPGM can be set to L times during the programming operation of the first target voltage PV1; the maximum number MAXn of double programming DPGM can be set to M times, which is greater than L times, during the programming operation of the second and third target voltages PV2 and PV3; the maximum number MAXn of double programming DPGM can be set to N times, which is greater than M times, during the programming operation of the fourth and fifth target voltages PV4 and PV5; and the maximum number MAXn of double programming DPGM can be set to P times, which is greater than N times, during the programming operation of the sixth and seventh target voltages PV6 and PV7 (see Figure 18B ).

[0125] The above first to third embodiments can be selectively applied during the programming operation, or they can be mixed and applied, and various changes can be made to the maximum number MAXn of double programming DPGM in addition to the above embodiments.

[0126] Figure 19 is a diagram illustrating a memory card system to which a memory device of the present disclosure is applied.

[0127] Referring to Figure 19 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0128] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 can be configured to control a programming, reading, or erasing operation of the memory device 2200, or to control a background operation. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory device 2200 can be configured the same as the memory device MD described with reference to Figure 2 .

[0129] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the various communication standards described above.

[0130] For example, the memory device 2200 can be constituted by various nonvolatile memory devices such as Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase-Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0131] The memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash card (CF), a Smart Media card (SM or SMC), a memory stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Storage (UFS).

[0132] Figure 20 is a diagram illustrating a solid state drive (SSD) system to which a memory device of the disclosure is applied.

[0133] Referring to Figure 20 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 through 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0134] According to an embodiment of the disclosure, the flash memories 3221 through 322n can be configured to be the same as the memory device MD described with reference to FIG. 1. Figure 2

[0135] The SSD controller 3210 can control the plurality of flash memories 3221 through 322n in response to a signal received from the host 3100. For example, the signal can be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal can be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0136] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply 3230 can receive power from the host 3100 and can be charged. The auxiliary power supply 3230 can supply power of the SSD 3200 when the power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 can be positioned in the SSD 3200 or can be positioned outside the SSD 3200. For example, the auxiliary power supply 3230 can be positioned on a main board and can supply auxiliary power to the SSD 3200.

[0137] The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 through 322n, or can temporarily store metadata (for example, a mapping table) of the flash memories 3221 through 322n. The buffer memory 3240 can include a volatile memory such as a DRAM, a SDRAM, a DDR SDRAM, and a LPDDR SDRAM, or a non-volatile memory such as an FRAM, a ReRAM, an STT-MRAM, and a PRAM.​

Claims

1. A memory device comprising: a memory block comprising memory cells; a peripheral circuit performing a plurality of program loops to cause a threshold voltage of a selected memory cell included in a selected page in the memory cells to reach a target voltage; and a control logic circuit controlling the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops and changing a maximum number of times the double program is applied according to an operating condition of the program loops, wherein the operating condition comprises at least one of: a program voltage, a step voltage, a segmentation of the program loops, and a target voltage, wherein the normal program increases the threshold voltage of the selected memory cell by a first change amount, wherein the double program increases the threshold voltage by a second change amount, the second change amount being lower than the first change amount, and wherein the peripheral circuit comprises: a voltage generator generating a program voltage or a verify voltage to be applied to a selected word line connected to the selected memory cell; and a page buffer sensing the threshold voltage of the selected memory cell through a bit line connected to the memory cell and applying a program enable voltage, a program down voltage, or a program inhibit voltage to the bit line according to the sensed data, wherein in the program loops to which the double program is applied, the program inhibit voltage is applied to a bit line connected to a memory cell whose threshold voltage is higher than the target voltage, the program down voltage is applied to a bit line connected to a memory cell whose threshold voltage is between the target voltage and a sub-verify voltage, the sub-verify voltage being lower than the target voltage, and the program enable voltage is applied to a bit line connected to a memory cell whose threshold voltage is lower than the sub-verify voltage.

2. The memory device of claim 1, wherein the program down voltage is set higher than the program enable voltage, and the program inhibit voltage is set higher than the program down voltage.

3. The memory device of claim 2, wherein in the program loops to which the normal program is applied, the program inhibit voltage is applied to a bit line connected to a memory cell whose threshold voltage is higher than the target voltage, and the program enable voltage is applied to a bit line connected to a memory cell whose threshold voltage is lower than the target voltage.

4. The memory device of claim 1, wherein the control logic circuit changes the maximum number of times the double program is used according to the program voltage applied to a selected word line connected to the selected memory cell among the operating conditions of the program loops. ​ 5. The memory device of claim 4, wherein the control logic circuit reduces the maximum number of times the double programming is used in the program cycle in which the program voltage is at or below a reference level, and increases the maximum number of times the double programming is used in the program cycle in which the program voltage is greater than the reference level.

6. The memory device of claim 1, wherein the control logic circuit varies the maximum number of times the double programming is used as a function of a step voltage, the step voltage being an amount of change in a program voltage applied to a selected word line connected to the selected memory cell in the operating conditions of the program cycle.

7. The memory device of claim 6, wherein the control logic circuit increases the maximum number of times the double programming is used in the program cycle in which the step voltage is relatively high, and reduces the maximum number of times the double programming is used in the program cycle in which the step voltage is relatively low.

8. The memory device of claim 1, wherein the control logic circuit varies the maximum number of times the double programming is used as a function of the target voltage of the selected memory cell in the operating conditions of the program cycle.

9. The memory device of claim 8, wherein the control logic circuit reduces the maximum number of times the double programming is used in the program cycle in which the target voltage is at or below a reference level, and increases the maximum number of times the double programming is used in the program cycle in which the target voltage is greater than the reference level.

10. A method of operating a memory device, the method comprising: performing a plurality of program cycles to program a selected memory cell connected to a selected word line by applying an increasing program voltage to the selected word line, wherein a maximum number of times double programming is used to increase a threshold voltage between a target voltage and a sub-verify voltage, the sub-verify voltage being lower than the target voltage, is set to a first number when the program voltage is at or below a reference level, and the maximum number is set to a second number when the program voltage is above the reference level, the second number being greater than the first number.

11. The method of claim 10, wherein each program cycle of the plurality of program cycles comprises: applying a program enable voltage, a program down voltage, or a program inhibit voltage to a bit line connected to the selected memory cell; applying the program voltage to the selected word line; and verifying the threshold voltage of the selected memory cell.

12. The method of claim 11, wherein the program enable voltage, the program down voltage, or the program inhibit voltage is applied to the bit line when the double programming is used, and the program enable voltage or the program inhibit voltage is applied to the bit line when the double programming is not used. ​ 13. The method of claim 12, wherein when the double programming is used, the program inhibit voltage is applied to bit lines connected to memory cells whose threshold voltages are higher than the target voltage, the program step down voltage is applied to bit lines connected to memory cells whose threshold voltages are between the sub verify voltage and the target voltage, and the program enable voltage is applied to bit lines connected to memory cells whose threshold voltages are lower than the sub verify voltage.

14. The method of claim 12, wherein when the double programming is not used, the program inhibit voltage is applied to bit lines connected to memory cells whose threshold voltages are higher than the target voltage, and the program enable voltage is applied to bit lines connected to memory cells whose threshold voltages are lower than the target voltage.

15. A method of operating a memory device, the method comprising: performing a program operation on a selected memory cell connected to a selected word line by applying an increasing program voltage to the selected word line, wherein in an initial period of the program operation, a maximum number of times that double programming is used to increase a threshold voltage between a target voltage and a sub verify voltage, the sub verify voltage being lower than the target voltage, is set to a first number, and as the program operation progresses, the maximum number is increased to a second number, the second number being greater than the first number.

16. The method of claim 15, wherein each program cycle of a plurality of program cycles comprises: applying a program enable voltage, a program step down voltage, or a program inhibit voltage to a bit line connected to the selected memory cell; applying the program voltage to the selected word line; and verifying the threshold voltage of the selected memory cell.

17. The method of claim 16, wherein when the double programming is used, the program enable voltage, the program step down voltage, or the program inhibit voltage is applied to the bit line, and when the double programming is not used, the program enable voltage or the program inhibit voltage is applied to the bit line.

18. The method of claim 17, wherein when the double programming is used, the program inhibit voltage is applied to bit lines connected to memory cells whose threshold voltages are higher than the target voltage, the program step down voltage is applied to bit lines connected to memory cells whose threshold voltages are between the sub verify voltage and the target voltage, and the program enable voltage is applied to bit lines connected to memory cells whose threshold voltages are lower than the sub verify voltage.

19. The method of claim 17, wherein when the double programming is not used, the program inhibit voltage is applied to bit lines connected to memory cells whose threshold voltages are higher than the target voltage, and the program enable voltage is applied to bit lines connected to memory cells whose threshold voltages are lower than the target voltage.

20. A method of operating a memory device, the method comprising: performing a plurality of program loops of programming a selected memory cell connected to a selected word line by applying an increasing program voltage to the selected word line, wherein a maximum number of times a double program is used for increasing a threshold voltage between a target voltage and a sub-verify voltage slower than a reference, the sub-verify voltage being lower than the target voltage, is set to a first number when the target voltage of the memory cell is equal to or lower than a reference level, and the maximum number of times is set to a second number greater than the first number when the target voltage of the memory cell is higher than the reference level.

21. The method of claim 20, wherein each program loop of the plurality of program loops comprises: applying a program enable voltage, a program down voltage, or a program inhibit voltage to a bit line connected to the selected memory cell; applying the program voltage to the selected word line; and verifying the threshold voltage of the selected memory cell.

22. The method of claim 21, wherein when the double program is used, the program enable voltage, the program down voltage, or the program inhibit voltage is applied to the bit line, and when the double program is not used, the program enable voltage or the program inhibit voltage is applied to the bit line.

23. The method of claim 22, wherein when the double program is used, the program inhibit voltage is applied to bit lines connected to memory cells whose threshold voltages are higher than the target voltage, the program down voltage is applied to bit lines connected to memory cells whose threshold voltages are between the sub-verify voltage and the target voltage, and the program enable voltage is applied to bit lines connected to memory cells whose threshold voltages are lower than the sub-verify voltage.

24. The method of claim 22, wherein when the double program is not used, the program inhibit voltage is applied to bit lines connected to memory cells whose threshold voltages are higher than the target voltage, and the program enable voltage is applied to bit lines connected to memory cells whose threshold voltages are lower than the target voltage. ​

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