Super junction device structure and method of fabricating the same

Abstract

The application discloses a super-junction device structure and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate of a first conductive type; epitaxially growing an epitaxial layer of the first conductive type on the semiconductor substrate; forming a column structure of a second conductive type in the epitaxial layer, and the column structure extends along the thickness direction of the epitaxial layer; performing first ion implantation on the top of the column structure to form an ion layer structure, performing second ion implantation from the top of the ion layer structure, forming a body contact region at the lower part of the ion layer structure, and forming a gate oxide layer on the upper surface of the epitaxial layer; forming a polysilicon gate on the upper surface of the gate oxide layer; forming a source region in the body contact region through an ion implantation process; and forming an interlayer dielectric layer on the surface and sidewall of the polysilicon gate. The application can effectively eliminate the phenomenon that the mutual diffusion of the doping ions of the body contact region and the epitaxial layer in the thermal propulsion drive process when the body contact region is formed, causes the unbalanced charge distribution, and thus improves the withstand voltage performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super-junction device structure and a preparation method thereof. BACKGROUND

[0002] In the prior art, a preparation method of a super-junction device structure is introduced by taking an NPN type super-junction device structure as an example. The method comprises the following steps:

[0003] (1) Firstly, deep trench etching is performed on an epitaxial layer (N- -EPI) of a semiconductor substrate (N+ -Sub), and an epitaxial filling process is performed inside the trench to form a P-type pillar structure (P-pillar), as shown in FIG. 1. Figure 1

[0004] (2) Then, a gate oxide layer is made, polycrystalline silicon (Polysilicon) is deposited, and polycrystalline silicon etching is completed to form a polysilicon gate, as shown in FIG. 2. Figure 2

[0005] (3) A P-type body contact region (P-body region) and an N+ source region are formed by implantation and diffusion, as shown in FIG. 3. Figure 3

[0006] (4) An interlayer dielectric layer is formed on the surface and sidewall of the polysilicon gate, and a front metal electrode is formed on the surface of the P-type body contact region, the N+ source region and the interlayer dielectric layer, as shown in FIG. 4. Figure 4

[0007] The super-junction device structure formed by the above preparation method has the advantage that: since the alternating P-type and N-type structure regions are formed in the body region of the device, the super-junction device structure can not only vertically distribute the depletion, but also support the lateral depletion, so that the super-junction device structure can better withstand the voltage.

[0008] However, the preparation method of the super-junction device structure has the following disadvantages:

[0009] I. Since the super-junction device structure has the problem of uneven heat diffusion, the carriers in the P-type region and the N-type region in the body region will diffuse with each other, which will cause the phenomenon of unbalanced charge distribution, thereby reducing the voltage resistance of the super-junction device structure.

[0010] ​​​​II. In the above preparation process, because the ion concentration in the formation of the P-type column structure is higher than the ion concentration of the P-type body contact region, in order to consider the opening voltage of the super junction device structure, it is necessary to ensure that the distance between each P-type column structure is not too close, so as to provide enough space for the high temperature diffusion of the P-type body contact region. Therefore, the size of the super junction device structure formed by the above preparation method cannot be too small, which cannot meet the requirement of reducing the size of the device, and the product competitiveness is low. SUMMARY

[0011] Therefore, it is necessary to provide a super junction device structure and a preparation method thereof to solve the problem of reduced withstand voltage of the super junction device structure prepared by the existing method.

[0012] In order to achieve the above purpose, a preparation method of a super junction device structure comprises the following steps:

[0013] providing a semiconductor substrate of a first conductivity type;

[0014] epitaxially growing an epitaxial layer of the first conductivity type on the semiconductor substrate;

[0015] forming a column structure of a second conductivity type in the epitaxial layer, and the column structure extends along the thickness direction of the epitaxial layer;

[0016] performing a first ion implantation on the top of the column structure to form an ion layer structure to reduce the doping concentration of the surface of the column structure; the ion type of the first ion implantation is the first conductivity type;

[0017] performing a second ion implantation from the top of the ion layer structure to form a body contact region in the lower part of the ion layer structure, and the ion type of the second ion implantation is the second conductivity type;

[0018] forming a gate oxide layer on the upper surface of the epitaxial layer;

[0019] forming a polysilicon gate on the upper surface of the gate oxide layer;

[0020] forming a source region in the body contact region by an ion implantation process;

[0021] forming an interlayer dielectric layer on the surface and sidewall of the polysilicon gate.

[0022] Optionally, the width of the body contact region formed by the second ion implantation is the same as the width of the column structure.

[0023] Optionally, the width of each column structure formed in the epitaxial layer is greater than 5um, and the distance between any two column structures is less than 4um.

[0024] Optionally, the ion concentration range for the first ion implantation is 2*10 16 / cm 3.

[0025] Optionally, the height of the source region is greater than the height of the ion layer structure, and the height of the source region is less than the height of the body contact region.

[0026] Based on the above purpose, a super-junction device structure comprises:

[0027] a semiconductor substrate of a first conductivity type;

[0028] an epitaxial layer of a first conductivity type on the upper surface of the semiconductor substrate;

[0029] a column structure of a second conductivity type in the epitaxial layer and extending along the thickness direction of the epitaxial layer;

[0030] an ion layer structure on the top of the column structure, the ion layer structure being formed by a first ion implantation on the top of the column structure; the ion type implanted in the ion layer structure is of a first conductivity type;

[0031] a body contact region in the lower part of the ion layer structure, the body contact region being formed by a second ion implantation on the upper part of the ion layer structure; the ion type implanted in the body contact region is of a second conductivity type;

[0032] a gate oxide layer on the upper surface of the epitaxial layer;

[0033] a polysilicon gate on the upper surface of the gate oxide layer;

[0034] a source region in the body contact region;

[0035] an interlayer dielectric layer on the surface and sidewall of the polysilicon gate.

[0036] Optionally, the width of the body contact region is the same as the width of the column structure.

[0037] Optionally, the width of each column structure formed in the epitaxial layer is greater than 5um, and the spacing between any two column structures is less than 4um.

[0038] Optionally, the ion concentration range for the first ion implantation is 2*10 16 / cm 3.

[0039] Optionally, the height of the source region is greater than the height of the ion layer structure, and the height of the source region is less than the height of the body contact region.

[0040] The above technical solution has the following beneficial effects:

[0041] The super junction device structure and the preparation method thereof of the present application can effectively eliminate the phenomenon of charge distribution imbalance caused by the mutual diffusion of the doping ions of the body contact region and the epitaxial layer in the thermal propulsion driving process when forming the body contact region, thereby improving the voltage resistance performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0043] Figure 1 is a semiconductor substrate, an epitaxial layer and a column structure diagram of an NPN type super junction device structure provided in the prior art;

[0044] Figure 2 is a gate oxide layer and a polysilicon gate structure diagram of an NPN type super junction device structure provided in the prior art;

[0045] Figure 3 is a body contact region and a source region structure diagram of an NPN type super junction device structure provided in the prior art;

[0046] Figure 4 is an interlayer dielectric layer and a metal electrode structure diagram of an NPN type super junction device structure provided in the prior art;

[0047] Figure 5 is a flow chart of the manufacturing method of the super junction device structure provided in the embodiment one of the present application;

[0048] Figure 6 is a semiconductor substrate structure diagram of the super junction device structure provided in the embodiment one of the present application;

[0049] Figure 7 is an epitaxial layer structure diagram of the super junction device structure provided in the embodiment one of the present application;

[0050] Figure 8 is a column structure diagram of the super junction device structure provided in the embodiment one of the present application;

[0051] Figure 9 is an ion layer structure diagram of the super junction device structure provided in the embodiment one of the present application;

[0052] Figure 10 is a body contact region structure diagram of the super junction device structure provided in the embodiment one of the present application;

[0053] Figure 11 is a gate oxide layer structure diagram of the super junction device structure provided in embodiment one of the present application;

[0054] Figure 12 is a polysilicon gate structure diagram of the super junction device structure provided in embodiment one of the present application;

[0055] Figure 13 is a source region structure diagram of the super junction device structure provided in embodiment one of the present application;

[0056] Figure 14 is an interlayer dielectric layer structure diagram of the super junction device structure provided in embodiment one of the present application;

[0057] Figure 15 is a metal electrode structure diagram of the super junction device structure provided in embodiment one of the present application;

[0058] The symbols are explained as follows:

[0059] 1, semiconductor substrate; 2, epitaxial layer; 3, column structure; 5, ion layer structure; 6, body contact region; 7, gate oxide layer; 8, polysilicon gate; 9, source region; 10, interlayer dielectric layer; 11, metal electrode. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0061] In embodiment one, as shown in Figure 5 , a preparation method of a super junction device structure is provided, including the following steps:

[0062] S1: providing a semiconductor substrate of a first conductive type.

[0063] In this step, the formed semiconductor substrate 1 is as shown in Figure 6 . Optionally, the first conductive type of the semiconductor substrate 1 is n-type, that is, the semiconductor substrate 1 is an n-type silicon substrate; as another implementation manner, the first conductive type of the semiconductor substrate 1 can also be p-type, that is, the semiconductor substrate adopts a p-type silicon substrate.

[0064] S2: epitaxially growing an epitaxial layer of the first conductive type on the semiconductor substrate.

[0065] In this step, the formed epitaxial layer 2 is as shown in Figure 7As shown, optionally, the epitaxial layer 2 is a germanium-silicon layer, and has the same first conductive type, i.e., n-type, as the semiconductor substrate. The n-type germanium-silicon layer can be obtained by doping during epitaxial growth.

[0066] As another implementation, the material of the epitaxial layer 2 can not be germanium-silicon, but other materials, such as gallium nitride or germanium-silicon-carbon.

[0067] S3: Forming a column structure of a second conductive type in the epitaxial layer, and the column structure extends along the thickness direction of the epitaxial layer. Specifically, the forming of the column structure of the second conductive type includes:

[0068] S301: Performing deep trench etching on the epitaxial layer to form a plurality of equidistant trenches;

[0069] In this step, a patterned photoresist mask layer is formed on the epitaxial layer by a photolithography process, and the photoresist mask layer is used as an etching stop layer to etch the epitaxial layer, for example, dry etching or wet etching, thereby forming a plurality of equidistant trenches.

[0070] S302: Epitaxially growing a filling layer with the second conductive type in each trench to form the column structure of the second conductive type.

[0071] In this step, the two column structures 3 of the second conductive type are formed as shown in Figure 8 As shown, optionally, the material of the column structure 3 includes silicon, and the second conductive type is p-type. In the design process of the column structure of the actual super-junction device structure, the column structure is a plurality (hundreds or thousands), and the plurality of column structures have the same width, and the plurality of column structures are equidistantly arranged in the epitaxial layer.

[0072] S4: Performing first ion implantation on the top of the column structure to form an ion layer structure to reduce the doping concentration of the surface of the column structure; the ion type of the first ion implantation is the first conductive type.

[0073] In this step, the specific process of performing the first ion implantation on the top of the column structure includes:

[0074] Photolithography is performed with a column structure mask to obtain a photoresist hard mask layer, and the photoresist hard mask layer is used as an etching stop layer to perform ion implantation on the top of the column structure. The ion concentration range of the implantation is 2*10 of 10~16 per cubic centimeter, and the preferred ion concentration is 14 per cubic centimeter, and the energy is about 40-50KeV. The formed ion layer structure 5 is as shown in Figure 9 .

[0075] The first ion implantation in this step reduces the doping concentration of the column structure surface, which can adjust the opening voltage of the super junction device structure. Moreover, this process makes an important preparation for the subsequent formation of the body contact region, which can effectively reduce the process cost, and can avoid the problem of mutual diffusion of the doping ions of the body contact region and the epitaxial layer caused by the high-temperature promotion process in the body contact region manufacturing process, thereby adjusting the charge balance.

[0076] S5: performing a second ion implantation from the top of the ion layer structure to form a body contact region in the lower part of the ion layer structure, and the ion type of the second ion implantation is the second conductive type.

[0077] In this step, after the ion layer structure is formed, the photoresist hard mask layer is used as an etching barrier to perform ion implantation from the top of the ion layer, and the body contact region 6 formed in the upper part of the column structure is as shown in Figure 10 , which has the same width and height as the column structure 3 in Figure 9 . As another implementation, the body contact region 6 has the same width as the column structure 3 in Figure 9 , but has a different height, i.e., the height of the body contact region 6 is less than the height of the column structure 3 in Figure 9 .

[0078] S6: forming a gate oxide layer on the upper surface of the epitaxial layer.

[0079] In this step, a thermal oxide layer is formed on the upper surface of the epitaxial layer by a furnace tube process, and then a patterned gate oxide layer 7 is formed by a photoetching and etching process, as shown in Figure 11 . Preferably, the thickness of the gate oxide layer 7 ranges from 90 nm to 110 nm.

[0080] S7: forming a polysilicon gate on the upper surface of the gate oxide layer.

[0081] In this step, the formed polysilicon gate 8 is as shown in Figure 12 . The specific formation process of the polysilicon gate 8 is to first deposit a polysilicon material layer on the gate oxide layer by chemical vapor deposition, and then form a patterned polysilicon gate 8 by photoetching and etching technology.

[0082] S8: forming a source region in the body contact region by an ion implantation process.

[0083] In this step, the formed source region 9 is as shown in Figure 13 . In an example, the source region 9 is n-type doped, and the ion implantation of the source region 9 is the same as that of the body contact region in step S7. Moreover, the height of the source region 9 is greater than the height of the ion layer structure 5, and the height of the source region 9 is less than the height of the body contact region 6.

[0084] S9: Forming an interlayer dielectric layer on the surface and sidewall of the polysilicon gate.

[0085] In this step, the formed interlayer dielectric layer 10 is as shown in the figure, and the specific forming process of the interlayer dielectric layer 10 is: depositing a dielectric material layer on the surface and sidewall of the body ion layer structure 5, the source region 9 and the polysilicon gate 8, and then removing the dielectric material layer on the body ion layer structure 5 and the source region 9 by etching, so as to obtain the interlayer dielectric layer 10 covering and wrapping the polysilicon gate. Figure 14

[0086] Optionally, the interlayer dielectric layer 10 can be a silicon nitride layer, or a silicon dioxide layer, or a combination of a silicon nitride layer and a silicon dioxide layer.

[0087] S10: Forming a metal electrode on the surface of the body ion layer structure, the source region and the interlayer dielectric.

[0088] In this step, the formed metal electrode 11 is as shown in the figure, and the specific forming method of the metal electrode 11 is physical vapor deposition or chemical vapor deposition. Optionally, the material of the metal electrode 11 includes aluminum, gold, silver or copper, etc. Figure 15

[0089] The preparation method of the super junction device structure has the following advantages:

[0090] (1) Before forming the body contact region by ion implantation, a first ion implantation is performed to form an ion layer structure on the surface of the column structure, which can effectively eliminate the phenomenon of charge distribution imbalance caused by the mutual diffusion of carriers (i.e. doping ions) between the body contact region and the epitaxial layer during the thermal propulsion driving process when forming the body contact region, thereby improving the device voltage withstand performance.

[0091] (2) From the perspective of optimizing the device structure, the width of the formed body contact region and the column structure is consistent, which can adjust the charge balance while reducing the process complexity and process cost.

[0092] (3) The mask manufacturing cost of the body contact region layer is saved, and the cost advantage of the device is improved.

[0093] In the second embodiment, a preparation method of a super junction device structure is provided, and the difference between the method and the preparation method in the first embodiment is:

[0094] In order to reduce the device size, in step S302, the width of each column structure formed after filling is greater than 5um, and the spacing between any two column structures is less than 4um. Therefore, in step S301, when designing the size of the trench, the width of each trench and the spacing between adjacent trenches need to be considered, that is, the width of each trench must be greater than 5um, and the spacing between adjacent trenches is less than or equal to 4um.​​

[0095] Preferably, the distance between the pillar structures of the conventional super junction device structure is reduced by 50%, and the width of the pillar structure is increased by 20%, so that the width of the pillar structure is 5.76um and the distance between adjacent pillar structures is 3.6um. According to the software simulation calculation of the super junction device structure according to this structure, the size of the whole device is reduced by about 30%, and the cost of the device is saved by about 30%.

[0096] In embodiment three, a preparation method of a super junction device structure is provided, which is different from the preparation method in embodiment one in that steps S6 and S7 in embodiment one are combined into:

[0097] forming a thermal oxide layer, depositing a polysilicon material layer on the thermal oxide layer, using a photoresist mask layer defined by photolithography to etch the polysilicon material layer and the thermal oxide layer in sequence, thereby forming a gate oxide layer and a polysilicon gate.

[0098] In embodiment four, as shown in Figure 15 , a super junction device structure is provided, which comprises:

[0099] a semiconductor substrate 1 of a first conductivity type;

[0100] an epitaxial layer 2 of a first conductivity type on the upper surface of the semiconductor substrate 1;

[0101] a pillar structure 3 of a second conductivity type (the pillar structure 3 is shown in Figure 8 ) in the epitaxial layer and extending along the thickness direction of the epitaxial layer;

[0102] an ion layer structure 5 on the top of the pillar structure 3, the ion layer structure 5 being formed by first ion implantation on the top of the pillar structure 3; the ion type implanted in the ion layer structure 5 is of a first conductivity type;

[0103] a body contact region 6 in the lower part of the ion layer structure 5, the body contact region 6 being formed by second ion implantation on the upper part of the ion layer structure 5; the ion type implanted in the body contact region 6 is of a second conductivity type;

[0104] a gate oxide layer 7 on the upper surface of the epitaxial layer 2;

[0105] a polysilicon gate 8 on the upper surface of the gate oxide layer 7;

[0106] a source region 9 in the body contact region 6;

[0107] an interlayer dielectric layer 10 on the surface and sidewall of the polysilicon gate 8;

[0108] Metal electrode 11, located on the surface of the ion layer structure 5, the source region 9 and the interlayer dielectric 10.

[0109] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method of fabricating a super junction device structure, comprising: The method comprises the following steps: ​ providing a semiconductor substrate of a first conductivity type; forming an epitaxial layer of the first conductivity type on the semiconductor substrate; forming a column structure of a second conductivity type in the epitaxial layer, and the column structure extends along the thickness direction of the epitaxial layer; performing a first ion implantation on the top of the column structure to form an ion layer structure for reducing the doping concentration of the surface of the column structure, and the ion type of the first ion implantation is the first conductivity type; performing a second ion implantation on the top of the ion layer structure to form a body contact region in the lower part of the ion layer structure, and the ion type of the second ion implantation is the second conductivity type; forming a gate oxide layer on the upper surface of the epitaxial layer; forming a polysilicon gate on the upper surface of the gate oxide layer; forming a source region in the body contact region by an ion implantation process; forming an interlayer dielectric layer on the surface and sidewall of the polysilicon gate.

2. The method of claim 1, wherein the superjunction device structure is formed by: The width of the body contact region is the same as the width of the column structure through the second ion implantation.

3. The method of claim 1, wherein the superjunction device structure is formed by: The width of each column structure formed in the epitaxial layer is greater than 5 um, and the spacing between any two column structures is less than 4 um.

4. The method of claim 1, wherein the superjunction device structure is formed by: The ion concentration range of the first ion implantation is 2*10 of 10~16 per cubic centimeter.

5. The method of claim 1, wherein the superjunction device structure is formed by: The height of the source region is greater than the height of the ion layer structure, and the height of the source region is less than the height of the body contact region.

6. A superjunction device structure, comprising: It comprises: a semiconductor substrate of a first conductivity type; an epitaxial layer of the first conductivity type on the upper surface of the semiconductor substrate; a column structure of a second conductivity type in the epitaxial layer, and the column structure extends along the thickness direction of the epitaxial layer; an ion layer structure on the top of the column structure, and the ion layer structure is formed by performing a first ion implantation on the top of the column structure; the ion type implanted in the ion layer structure is the first conductivity type; a body contact region in the lower part of the ion layer structure, and the body contact region is formed by performing a second ion implantation on the upper part of the ion layer structure; the ion type implanted in the body contact region is the second conductivity type; a gate oxide layer on the upper surface of the epitaxial layer; a polysilicon gate on the upper surface of the gate oxide layer; a source region in the body contact region; an interlayer dielectric layer on the surface and sidewall of the polysilicon gate.

7. The superjunction device structure of claim 6, wherein the first and second semiconductor layers are formed of a semiconductor material having a bandgap of about 1.0 eV to about 1.4 eV. The width of the body contact region is the same as the width of the column structure.

8. The superjunction device structure of claim 6, wherein, The width of each column structure formed in the epitaxial layer is greater than 5 um, and the spacing between any two column structures is less than 4 um.

9. The super-junction device structure of claim 6, wherein, The ion concentration range of the first ion implantation is 2*10 of 10~16 per cubic centimeter.

10. The superjunction device structure of claim 6, wherein, The height of the source region is greater than the height of the ion layer structure, and the height of the source region is less than the height of the body contact region.

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