Method of forming a semiconductor package

Abstract

A method of forming a semiconductor package includes forming a region of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature greater than the first melting temperature; placing the solder bumps on the region of solder paste; performing a first reflow process at a first reflow temperature for a first duration, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration, wherein the second reflow temperature is greater than the second melting temperature.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to methods of forming semiconductor packages. BACKGROUND

[0002] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size of the devices. This allows more components to be integrated into a given area, which in turn, increases the functionality of the electronic devices. Integrated circuits having high functionality requirements need many input / output pads. However, for applications where miniaturization is important, small packages can be desirable.

[0003] Integrated fan-out (InFO) packaging technology is becoming increasingly popular, particularly when combined with wafer level packaging (WLP) technology, in which an integrated circuit is packaged in a package that typically includes a redistribution layer (RDL) or a post-passivation interconnect for fan-out routing of the contact pads for the package so that electrical contacts can be made at a greater pitch than the contact pads of the integrated circuit. The resulting package structure provides a high functional density and high performance package at a relatively low cost. SUMMARY

[0004] Embodiments of the present invention provide a method of forming a semiconductor package, comprising: forming a redistribution structure, the redistribution structure comprising a first metallization pattern on a first side of the redistribution structure; forming an interconnect structure, the interconnect structure comprising a second metallization pattern on a first side of the interconnect structure; joining the interconnect structure to the redistribution structure, comprising: depositing a solder paste on the first metallization pattern, wherein the solder paste is a first material; forming a solder ball on the second metallization pattern, wherein the solder ball is a second material different from the first material; placing the solder ball in physical contact with the solder paste; performing a first reflow process at a first temperature at which the solder paste is melted; and after performing the first reflow process, performing a second reflow process at a second temperature at which the solder paste is melted and the solder ball is melted, wherein the second temperature is greater than the first temperature; and after performing the second reflow process, depositing an underfill between the redistribution structure and the interconnect structure.

[0005] Another embodiment of the invention provides a method of forming a semiconductor package, comprising: forming a plurality of regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming a plurality of solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature greater than the first melting temperature; placing the plurality of solder bumps on the plurality of regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration, wherein the second reflow temperature is greater than the second melting temperature.

[0006] Yet another embodiment of the invention provides a method of forming a semiconductor package, comprising: depositing solder paste on a first contact pad of a first package component, wherein the solder paste includes bismuth; depositing solder material on a second contact pad of a second package component, wherein the solder material is free of bismuth; performing a first heating process at a first temperature, the first heating process joining the solder paste to the solder material, wherein the solder material remains solid during the first heating process; and after performing the first heating process, performing a second heating process at a second temperature that melts the solder paste and the solder material to form a connection that joins the first contact pad and the second contact pad. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the invention can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that various components have not been drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 and Figure 2 A cross-sectional view showing an intermediate step of forming a redistribution structure is shown, in accordance with some embodiments.

[0009] Figure 3 A cross-sectional view showing an interconnect structure is shown, in accordance with some embodiments.

[0010] Figure 4 and Figure 5 A cross-sectional view showing an intermediate step of joining an interconnect structure to a redistribution structure is shown, in accordance with some embodiments.

[0011] Figure 6A 、 Figure 6B and Figure 6C A cross-sectional view showing an intermediate step of joining an interconnect structure to a redistribution structure is shown, in accordance with some embodiments.

[0012] Figure 7A、 Figure 7B and Figure 7C A cross-sectional view showing an intermediate step of bonding an interconnect structure to a redistribution structure is shown in accordance with some embodiments.

[0013] Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12A and Figure 12B A cross-sectional view showing an intermediate step of forming a bonded structure is shown in accordance with some embodiments.

[0014] Figure 13 A cross-sectional view showing a packaged structure is shown in accordance with some embodiments.

[0015] Figure 14A and Figure 14B A cross-sectional view showing an intermediate step of bonding a redistribution structure on a carrier substrate is shown in accordance with some embodiments.

[0016] Figure 15 A cross-sectional view showing a package is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first component over or on a second component can include embodiments where the first component and the second component are formed in direct contact, and where additional components can be formed between the first component and the second component such that the first component and the second component do not form direct contact. Moreover, the application can be practiced with additional components not expressly described herein. Further, the application can be repeated with variations and permutations of the examples described herein. This repetition and practice together with variations and permutations of the examples are expressly contemplated herein.

[0018] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] In the present disclosure, various aspects of packaging structures and their formation are described. In some embodiments, two separate reflows (one at a relatively lower temperature and the other at a relatively higher temperature) are used to form the joints between structures. The joints can be formed by applying a solder paste with a relatively lower melting temperature to one structure and attaching a solder bump with a relatively higher melting temperature to another structure, and then using two reflows to form the joints from the solder paste and the solder bump. Using the techniques described herein to form the joints within a package can result in reduced warpage of the packaged structure after the joints are formed. Reducing warpage can reduce problems associated with warpage and can improve performance and yield.

[0020] In some cases, using connections formed from low temperature solder paste and solder balls that are connected using the described low temperature reflow and subsequent high temperature reflow can improve the conductivity and reliability of the electrical connections between the joined structures. In some cases, the techniques described herein can be performed in a process flow with other typical manufacturing processes, and thus can add little or no additional cost to existing processes. Additionally, using the described process techniques can result in improved yield and improved connection reliability, particularly for packages with larger areas. For example, the process techniques described herein can reduce warpage, and thus also reduce problems such as cracking or delamination associated with warpage.

[0021] Turning to Figure 1 , a first carrier substrate 102 on which a metallization pattern 105 has been formed is shown, in accordance with some embodiments. The first carrier substrate 102 can comprise, for example, a silicon-based material such as a silicon substrate (e.g., a silicon wafer), a glass material, silicon oxide, or other materials such as aluminum oxide or combinations. In some embodiments, the first carrier substrate 102 can be a panel structure, which can be, for example, a support substrate formed from a suitable dielectric material such as a glass material, a plastic material, or an organic material. The panel structure can be, for example, a rectangular panel.

[0022] As illustrative examples, Figure 14A and Figure 14B structures formed using different types of first carrier substrates 102 are shown, in accordance with some embodiments (see Figure 11 ). Figure 14A embodiments in which the first carrier substrate 102 is a silicon wafer, and Figure 14B embodiments in which the first carrier substrate 102 is a panel structure are shown. Figures 14A-14B A plurality of redistribution structures 100 formed on the first carrier substrate 102 are shown. In this manner, multiple structures can be formed on the first carrier substrate 102 at the same time. The structures formed on the first carrier substrate 102 can be subsequently singulated (see, for example, Figure 12B ).

[0023] In some embodiments, a release layer 103 can be formed on the top surface of the first carrier substrate 102 to facilitate subsequent debonding of the first carrier substrate 102. The release layer 103 can be formed of a polymer-based material that can be removed along with the first carrier substrate 102 from the structure above that will be formed in subsequent steps. In some embodiments, the release layer 103 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 103 can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 103 can be dispensed as a liquid and cured, can be a laminate film laminated onto the first carrier substrate 102, or the like. The top surface of the release layer 103 can be flush and can have a high degree of planarity. In some embodiments, instead of or in addition to the release layer 103, a die attach film (DAF) (not shown) can be used.

[0024] In some embodiments, a dielectric layer 104 can be formed on the release layer 103. The bottom surface of the dielectric layer 104 can be in contact with the top surface of the release layer 103. In some embodiments, the dielectric layer 104 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 104 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 104 can be formed by any acceptable deposition process such as spin coating, CVD, lamination, or the like or a combination thereof.

[0025] A metallization pattern 105 of the redistribution structure 100 can then be formed on the dielectric layer 104. The metallization pattern 105 can include, for example, wires, redistribution layers or redistribution lines, contact pads, or other conductive components that extend over a major surface of the dielectric layer 104. As an example of forming the metallization pattern 105, a seed layer is formed over the dielectric layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a layer of titanium and a layer of copper over the layer of titanium. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 105. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 105. Other techniques of forming the metallization pattern 105 are possible.

[0026] In Figure 2 some embodiments, additional dielectric layers and metallization patterns of the redistribution structure 100 are formed over the dielectric layer 104 and the metallization pattern 105, in accordance with some embodiments. Figure 2 The redistribution structure 100 shown includes additional dielectric layers 106, 108, 110, 112, 114, 116, and 118; and additional metallization patterns 107, 109, 111, 113, 115, 117, and 119. The redistribution structure 100 is shown as an example having eight metallization patterns, but more or fewer dielectric layers and metallization patterns can be formed in the redistribution structure 100. If fewer dielectric layers and metallization patterns are to be formed, some of the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, some of the steps and processes discussed below can be repeated.

[0027] A dielectric layer 106 can be deposited over the dielectric layer 104 and the metallization pattern 105. In some embodiments, the dielectric layer 106 is formed of a photosensitive material such as PBO, polyimide, BCB, etc. The photosensitive material can be patterned using a photolithography mask. The dielectric layer 106 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. The dielectric layer 106 is then patterned. The patterning forms openings that expose portions of the metallization pattern 105. The patterning can be by an acceptable process such as by exposing the dielectric layer 106 to light and developing the dielectric layer 106 when the dielectric layer 106 is a photosensitive material, or by etching such as anisotropic etching.

[0028] A metallization pattern 107 is then formed. The metallization pattern 107 includes electrically conductive elements that extend along a major surface of the dielectric layer 106 and extend through the dielectric layer 106 to physically and electrically couple to the metallization pattern 105. As an example of forming the metallization pattern 107, a seed layer is formed over the dielectric layer 106 and in the openings that extend through the dielectric layer 106. In some embodiments, the seed layer is a metal layer that can be a single layer or a composite layer that includes multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD, etc. A photoresist is then formed over the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 107. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating, etc. The conductive material can include a metal such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and portions of the underlying seed layer form the metallization pattern 107. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portions of the seed layer are removed such as by using an acceptable etching process such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 107. In some embodiments, the metallization pattern 107 has a different size than the metallization pattern 105. For example, the wires and / or vias of the metallization pattern 107 can be wider or thicker than the wires and / or vias of the metallization pattern 105. The metallization pattern 107 can be formed to a larger pitch than the metallization pattern 105.

[0029] The remaining dielectric layers and metallization patterns of redistribution structure 100 can be formed in a similar manner to dielectric layer 106 and metallization pattern 107. For example, dielectric layer 108 can be deposited on metallization pattern 107 and dielectric layer 106. Dielectric layer 108 can be formed in a similar manner to dielectric layer 106, and can be formed from a similar material to dielectric layer 106. Metallization pattern 109 can then be formed. Metallization pattern 109 includes portions that are located on and extend along a major surface of dielectric layer 108, as well as portions that extend through dielectric layer 108 to physically and electrically couple metallization pattern 107. Metallization pattern 109 can be formed in a similar manner and from a similar material to metallization pattern 107. In some embodiments, metallization pattern 109 has a different size than metallization pattern 107. For example, the conductive lines and / or vias of metallization pattern 109 can be wider or thicker than the conductive lines and / or vias of metallization pattern 107. Additionally, metallization pattern 109 can be formed with a larger pitch than metallization pattern 107.

[0030] The above-described steps and processes for forming dielectric layer 106 or 108 can be repeated to form dielectric layers 110, 112, 114, 116, or 118. The above-described steps and processes for forming metallization pattern 107 or 109 can be repeated to form metallization patterns 111, 113, 115, 117, or 119. As shown, dielectric layer 118 is the topmost dielectric layer of redistribution structure 100, and metallization pattern 119 is the topmost metallization pattern of redistribution structure 100. In this way, all of the intermediate metallization patterns of redistribution structure 100 are disposed between metallization pattern 119 and metallization pattern 105. In some embodiments, metallization pattern 119 has a different size than one or more of the intermediate metallization patterns. Additionally, metallization pattern 119 can be formed with a larger pitch than one or more of the intermediate metallization patterns. In some embodiments, metallization pattern 119 can be an under bump metallization structure (UBM) of redistribution structure 100. Figure 2

[0031] Figure 3 An interconnect structure 200 according to some embodiments is shown. Interconnect structure 200 is subsequently bonded to redistribution structure 100 to form bonded structure 300 (see Figure 8 ​), and provide additional routing and stability for redistribution structure 100. For example, interconnect structure 200 can reduce warpage of redistribution structure 100. In some embodiments, interconnect structure 200 can be, for example, an interposer or a“semi-finished substrate,” and can be devoid of active devices. In some embodiments, the interconnect structure can include routing layers (e.g., routing structures 212 and 213) formed on a core substrate 202. Core substrate 202 can include materials such as anode build film (ABF), pre-impregnated composite fiber (“prepreg”) material, epoxy, molding compound, epoxy molding compound, fiberglass reinforced resin material, printed circuit board (PCB) material, silica filler, polymeric material, polyimide material, paper, fiberglass, non-woven glass fabric, glass, ceramic, other laminates, etc., or combinations thereof. In some embodiments, the core substrate can be a double-sided copper clad laminate (CCL) substrate, etc. Core substrate 202 can have a thickness between about 30 pm and about 2000 pm, such as about 500 pm or about 1200 pm.

[0032] Interconnect structure 200 can have one or more routing structures 212 / 213 formed on each side of core substrate 202 and through-vias 210 extending through core substrate 202. Routing structures 212 / 213 and through-vias 210 provide additional circuit routing and interconnects. Through-vias 210 can interconnect routing structure 212 and routing structure 213. Routing structures 212 / 213 can include one or more routing layers 208 / 209 and one or more dielectric layers 218 / 219. In some embodiments, routing layers 208 / 209 and / or through-vias 210 can include one or more layers of copper, nickel, aluminum, other conductive materials, etc., or combinations thereof. In some embodiments, dielectric layers 218 / 219 can include materials such as build-up material, ABF, pre-impregnated material, laminate material, another material similar to those described above for core substrate 202, etc., or combinations thereof. Figure 2 The illustrated interconnect structure 200 shows two routing structures 212 / 213 with a total of six routing layers, but in other embodiments, interconnect structure 200 can include only one routing structure (e.g., 212 or 213), or routing structures 212 / 213 can include more or fewer routing layers.

[0033] In some embodiments, the openings in the core substrate 202 for the through-hole 210 may be filled with a filler material 211. The filler material 211 can provide structural support and protection for the conductive material of the through-hole 210. In some embodiments, the filler material 211 may be a material such as molding material, epoxy resin, epoxy molding compound, resin, material including monomers or oligomers (such as acrylated urethane, rubber-modified acrylated epoxy resin, or multifunctional monomers), or combinations thereof. In some embodiments, the filler material 211 may include pigments or dyes (e.g., for color), or other fillers and additives that alter rheology, improve adhesion, or affect other properties of the filler material 211. The through-hole 210 may be completely filled, omitting the filler material 211.

[0034] In some embodiments, the interconnect structure 200 may include a passivation layer 207 formed over one or more sides of the interconnect structure 200. The passivation layer 207 may be a material such as a nitride, oxide, polyimide, high-temperature polyimide, solder resist, or a combination thereof. Once formed, the passivation layer 207 may be patterned (e.g., using suitable photolithography and etching processes) to expose portions of the routing layers 208 / 209 of the routing structures 212 / 213.

[0035] Figures 4-8 This illustrates, according to some embodiments, joining the interconnect structure 200 to the redistribution structure 100 to form the joining structure 300 (see...). Figure 8 The intermediate steps of ). Figure 4 In some embodiments, regions of solder paste with a relatively low melting temperature (“LT paste”) 122 are formed on the redistribution structure 100, and solder bumps 220 are formed on the interconnect structure 200. The following can be used for… Figures 6A-6C The described low-temperature reflow process (“LT reflow”) 130 and subsequent high-temperature reflow process (“HT reflow”) 132 bond regions of the LT paste 122 of the redistribution structure 100 to corresponding solder bumps 220 of the interconnect structure 200. As described herein, the use of LT paste 122, LT reflow 130, and HT reflow 132 can reduce warpage of bonding structures such as bonding structure 300. For example, in some cases, the techniques described herein can reduce the warpage of bonding structure 300 by between about 35% and about 50%. In some cases, the techniques described herein can result in warpage of bonding structure 300 of less than about 1400 μm. The described embodiments include LT paste 122 formed on the redistribution structure 100 and solder bumps 220 formed on the interconnect structure 200; however, in other embodiments, LT paste 122 may be formed on the interconnect structure 200, and solder bumps 220 may be formed on the redistribution structure 100.

[0036] refer to Figure 4 Solder bumps 220 can be formed on the outer routing layer (e.g., the outermost routing layer 209) of the interconnect structure 200. Solder bumps 220 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-plating and electroless palladium-plating immersion gold technology (ENEPIG), etc. Solder bumps 220 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, tin-silver-copper (“SAC”), etc., or combinations thereof. In some embodiments, solder bumps 220 are formed by first forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In some embodiments, solder bumps 220 are materials with a melting point greater than that of LT paste 122. For example, solder bump 220 may have a melting point greater than about 210°C, and LT paste 122 may have a melting point less than about 210°C. In some embodiments, LT paste 122 may have a melting point greater than room temperature but less than 210°C, such as about 138°C or another temperature. In some cases, using LT paste 122 with a relatively low melting point can reduce warpage of the bonded structure compared to using LT paste 122 with a relatively high melting point. Other materials and melting point temperatures are possible and are considered to be within the scope of this invention.

[0037] Still referencing Figure 4 An area of ​​LT paste 122 may be formed on the topmost metallized pattern (e.g., metallized pattern 119) of the redistribution structure 100. In some embodiments, LT paste 122 comprises a conductive material such as solder, solder paste, etc. LT paste 122 may be formed using any suitable process, such as printing, stenciling, dispensing, or other processes. Each area of ​​LT paste 122 may be separated from adjacent areas of LT paste 122, and each area of ​​LT paste 122 may have a corresponding solder bump 220 to which LT paste 122 will subsequently be attached.

[0038] The region of LT paste 122 can have a thickness T1 between approximately 50 μm and approximately 100 μm (see...) Figure 6A However, other thicknesses are permissible. In some embodiments, the mass ratio of the area of ​​LT paste 122 to its corresponding solder bump 220 is between about 1:2 and about 1:7, but other ratios are permissible. In some embodiments, the area of ​​LT paste 122 may have a width W1 between about 100 μm and about 250 μm (see...). Figure 6A Alternatively, the solder bump 220 may have a width W2 between approximately 200 μm and approximately 400 μm (see...). Figure 6A), but other widths are possible. The width ratio of W1 : W2 can be between about 1 : 2 and about 1 : 4, but other ratios are possible. In some embodiments, the shape of the connections 222 can be controlled by controlling the thickness T1, the mass ratio of the LT paste 122 to the solder bumps 220, the area of the LT paste 122 to the width of the solder bumps 220 or width ratio, and other features (see Figure 6C ) are described in more detail below. Figures 6A-7C The shape of the connections 222 is controlled in this way is described in more detail below.

[0039] In some embodiments, the LT paste 122 can include tin bismuth (SnBi) or a combination of tin bismuth and other metals, such as silver, antimony, copper, nickel, etc. In some embodiments, the LT paste 122 includes about 35% by mass to about 58% by mass bismuth, but other amounts are possible. For example, the mass ratio of tin to bismuth can be between about 65:35 and about 42:58, but other ratios are possible. In some cases, the relatively small proportion of bismuth in the LT paste 122 can form an initial connection 222' or connection 222 that is less brittle (see Figures 6A-6C ), which can improve the reliability and yield of the bonded structure. The LT paste 122 can be, for example, Sn-58Bi, Sn-57Bi-1Ag, Sn-40Bi-Cu-Ni, Sn-58Bi-Sb-Ni, Sn 35Bi-0.5Cu-0.03Ni, etc. These are example materials that can be used for the LT paste 122, and other materials besides these can be used in other embodiments. In some embodiments, the LT paste 122 is a material that has a lower melting point than the solder bumps 220. For example, the LT paste 122 can be tin bismuth, which has a melting point of about 139°C, and the solder bumps 220 can be tin silver copper (SAC), which has a melting point of about 217°C. This is an example, and other materials or melting point temperatures besides these are within the scope of the disclosure.

[0040] Figure 5 The solder bumps 220 of the interconnect structure 200 are shown placed in physical contact with the LT paste 122 on the redistribution structure 100. The interconnect structure 200 can be placed on the redistribution structure 100 using, for example, a pick and place process. As shown in Figure 5 each solder bump 220 is in physical contact with a respective area of the LT paste 122. In other embodiments, more than one solder bump 220 can be in physical contact with the same area of the LT paste 122.

[0041] Turning to Figures 6A-6CLT reflow 130 and a high temperature reflow process ("HT reflow") 132 to join the solder bumps 220 to the LT paste 122, forming the connections 222. In some embodiments, the LT reflow 130 is performed first, followed by the HT reflow 132. The HT reflow 132 is performed using a higher process temperature than the LT reflow 130. For clarity, Figures 6A-6C An enlarged view of the portion labeled "P" in Figure 5 is shown. Figure 6A A structure after the solder bumps 220 have been placed in contact with the regions of the LT paste 122 is shown, similar to Figure 5 the structure shown.

[0042] In Figure 6B , the LT reflow 130 is performed to initially join the solder bumps 220 of the interconnect structure 200 to the LT paste 122 of the redistribution structure 100. The LT reflow 130 can be performed using a temperature that is greater than the melting point of the LT paste 122 but less than the melting point of the solder bumps 220. In this way, the LT reflow 130 melts the LT paste 122 and forms a join between the LT paste 122 and the solder bumps 220 without melting the solder bumps 220. As Figure 6B shown, the LT reflow 130 joins the solder bumps 220 and the LT paste 122 to form initial connections 222'. In some cases, the initial connections 222' can be considered temporary connections that initially join the interconnect structure 200 to the redistribution structure 100.

[0043] In some cases, using the LT reflow 130 to form the initial connections 222' by melting the LT paste 122 can result in a reduced warpage of the joined structure 300. For example, a change in material dimensions can be directly proportional to a temperature increase of the material, directly proportional to the coefficient of thermal expansion (CTE) of the material, due to the increase in material temperature. Thus, a smaller temperature increase can result in a smaller change in dimensions. In some cases, if the redistribution structure 100 has a different overall CTE than the interconnect structure 200, then for a given temperature increase, the relative change in dimensions of the redistribution structure 100 is different than the relative change in dimensions of the interconnect structure 200. When the redistribution structure 100 is joined to the interconnect structure 200 to form the joined structure 300 (see Figure 8During reflow, dimensional mismatches between the redistribution structure 100 and the interconnect structure 200 can cause warping of the bonding structure 300. Therefore, the relatively low temperature used in the LT reflow 130 can reduce warping or bending during the formation of bonding structures such as the bonding structure 300. In some embodiments, the LT reflow 130 is performed at a temperature between about 130°C and about 180°C, but other temperatures are possible. The temperature used for the LT reflow 130 can depend on the specific components of the LT paste 122. In some embodiments, the LT reflow 130 is performed for a time between about 100 seconds and about 200 seconds, but other times are possible.

[0044] In some cases, such as Figure 6B As shown, LT reflow 130 can soften solder bumps 220, causing them to change shape. In other cases, solder bumps 220 can substantially maintain their shape during LT reflow 130. LT reflow 120 can form initial connections 222' with regions of different compositions. (See reference...) Figure 6B The initial connector 222' may include a region 220' having a composition similar to that of the solder bump 220 and a region 122' having a composition similar to that of the LT paste 122. For example, in an embodiment where the LT paste 122 includes a higher bismuth concentration than the solder bump 220, region 122' may have a higher bismuth concentration than region 220'. The interface between region 122' and region 220' may be abrupt or gradual, or a combination thereof. Region 122' or 220' may have a different shape, size, or composition than these examples.

[0045] exist Figure 6CIn some embodiments, HT reflow 132 is performed to form connection 222 from initial connection 222'. HT reflow 132 can be performed using a temperature greater than the melting point of solder bump 220 (or region 220'). In this way, HT reflow 132 melts solder bump 220 and LT paste 122 bonded to solder bump 220 to form connection 222. Connection 222 can form a stronger bond than initial connection 222', which can improve the reliability and structural stability of bonded structure 300. In some embodiments, HT reflow 132 is performed at a temperature between about 210 °C and about 250 °C, although other temperatures are possible. In some embodiments, HT reflow 132 is performed for a time between about 50 seconds and about 80 seconds, although other times are possible. HT reflow 132 can be performed immediately after LT reflow 130, or can be performed in a separate process after LT reflow 130 is performed. Because redistribution structure 100 and interconnect structure 200 are already bonded by initial connection 222' when HT reflow 132 is performed, any warpage caused by the relatively high temperature of HT reflow 132 is less than if initial connection 222' were not formed. In some cases, HT reflow 132 does not cause significant additional warpage, and the majority of warpage of bonded structure 300 occurs during LT reflow 130. In this way, the amount of warpage of bonded structure 300 can be controlled by controlling the parameters of LT reflow 130. Thus, performing LT reflow 130 prior to performing HT reflow 132 as described herein can reduce warpage of bonded structure 300, which can reduce the occurrence of defects such as delamination, layer separation, bond point failure, cracking, etc.

[0046] In some embodiments, HT reflow 132 can reduce the separation distance between redistribution structure 100 and interconnect structure 200 during formation of connection 222. For example, prior to performing LT reflow 130, redistribution structure 100 and interconnect structure 200 can be separated by a distance Dl, as shown in FIG. 1A. After performing LT reflow 130, redistribution structure 100 and interconnect structure 200 can be separated by a distance D2, as shown in FIG. 1B. In some embodiments, HT reflow 132 can reduce the separation distance between redistribution structure 100 and interconnect structure 200 from distance D2 to a distance D3, as shown in FIG. 1C. In this way, HT reflow 132 can reduce the separation distance between redistribution structure 100 and interconnect structure 200 during formation of connection 222. Figure 6AAs shown. The separation distance D1 can be between approximately 300 μm and approximately 500 μm, but other distances are permissible. After performing HT reflow 132, the redistribution structure 100 and the interconnect structure 200 can be separated by a distance D2 smaller than D1, such as a distance D2 between approximately 250 μm and approximately 400 μm, but other distances are permissible. In this way, after performing HT reflow 132, the separation distance D1 can be reduced (e.g., D1-D2) to approximately 0 μm and approximately 10 μm. In some cases, reducing the separation distance can reduce warpage and improve the connection between the redistribution structure 100 and the interconnect structure 200. In some cases, the separation distance D1 or the separation distance D2 can be different at different locations. For example, warpage may cause the separation distance (D1 or D2) to differ near the center of the bonding structure 300 from that near the edge of the bonding structure 300. In some cases, LT reflow 130 can also reduce the separation distance.

[0047] The connector 222 formed by HT reflow 132 can have a substantially homogeneous or heterogeneous composition. As an example of a homogeneous composition, the connector 222 can be formed to have a substantially uniform bismuth concentration throughout. In some embodiments, the connector 222 can be formed to have a homogeneous composition comprising approximately 4% bismuth by mass and approximately 20% bismuth by mass. As another example of a homogeneous composition, the connector 222 can be formed to have a substantially uniform tin to bismuth mass ratio throughout, such as between approximately 5:1 and approximately 8:1. As an example of a heterogeneous composition, the connector 222 can be formed to have a greater bismuth atom concentration near the side of the connector 222 where the LT paste 122 is formed than near the side where the solder bump 220 is formed. These are examples, and other compositions, materials, concentrations, or mass ratios are possible. In some cases, a higher temperature and / or a longer duration of HT reflow 132 can result in a more homogeneous connector 222. In some cases, a connector 222 with a lower bismuth concentration can have greater structural integrity and be less prone to breakage. In some cases, connectors 222 with more homogeneous components can have greater structural integrity, greater electrical uniformity, and are less prone to failure, cracking, debonding, etc.

[0048] In some embodiments, the shape of the connector 222 can be controlled by controlling the size or shape of the area of ​​LT paste 122; the size or shape of the solder bumps 220; the temperature or time of LT reflow 130; and / or the temperature or time of HT reflow 132. Controlling the shape of the connector 222 can allow for improved design flexibility, such as controlling the shape of the connector 222 to reduce bridging or to be compatible with a specific pitch, connector size, or expected warpage of the joint structure 300. As an example, Figures 6A-6CAn embodiment is shown in which the connector 222 is formed to have a circular shape (e.g., having protruding sidewalls). In some cases, performing the HT reflow 132 at a higher temperature and / or a longer duration can result in a connector 222 having a more circular shape compared to performing the HT reflow 132 at a lower temperature and / or a shorter duration.

[0049] Other shapes can be formed for the connector 222, such as connectors 222 with tapered sidewalls, straight sidewalls, vertical sidewalls, concave sidewalls, irregular sidewalls, asymmetrical sidewalls, or sidewalls with other contours. For example, Figures 7A-7C A connector 222 is shown that has been formed into other shapes. Figures 7A-7C The shape of connector 222 shown is an example, and other shapes besides these can be formed and are considered to be within the scope of the invention. Techniques different from those described herein can be used to form... Figures 6A-7C The shape shown.

[0050] Figure 7A The formation of a connector 222 with tapered sidewalls is shown, wherein the width of the connector 222 is greatest near the redistribution structure 100. For example, the width of the connector 222 near the redistribution structure 100 may be greater than the width W2 of the solder bump 220. Figure 7A As shown, the tapered sidewalls of connector 222 can be approximately straight, or can be approximately straight near the redistribution structure 100. In some cases, a relatively large ratio of LT paste 122 to solder bumps 220 can be used to form a shape with... Figure 7A The connector 222 has a similar shape to the one shown. For example, a mass ratio of LT paste 122 to solder bump 220 between approximately 1:8 and approximately 1:16 can be used. In some cases, a relatively large width ratio W1:W2 can be used (see...). Figure 6A ), such as width ratios between approximately 1:2 and approximately 1:4. Figure 7B The formation of a connector 222 with approximately vertical sidewalls is shown. The connector 222 can be formed to have approximately the same width as W1 or W2, or it can be formed to have different widths. Figure 7B As shown, the vertical sidewalls of connector 222 can be approximately straight, or approximately straight, near the redistribution structure 100. In some cases, a shape with the same characteristics as the solder bumps 220 can be formed by using an appropriate ratio of LT paste 122 to solder bumps 220. Figure 7B The connector 222 has a similar shape to the one shown. For example, a mass ratio of LT paste 122 to solder bump 220 between approximately 1:8 and approximately 1:16 can be used. In some cases, a width ratio W1:W2, such as a width ratio between approximately 1:2 and approximately 1:4, can be used. Figure 7CFormation of the connectors 222 with concave sidewalls is shown. In some cases, connectors 222 with shapes similar to those shown can be formed by using a relatively small ratio of LT paste 122 to solder bumps 220. For example, a mass ratio of LT paste 122 to solder bumps 220 between about 1 :8 and about 1 : 16 can be used. In some cases, a relatively small width ratio W1 :W2, such as a width ratio between about 1 :2 and about 1 :4, can be used. Figure 7C

[0051] Turning to Figure 8 , according to some embodiments, the redistribution structure 100 is shown joined to the interconnect structure 200 by the connectors 222 to form a joined structure 300. The connectors 222 can be formed using the techniques described above for Figures 5-7C forming the connectors 222 to reduce warpage of the joined structure 300.

[0052] In Figure 9 , an underfill 224 is deposited along the sidewalls of the interconnect structure 200 and in the gap between the interconnect structure 200 and the redistribution structure 100. The underfill 224 can be a material such as a mold compound, encapsulant, epoxy, underfill, mold underfill (MUF), resin, or the like. The underfill 224 can protect the connectors 222 and provide structural support for the joined structure 300. In some embodiments, the underfill 224 can be applied in a liquid or semi-liquid form, which is subsequently cured. In some embodiments, the underfill 224 can be thinned after deposition. Thinning can be performed, for example, using mechanical grinding or a CMP process. In some embodiments, the underfill 224 can be deposited over the interconnect structure 200, and the thinning can expose the topmost routing layer 208 of the interconnect structure 200.

[0053] Turning to Figure 10 , the first carrier substrate 102 is debonded to separate (or “debond”) the first carrier substrate 102 from the joined structure 300. In some embodiments, debonding includes projecting light, such as a laser or ultraviolet light, onto the release layer 103 on the first carrier substrate 102, such that the release layer breaks down under the heat of the light and the first carrier substrate 102 can be removed. The joined structure 300 can also be flipped over, as shown in Figure 10 .

[0054] In Figure 11 ​In some embodiments, under bump metallization (UBM) 310 and external connections 312 are formed on the bond structure 300. The UBM 310 extends through the dielectric layer 104 of the redistribution structure 100 and forms an electrical connection with the metallization pattern (e.g., metallization pattern 105) of the redistribution structure 100. In some embodiments, the UBM 310 can be formed, for example, by forming an opening in the dielectric layer 104 and then forming a conductive material of the UBM 310 over the dielectric layer 104 and within the opening in the dielectric layer 104. In some embodiments, the opening in the dielectric layer 104 can be formed by forming a photoresist over the dielectric layer 104, patterning the photoresist, and etching the dielectric layer 104 through the patterned photoresist using a suitable etching process (e.g., a wet etching process and / or a dry etching process).

[0055] In some embodiments, the UBM 310 includes three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers can be used for the formation of the UBM 310, such as a chromium / chromium copper alloy / copper / gold arrangement, a titanium / titanium tungsten / copper arrangement, or a copper / nickel / gold arrangement. Any suitable material or layer of material that can be used for the UBM 310 is intended to be fully encompassed within the scope of the present application. The conductive material (e.g., layers) of the UBM 310 can be formed using one or more plating processes, such as an electroplating or electroless plating process, although other formation processes, such as sputtering, evaporation, or PECVD processes, can optionally be used. Once the conductive material of the UBM 310 has been formed, portions of the conductive material can then be removed by a suitable photomasking and etching process to remove undesired material. The remaining conductive material forms the UBM 310.

[0056] Still referring to Figure 11 , according to some embodiments, the external connections 312 are formed over the UBM 310. In some embodiments, the external connections 312 can be ball grid array (BGA) connections, solder balls, controlled collapse chip connection (C4) bumps, micro bumps (e.g., micron bumps), electroless nickel electroless palladium immersion gold technology (ENEPIG) formed bumps, or the like. The external connections 312 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the external connections 312 are formed by first forming a layer of solder by evaporation, electroplating, printing, solder transfer, solder ball placement, or the like. Once the layer of solder is formed on the external connections 312, reflow can be performed to shape the material into the desired shape.

[0057] In some embodiments, an opening 226 can be formed in the underfill 224 to expose a routing layer (e.g., routing layer 208) of the interconnect structure 200. The opening 226 exposes the routing layer on which the external connections 230 (seeFigure 13 The openings 226 can be formed, for example, by forming photoresist over the underfill 224, patterning the photoresist, and etching the underfill 224 through the patterned photoresist using a suitable etching process (e.g., a wet etching process and / or a dry etching process).

[0058] Figure 12A and Figure 12B A singulation process is shown that forms individual bonded structures 300. In some embodiments, multiple bonded structures 300 can be formed on the same substrate (e.g., the first carrier substrate 102). For example, multiple redistribution structures 100 can be formed on the same substrate, and then multiple interconnect structures 200 can be bonded to the redistribution structures 100 to form multiple bonded structures 300, as previously described with respect to Figures 5-11 As shown in Figure 12A , the bonded structures 300 can then be attached to a second carrier substrate 302. The second carrier substrate 302 can be a carrier substrate similar to that described above with respect to the first carrier substrate 102. For example, the second carrier substrate 302 can be a wafer similar to that shown in Figure 14A or a panel similar to that shown in Figure 14B A release layer (not shown) can be formed on the second carrier substrate 302 to facilitate attachment of the bonded structures 300 to the second carrier substrate 302. The release layer can be similar to the release layer 104 previously described.

[0059] As shown in Figure 12B , the bonded structures 300 attached to the second carrier substrate 302 can be singulated to form individual bonded structures 300. The bonded structures 300 can be singulated using one or more saw blades that separate the structures into discrete pieces, forming one or more singulated bonded structures 300. However, any suitable singulation method can also be utilized, including laser ablation or one or more wet etches. As shown in Figure 12B , the singulation process can leave the underfill 224 remaining on the sidewalls of the interconnect structures 200, or the singulation process can remove the underfill 224 from the sidewalls of the interconnect structures 200. After the singulation process, each redistribution structure 100 can have sidewalls that are coplanar with the sidewalls of the bonded interconnect structures 200, or can have sidewalls that are coplanar with the underfill 224 remaining on the sidewalls of the bonded interconnect structures 200. In other embodiments, the redistribution structures 100 are singulated prior to being bonded to the interconnect structures 200.

[0060] Figure 13Attachment of semiconductor device 450 to bonding structure 300 to form package structure 400 is shown in accordance with some embodiments. Semiconductor device 450 is physically and electrically connected to external connections 312 for electrical connection between semiconductor device 450 and bonding structure 300. Semiconductor device 450 can be placed on external connections 312 using a suitable process, such as a pick-and-place process. Figure 13 Attachment of one semiconductor device 450 is shown, but in other embodiments, one, two, or more than three semiconductor devices can be attached to external connections 312. In some embodiments, semiconductor devices attached to external connections 312 can include more than one semiconductor device of the same type, or can include two or more semiconductor devices of different types.

[0061] Semiconductor device 450 can include one or more integrated circuit dies, such as a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), a component on a wafer (CoW), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), an I / O die, etc., or a combination thereof.

[0062] In some embodiments, semiconductor device 450 can include more than one integrated circuit die, and can include electrical interconnects between the multiple integrated circuit dies, such as a redistribution structure, an integrated fan-out structure (InFO), a through-substrate via (TSV), a metallization pattern, a circuit trace, etc. For example, the integrated circuit dies can be a memory device including multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. Semiconductor device 450 can be, for example, a package.

[0063] Semiconductor device 450 can be placed such that conductive regions (e.g., contact pads, conductive connections, solder bumps, etc.) of semiconductor device 450 are aligned with corresponding external connections 312. Once in physical contact, external connections 312 can be bonded to semiconductor device 450 with a reflow process. As Figure 13As shown, a underfill 452 can be deposited between the semiconductor device 450 and the bonded structure 300. The underfill 452 can also at least partially surround the external connections 312 or the UBMs 310. The underfill 452 can be a material such as a mold compound, an epoxy, an underfill, a molded underfill (MUF), a resin, etc., and can be similar to the underfill 224 described previously.

[0064] Still referring to Figure 13 , according to some embodiments, the second carrier substrate 302 is debonded and external connections 230 can be formed on the interconnect structure 200. In some embodiments, debonding includes projecting light, such as a laser or UV light, on a release layer on the second carrier substrate 302 such that the release layer decomposes under the heat of the light and the second carrier substrate 302 can be removed. The external connections 230 can be formed in the openings 226 of the interconnect structure 200. In some embodiments, the UBMs are first formed on the interconnect structure 200 and the external connections 230 are formed over the UBMs. The external connections 230 can be, for example, contact bumps or solder balls, but any suitable type of connection can be utilized. In embodiments where the external connections 230 are contact bumps, the external connections 230 can include a material such as tin, or other suitable materials such as silver, lead-free tin, or copper. In embodiments where the external connections 230 are solder bumps, the external connections 230 can be formed by first forming a solder layer using a technique such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape for the external connections 230. In this manner, a package structure 400 can be formed.

[0065] In some embodiments, an optional support ring 410 is attached to the bonded structure 300 to provide further mechanical support to reduce warpage of the package structure 400. The support ring 410 can be attached to the bonded structure 300 by an adhesive, an adhesive film, etc. The support ring 410 can be a material such as metal, but other materials can be used. In some cases, an outer edge of the support ring 410 can be flush with the sidewalls of the bonded structure 300.

[0066] Turning to Figure 15 , according to some embodiments, a package 500 is shown. The package 500 can be, for example, a package-on-package (PoP) structure, and can be formed as Figure 15The package 500 is connected to the package substrate 600. In some embodiments, the package 500 is formed by a first package assembly 510 bonded to the second package assembly 540. The first package assembly 510 may include one or more integrated circuit dies 512 and one or more through-holes 516 connected to the redistribution structure 514. The integrated circuit die 512 may be similar to the previously described semiconductor device 450. The first package assembly 510 includes contacts 518 located on the redistribution structure 514 for connection to the package substrate 600; and contacts 520 located on the through-holes 516 for connection to the second package assembly 540. The second package assembly 540 may include one or more integrated circuit dies 542, which may be similar to the previously described integrated circuit die 512 or semiconductor device 450, and may be as follows: Figure 15 The components are stacked as shown. The second package assembly 540 includes contacts 544 for connection to the first package assembly 510.

[0067] like Figure 15 As shown, connector 522 can be used to bond contacts 520 of the first package assembly 510 to contacts 544 of the second package assembly 540, and connector 622 can be used to bond contacts 518 of the first package assembly 510 to contacts 602 of the package substrate 600. In some embodiments, connector 522 and / or connector 622 can be formed in a manner similar to connector 222 previously described. For example, connector 622 can be formed by the following steps: forming areas of LT paste on contacts 602 of the package substrate 600, forming solder bumps on contacts 518 of the first package assembly, placing solder bumps on corresponding areas of LT paste, and then performing LT reflow 130 and HT reflow 132 to melt the LT paste and solder bumps into connector 622. The connector 522 can be formed in a similar manner, such as by forming an area of ​​LT paste on the contact 544 and forming solder balls on the contactor 520, and then performing LT reflow 130 and HT reflow 132 to form the connector 522. LT paste and solder bumps for forming the connector 522 and / or connector 622 can be formed on contact pads opposite to those in the given example. In this way, using the bonding techniques described herein, warpage between the various bonding components of the package 500 can be reduced. The package 500 is intended as an illustrative example, and other package reduction or bonding structures using the techniques described herein are considered to be within the scope of the invention.

[0068] Other components and processes can also be included in various embodiments described herein. For example, test structures can be included to assist in verification testing of 3D packages or 3DIC devices. Test structures can include, for example, test pads formed in redistribution layers or on substrates that allow testing of 3D packages or 3DICs using probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. Additionally, the structures and techniques disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0069] By utilizing the embodiments described herein, performance of device packages can be improved, and reliability of device packages can be improved. Different components of the embodiments described herein can be combined to achieve these and other benefits. In some cases, using connections formed from low temperature solder paste and solder balls that are connected by the described low temperature reflow and subsequent high temperature reflow can improve the conductivity and reliability of electrical connections between bonded structures. In some cases, the techniques described herein can be performed in a process flow with other typical manufacturing processes, and thus can add little or no additional cost to existing processes. The techniques described herein are also applicable to bonding various structures to form different types of packages. Additionally, using the described process techniques can result in improved yield and improved connection reliability, particularly for packages having larger areas. For example, the process techniques described herein can reduce warpage, and thus also reduce problems such as cracking or delamination associated with warpage.

[0070] In some embodiments, a method includes forming a redistribution structure, the redistribution structure including a first metallization pattern on a first side of the redistribution structure; forming an interconnect structure, the interconnect structure including a second metallization pattern on a first side of the interconnect structure; bonding the interconnect structure to the redistribution structure including: depositing a solder paste on the first metallization pattern, wherein the solder paste is a first material; forming a solder ball on the second metallization pattern, wherein the solder ball is a second material different from the first material; placing the solder ball in physical contact with the solder paste; performing a first reflow process at a first temperature at which the solder paste is melted; and after performing the first reflow process, performing a second reflow process at a second temperature at which the solder paste is melted and the solder ball is melted, wherein the second temperature is greater than the first temperature; and after performing the second reflow process, depositing an underfill between the redistribution structure and the interconnect structure. In embodiments, the solder paste includes tin and bismuth. In embodiments, the solder ball is bismuth-free. In embodiments, the first temperature is between 140 °C and 180 °C. In embodiments, the second temperature is between 210 °C and 250 °C. In embodiments, the method includes connecting a semiconductor device to a second side of the redistribution structure. In embodiments, performing the first reflow process forms a temporary connection between the first metallization pattern and the second metallization pattern, wherein the temporary connection includes a region of the first material bonded to a region of the second material. In embodiments, performing the second reflow process forms a connection between the first metallization pattern and the second metallization pattern, wherein the connection has a homogeneous composition. In embodiments, the connection has between 4% and 20% bismuth by mass. In embodiments, after performing the second reflow process, a warpage of the interconnect structure is less than 1400 pm.

[0071] In some embodiments, a method includes forming a region of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming a solder bump on an interconnect structure, wherein the solder bump has a second melting temperature greater than the first melting temperature; placing the solder bump on the region of solder paste; performing a first reflow process at a first reflow temperature for a first duration, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration, wherein the second reflow temperature is greater than the second melting temperature. In embodiments, a mass ratio of the region of solder paste to the solder bump is between 1 :8 and 1 : 16. In embodiments, the first duration is between 100 seconds and 200 seconds. In embodiments, the second duration is between 50 seconds and 80 seconds. In embodiments, the interconnect structure includes an organic substrate. In embodiments, a ratio of a width of the region of solder paste to a width of the solder bump is between 1 :2 and 1 :4.

[0072] In some embodiments, a method of forming a semiconductor package includes depositing a solder paste on a first contact pad of a first package component, wherein the solder paste includes bismuth; depositing a solder material on a second contact pad of a second package component, wherein the solder material is free of bismuth; performing a first heating process at a first temperature, the first heating process joining the solder paste to the solder material, wherein the solder material remains solid during the first heating process; and after performing the first heating process, performing a second heating process at a second temperature that melts the solder paste and the solder material to form a joint joining the first contact pad and the second contact pad. In embodiments, the second temperature is between 30 °C and 70 °C greater than the first temperature. In embodiments, a mass percentage of the bismuth of the solder paste is between 35% and 58%. In embodiments, the first temperature is less than 180 °C.

[0073] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the aspects of the application. Those skilled in the art should appreciate that they can readily use the application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the application, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the application.

Claims

1. A method for forming a semiconductor package, comprising: A redistribution structure is formed, the redistribution structure including a first metallization pattern located on a first side of the redistribution structure; An interconnect structure is formed, the interconnect structure including a second metallization pattern located on a first side of the interconnect structure; Joining the interconnect structure to the redistribution structure includes: Solder paste is deposited on the first metallization pattern, wherein the solder paste is a first material; Solder bumps are formed on the second metallization pattern, the solder bumps being physically and electrically connected to the second metallization pattern, wherein the solder bumps are a second material different from the first material, and wherein forming the solder bumps includes performing a first reflow process to produce the solder bumps; The solder bump is positioned to make physical contact with the solder paste; A second reflow process is performed at a first temperature that melts the solder paste and transforms it into a solder support structure. This second reflow process physically couples the solder bumps of the interconnect structure to the redistributed structure via the solder support structure. After performing the second reflow process, a third reflow process is performed at a second temperature that melts the solder support structure and the solder bumps together, wherein the second temperature is greater than the first temperature, and wherein the third reflow process forms a connector between the first metallization pattern and the second metallization pattern; and After performing the third reflow process, a bottom filler is deposited between the redistribution structure and the interconnect structure.

2. The method according to claim 1, wherein, The solder paste comprises tin and bismuth.

3. The method according to claim 1, wherein, The solder bumps are bismuth-free.

4. The method according to claim 1, wherein, The first temperature is between 140°C and 180°C.

5. The method according to claim 1, wherein, The second temperature is between 210°C and 250°C.

6. The method of claim 1, further comprising connecting a semiconductor device to a second side of the redistribution structure.

7. The method according to claim 1, wherein, The bottom filler extends toward the interconnect structure and completely covers the sidewalls of the interconnect structure.

8. The method according to claim 1, wherein, The second reflow process is performed to form a connector between the first metallization pattern and the second metallization pattern, wherein the connector has a homogeneous composition.

9. The method according to claim 8, wherein, The connector contains between 4% and 20% bismuth by weight.

10. The method according to claim 1, wherein, After performing the second reflow process, the warpage of the interconnect structure is less than 1400 μm.

11. A method of forming a semiconductor package, comprising: Multiple regions of solder paste are formed on the redistribution structure, wherein the solder paste has a first melting temperature; Multiple solder bumps are formed on the interconnect structure, wherein the solder bumps have a second melting temperature greater than the first melting temperature, and wherein the solder bumps are formed by a first reflow process; The plurality of solder bumps are placed on the plurality of regions of the solder paste, and the plurality of solder bumps are fixed to the interconnect structure; A second reflow process is performed for a first duration at a first reflow temperature, wherein the first reflow temperature is lower than the second melting temperature. The second reflow process reflows the plurality of regions of the solder paste, thereby attaching the plurality of solder bumps of the interconnect structure to the redistribution structure, and transforming the plurality of regions of the solder paste into a plurality of solder support structures; and After performing the second reflow process, the second reflow process is performed for a second duration at a third reflow temperature, wherein the second reflow temperature is greater than the second melting temperature, and the third reflow process melts the corresponding bumps of the plurality of solder bumps together with the corresponding solder support structures of the plurality of solder support structures.

12. The method according to claim 11, wherein, The mass ratio of the solder paste area to the solder bump is between 1:8 and 1:

16.

13. The method according to claim 11, wherein, The first duration is between 100 seconds and 200 seconds.

14. The method according to claim 11, wherein, The second duration is between 50 and 80 seconds.

15. The method according to claim 11, wherein, The interconnect structure includes an organic substrate.

16. The method according to claim 11, wherein, The ratio of the width of the solder paste area to the width of the solder bump is between 1:2 and 1:

4.

17. A method of forming a semiconductor package, comprising: Solder paste is deposited on the first contact pad of the first package assembly, wherein the solder paste comprises bismuth; Solder material is deposited on the second contact pad of the second package assembly, wherein the solder material is free of bismuth, and the solder material is attached to the second contact pad of the second package assembly by a first reflow process; A second reflow process, including a first heating process, is performed at a first temperature, which melts the solder paste and transforms it into a solder joint structure that bonds the solder material to a first contact pad of the first package assembly. The solder material remains solid during the first heating process, thereby coupling the second package assembly to the first package assembly through the solder material, with an interface remaining between the solder material and the solder joint structure. After performing the first heating process, a third reflow process including the second heating process is performed at a second temperature, the second temperature melting the solder bonding structure and the solder material to form a connector that bonds the first contact pad and the second contact pad together.

18. The method according to claim 17, wherein, The second temperature is between 30°C and 70°C higher than the first temperature.

19. The method of claim 17, wherein, The bismuth mass percentage of the solder paste is between 35% and 58%.

20. The method of claim 17, wherein, The first temperature is less than 180°C.

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