A method for measuring the parasitic resistance of a deep trench capacitor

Abstract

The present invention discloses a method for measuring the parasitic resistance of a deep trench capacitor, which includes the following steps: Step S1, symmetrically open windows on both sides of the positive terminal electrode of the deep trench capacitor to form a first test point (P1) and a second test point (P2), and open a window on the GND electrode of the deep trench capacitor to form a ground test point (GND); Step S2, connect a test device and the deep trench capacitor through the first test point (P1), the second test point (P2), and the ground test point (GND), measure the S-parameters of the deep trench capacitor, and record the test results; Step S3, according to circuit theory, perform a transformation from S-parameters to Z-parameters to obtain the Z-parameters of the deep trench capacitor, thereby obtaining the parasitic resistance of the deep trench capacitor.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to a method for accurately measuring the parasitic resistance of a deep trench capacitor (DTC). Background Art

[0002] Figure 1a FIG. 9 is a cross-sectional view of a deep trench capacitor (DTC) in the prior art. Specifically, the deep trench capacitor (DTC) is composed of a first conductor 10, a second conductor 20, a third conductor 30, a fourth conductor 40, a plurality of metal silicides 50, a substrate 60, and a dielectric material between the conductors. When generating the DTC, two deep trenches are first formed on the substrate 60, and then the fourth conductor 40, the dielectric material, the third conductor 30, the dielectric material, the second conductor 20, the dielectric material, and the first conductor 10 are sequentially formed in the deep trenches.

[0003] Specifically, the fourth conductor 40 is formed along the edges of the two deep trenches, and metal silicides 50 are formed on both sides thereof. Dielectric materials are formed in other regions on the surface of the fourth conductor 40; the third conductor 30 is formed on the dielectric material, and metal silicides 50 are formed in the middle of the third conductor 30. Dielectric materials are formed in other regions on the surface of the third conductor 30; then two second conductors 20 are formed along the two deep trenches on the dielectric material on the surface of the third conductor 30, and metal silicides 50 are formed outside the two second conductors 20. Then dielectric materials are formed in other regions on the two second conductors 20; finally, the first conductor 10 is formed on the dielectric materials on the two second conductors and in the two deep trenches, and metal silicides 50 are formed on the first conductor 10; the metal silicides 50 on one side of the fourth conductor 40 and the metal silicides 50 on the second conductor 20 on the same side are respectively connected to the first metal layer M1 through vias Via and connected together, and then connected to the second metal layer M2 through vias Via, and finally the GND electrode on one side of the DTC is led out at M2; the metal silicides 50 on the other side of the fourth conductor 40 and the metal silicides 50 on the second conductor 20 on the same side are respectively connected to the first metal layer M1 through vias Via and connected together, and then connected to the second metal layer M2 through vias Via, and finally the GND electrode on the other side of the DTC is led out at M2; the metal silicides 50 on the third conductor 30 and the metal silicides 50 on the first conductor are connected to the first metal layer M1 through vias Via and connected together, and then connected to the second metal layer M2 through vias Via, and finally the positive terminal electrode PORT1 of the DTC is led out at M2.

[0004] Generally, the first conductor 10, the second conductor 20, and the third conductor 30 are doped polysilicon. The dielectric material between the polysilicon is generally silicon dioxide (SiO2) or silicon dioxide containing nitrogen element (N). The fourth conductor 40 is the substrate material of a doped silicon wafer. The metal silicide 50 is a contact electrode, and generally silicide is used (TiSi or CoSi in an 8-inch wafer fab, and NiSi is usually used in a 12-inch wafer fab). The substrate 60 is a silicon wafer, which is the initial material used by the wafer fab. For back-end wiring, in an 8-inch wafer fab, generally tungsten is used as the via material and aluminum is used as the metal wiring. In a 12-inch wafer fab, copper or tungsten is used as the via material and copper is used as the metal wiring.

[0005] Figure 1b is the equivalent circuit of the deep trench capacitor DTC, which includes an equivalent series resistance ESR, an equivalent series inductance ESL, and a capacitor C. As is well known, the equivalent series resistance ESR and the equivalent series inductance ESL of a capacitor have a great impact on its electrical performance. The materials and processes of an integrated circuit determine that the resistivity of the conductor materials used inside is relatively large. When designing, designers need to consider the equivalent series resistance ESR and the equivalent series inductance ESL while caring about the capacitor C.

[0006] When measuring the DTC in the prior art, it is generally completed in two steps. First, use a probe card to measure the impedance Z(DTC) of a normal DTC, and then measure the impedance Z(short) of a short-circuited DTC. The difference between the two results is the impedance of the capacitor C: Z(DTC) - Z(short). Using the prior art, the measured ESR (the lowest impedance point) is 0.5 - 0.12 Ω, and the contact resistance of a general probe card (Contact Resistance For RF probe) is 0.05 - 1 Ω.

[0007] Figure 2a is the measurement result of the prior art. The upper part is the impedance Z(DTC) curve of the DTC, the lower "xx" connection is the Z(DTC) - Z(short) curve (the lowest point is the ESR), and the upper small box connection is Z(DTC). Figure 2b is the impedance / ESR results (box, circle, small cross connections) measured for the same device at different times. The impedance on the left is 0.12 Ω, the highest on the right is 0.5 Ω, and there is a depression in the middle. The lowest point is the ESR. The measured value of the ESR is close to the contact resistance of the probe card. Since the contact resistance is different each time when using the probe card for testing, the measured values at different times vary greatly. Summary of the Invention

[0008] To overcome the deficiencies of the above-mentioned existing technologies, the purpose of the present invention is to provide a method for measuring the parasitic resistance of a deep trench capacitor, so as to achieve the purpose of accurately measuring the parasitic resistance of the deep trench capacitor and effectively avoid the error introduced by the probe.

[0009] To achieve the above and other purposes, the present invention proposes a method for measuring the parasitic resistance of a deep trench capacitor, including the following steps:

[0010] Step S1: Symmetrically open windows on both sides of the positive terminal electrode of the deep trench capacitor to form a first test point (P1) and a second test point (P2). Open windows on the two GND electrodes of the deep trench capacitor to form a first ground test point and a second ground test point respectively, and form a third ground test point at the midpoint between the first test point (P1) and the second test point (P2).

[0011] Step S2: Connect the test equipment and the deep trench capacitor through the first test point (P1), the second test point (P2) and the three ground test points, measure the S parameters of the deep trench capacitor, and record the test results.

[0012] Step S3: According to circuit theory, perform a transformation from S parameters to Z parameters to obtain the Z parameters of the deep trench capacitor, thereby obtaining the parasitic resistance of the deep trench capacitor.

[0013] Preferably, the circuit between the first test point (P1) and the positive terminal electrode includes a first equivalent series resistance (P1R) and a first equivalent series inductance (P1L) connected in series, which are used to simulate the circuit network between the first test point (P1) and the positive terminal electrode of the deep trench capacitor. The circuit between the second test point (P2) and the positive terminal electrode includes a second equivalent series resistance (P2R) and a second equivalent series inductance (P2L) connected in series, which are used to simulate the circuit network between the second test point (P2) and the positive terminal electrode of the deep trench capacitor. The circuit between the positive terminal electrode and the ground includes an equivalent series resistance (ESR), an equivalent series inductance (ESL) and a capacitor (C) connected in series, which are used to simulate the circuit network from the positive terminal electrode of the deep trench capacitor to the ground.

[0014] Preferably, the third ground test point is connected to the first ground test point and the second ground test point through the shortest path.

[0015] Preferably, the third ground test point is directly connected to the first ground test point and the second ground test point through metal.

[0016] Preferably, in step S2, a 5-contact pin card is used to connect the test equipment and the deep trench capacitor.

[0017] Preferably, the outermost probes of the 5-contact pin card are connected to the first ground test point and the second ground test point on the two GND electrodes of the deep trench capacitor, the second and fourth probes are connected to the first test point (P1) and the second test point (P2) of the deep trench capacitor, and the middle third probe is connected to the third ground test point between the first test point (P1) and the second test point (P2). The other side of the 5-contact pin card is connected to the test equipment.

[0018] Preferably, in step S3, the Z parameter of the deep trench capacitor is obtained by performing the transformation Z = S2Y(S) from the S parameter to the Z parameter.

[0019] Preferably, the five test points are symmetrically arranged.

[0020] Compared with the prior art, the method for measuring the parasitic resistance of a deep trench capacitor in the present invention can achieve the purpose of accurately measuring the parasitic resistance of the deep trench capacitor and effectively avoid the error introduced by the probe. Description of the Drawings

[0021] Figure 1a is a cross-sectional view of a deep trench capacitor DTC in the prior art;

[0022] Figure 1b is the equivalent circuit of the deep trench capacitor DTC;

[0023] Figure 2a is the measurement result of the prior art;

[0024] Figure 2b is the ESR result of measuring the same device at different times;

[0025] Figure 3 is the step flow chart of the method for measuring the parasitic resistance of a deep trench capacitor in the present invention;

[0026] Figure 4a is the schematic diagram of the present invention;

[0027] Figure 4b is the cross-sectional view of the DTC of the present invention and the schematic diagram of the test contacts;

[0028] Figure 5a 、 Figure 5b are the measured diagram and the simulation diagram of a certain DTC device in the embodiment of the present invention. Detailed Embodiment

[0029] The following describes the embodiments of the present invention through specific specific examples in combination with the drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 3 This is the step flowchart of a method for measuring the parasitic resistance of a deep trench capacitor in the present invention. As Figure 3 shown, a method for measuring the parasitic resistance of a deep trench capacitor in the present invention includes the following steps:

[0031] Step S1, symmetrically open windows on both sides of the positive terminal electrode of the deep trench capacitor DTC to form a first test point P1 (Port1) and a second test point P2 (Port2), open windows on the left and right GND electrodes of the deep trench capacitor DTC to form a first ground test point GND and a second ground test point GND, and form a third ground test point at the midpoint between P1 and P2.

[0032] Figure 4a This is the schematic diagram of the present invention. P1 and P2 are two ports, and the middle node P0 is the positive terminal electrode Port1 of the deep trench capacitor DTC. The circuit between P1 and P0 (the series-connected first equivalent series resistance P1R and first equivalent series inductance P1L) is used to simulate the circuit network (instrument test cable, first probe and its contact resistance) between the first port P1 (Port1) and the positive terminal electrode Port1 of the DTC; the circuit between P2 and P0 (the series-connected second equivalent series resistance P2R and second equivalent series inductance P2L) is used to simulate the circuit network (instrument test cable, fifth probe and its contact resistance) between the second port P2 (Port2) and the positive terminal electrode Port1 of the DTC; the circuit between the middle node P0 and the ground (GND) (the series-connected equivalent series resistance ESR, equivalent series inductance ESL, and capacitor C) is used to simulate the circuit network (actual DTC) from the positive terminal electrode Port1 of the DTC to the ground.

[0033] Figure 4b This is the cross-sectional view of the DTC and the schematic diagram of the test contacts in the present invention. Symmetrically open windows on both sides of the positive terminal electrode of the deep trench capacitor DTC to form a first test point P1 (Port1) and a second test point P2 (Port2), open windows on the left and right GND electrodes of the DTC to form two ground test points, namely the first ground test point and the second ground test point, form a third ground test point at the midpoint between the first test point P1 (Port1) and the second test point P2 (Port2) and connect it to the first ground test point and the second ground test point on the GND electrode by the shortest path. The 5 test points formed are GND, P1, GND, P2, GND in sequence and are symmetrically arranged.

[0034] Step S2, connect the test equipment and the device under test (deep trench capacitor DTC) for measurement, and measure the S parameters of the two-port device under test (device under test DTC) (Measure Two Port S parameters S)

[0035] In the present invention, a 5-contact pin card is used to connect a test device to a deep trench capacitor (DTC). During testing, the outermost probes of the 5-contact pin card are connected to the two GND electrodes of the DTC, namely the first ground test point and the second ground test point. The second and fourth probes are connected to both sides of the positive terminal electrode (on the second metal M2) of the DTC, and the middle third probe is connected to the middle third ground test point (GND). The other side of the 5-contact pin card is connected to the test device.

[0036] That is to say, the present invention uses this 5-contact pin card to measure the S parameters (Measure Two Port S parameters S) of the two-port device under test (DTC under test), and records the test results:

[0037]

[0038] Since the measurement of S parameters is a function of the test device itself, it will not be elaborated here.

[0039] Step S3, according to circuit theory, perform the transformation from S parameters to Z parameters Z = S2Y(S) to obtain the Z parameters of the two-port device (DTC under test):

[0040]

[0041] Among them,

[0042]

[0043]

[0044]

[0045]

[0046] Among them, Z0 is the characteristic impedance.

[0047] According to circuit theory, Figure 4a Z12 of the Z parameters of the shown circuit network is the equivalent circuit of the deep trench capacitor DTC (ω is the angular frequency):

[0048] Z12 = ESR + jω * ESL + 1 / (jω * C)

[0049] Figure 5a 、 Figure 5bThis is the measured and simulated graphs of a certain DTC device in an embodiment of the present invention (DTC design values: ESR = 0.06, ESL = 29 pH, C = 200 nF). According to the measurement data, the |Z| parameter frequency curve (Plot |Z| (Z12 or Z21) vs Frequency) is formed, as Figure 5a , and the lowest point of the curve (Lowest Point) is the equivalent series resistance ESR of the DTC; Figure 5b are the simulation curves when R1 / R2 are 0.5 / 0.5, 0.1 / 0.1, and 0.1 / 0.5 respectively (R1 is the contact resistance of the probe connected to the first test point P1, and R2 is the contact resistance of the probe connected to the second test point P2). Although the contact resistances are different, the three simulation curves coincide, indicating that the method of the present invention has good effects.

[0050] After testing, when using the method shown in the present invention to measure the DTC parameters, the obtained ESR is 0.005 - 0.15 Ω. The simulation data and the measured data are relatively consistent, significantly superior to the measurement data of the prior art, and effectively avoiding the parasitic parameters and uncertainty errors introduced by the probes.

[0051] The above embodiments are only illustrative of the principles and effects of the present invention, rather than limiting the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the present invention shall be as listed in the claims.

Claims

1. A method for measuring the parasitic resistance of a deep trench capacitor, comprising the following steps: Step S1, symmetrically open windows on both sides of the positive terminal electrode of the deep trench capacitor to form a first test point (P1) and a second test point (P2), open windows on the two GND electrodes of the deep trench capacitor respectively to form a first ground test point and a second ground test point, and form a third ground test point at the midpoint between the first test point (P1) and the second test point (P2); Step S2, connect a test device and the deep trench capacitor through the first test point (P1), the second test point (P2) and the three ground test points, measure the S parameters of the deep trench capacitor, and record the test results; Step S3, according to circuit theory, perform a transformation from S parameters to Z parameters to obtain the Z parameters of the deep trench capacitor, thereby obtaining the parasitic resistance of the deep trench capacitor.

2. The method for measuring the parasitic resistance of a deep groove capacitor according to claim 1, wherein: The circuit between the first test point (P1) and the positive terminal electrode includes a first equivalent series resistance (P1R) and a first equivalent series inductance (P1L) connected in series, which is used to simulate the circuit network between the first test point (P1) and the positive terminal electrode of the deep trench capacitor. The circuit between the second test point (P2) and the positive terminal electrode includes a second equivalent series resistance (P2R) and a second equivalent series inductance (P2L) connected in series, which is used to simulate the circuit network between the second test point (P2) and the positive terminal electrode of the deep trench capacitor. The circuit between the positive terminal electrode and the ground includes an equivalent series resistance (ESR), an equivalent series inductance (ESL) and a capacitor (C) connected in series, which is used to simulate the circuit network from the positive terminal electrode of the deep trench capacitor to the ground.

3. A method for measuring the parasitic resistance of a deep trench capacitor as described in claim 2, characterized in that: The third ground test point is connected to the first ground test point and the second ground test point through the shortest path.

4. The method for measuring the parasitic resistance of a deep trench capacitor according to claim 3, wherein: The third ground test point is directly connected to the first ground test point and the second ground test point through metal.

5. The method for measuring the parasitic resistance of a deep trench capacitor according to claim 4, wherein: In step S2, a 5-contact pin card is used to connect the test device and the deep trench capacitor.

6. The method for measuring the parasitic resistance of a deep trench capacitor according to claim 5, wherein: The outermost probes of the 5-contact pin card are connected to the first ground test point and the second ground test point on the two GND electrodes of the deep trench capacitor. The second and fourth probes are connected to the first test point (P1) and the second test point (P2) of the deep trench capacitor. The middle third probe is connected to the third ground test point in the middle of the first test point (P1) and the second test point (P2). The other side of the 5-contact pin card is connected to the test device.

7. The method for measuring the parasitic resistance of a deep groove capacitor according to claim 6, characterized in that: In step S3, perform a transformation from S parameters to Z parameters Z = S2Y(S) to obtain the Z parameters of the deep trench capacitor.

8. A method for measuring the parasitic resistance of a deep groove capacitor as described in claim 1, characterized in that: The five test points are symmetrically arranged.

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