Semiconductor structure and method of manufacturing the same, three-dimensional device

Abstract

The application discloses a semiconductor structure and a preparation method thereof, and a three-dimensional device, and relates to the technical field of three-dimensional devices, and aims to provide a technical scheme of a via structure with low residual stress. The semiconductor structure comprises a semiconductor substrate, a spindle-shaped via structure formed in the semiconductor substrate, the spindle-shaped via structure comprising a plurality of spindle-shaped vias, a laminated structure formed on the sidewall of each spindle-shaped via, and a metal interconnection structure filled in each spindle-shaped via, wherein the metal interconnection structure is in contact with the laminated structure, the top and bottom of the metal interconnection structure have a solid structure, and the middle part of the metal interconnection structure has a vacuum hollow structure.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional device technology, and in particular to a semiconductor structure and its fabrication method, and a three-dimensional device. Background Technology

[0002] Three-dimensional stacking encapsulates multiple chips into a single unit using Through Silicon Via (TSV) interconnect technology. Currently, with the further increase in chip integration density, the number of TSVs used for vertical interconnects is also increasing. For integrated chips such as high-density memory and high-resolution image sensors, ultra-high-density TSVs are a key structure. This involves filling the TSVs with metal materials to achieve electrical interconnects. Due to the mismatch in thermal expansion coefficients between the metal and the substrate materials, which is generally significant, thermal stress exists within the TSV structure. Additionally, lattice mismatch stress arises during thin-film deposition. Typically, when the TSV aspect ratio reaches 10:1, most areas of the chip are affected by stress. Furthermore, when the TSV spacing is less than three times the diameter, the stress within the chip becomes very significant, often leading to various reliability issues.

[0003] Currently, in conventional TSV structures, the stress generated by metal deposition cannot be fully released, or the released stress is transferred to other areas of the device, which can easily lead to internal cracks or interface delamination, and may even cause chip breakage and malfunction. Furthermore, when the released stress is transferred to other areas of the chip, it may affect the performance of the semiconductor device. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor structure and its fabrication method, as well as a three-dimensional device, which provides a technical solution for a through-hole structure with low residual stress.

[0005] In a first aspect, the present invention provides a semiconductor structure for use in a three-dimensional device, the semiconductor structure comprising: a semiconductor substrate; a spindle-shaped via structure formed therein, the spindle-shaped via structure comprising a plurality of spindle-shaped vias; a stacked structure formed on the sidewalls of the spindle-shaped vias; and a metal interconnect structure filling each of the spindle-shaped vias, wherein the metal interconnect structure is in contact with the stacked structure, the top and bottom of the metal interconnect structure have solid structures, and the middle portion of the metal interconnect structure has a vacuum hollow structure.

[0006] Compared with existing technologies, the present invention provides a semiconductor structure comprising a semiconductor substrate in which a spindle-shaped via structure is formed, wherein the spindle-shaped via structure includes multiple spindle-shaped vias. It should be understood that the structure of the spindle-shaped vias is characterized by small dimensions at both ends and a large dimension in the middle. Based on this, after uniformly forming a stacked structure on the sidewalls of each spindle-shaped via, a metal interconnect structure is then filled into each spindle-shaped via. The top and bottom of the metal interconnect structure are solid, and the middle portion of the metal interconnect structure is a vacuum hollow structure. The metal interconnect structure in the present invention fills the openings at both ends of the corresponding spindle-shaped vias, which not only ensures that impurities are not introduced into the TSV structure during subsequent processes, avoiding subsequent contamination, but also allows the subsequent manufacturing processes to still use conventional integrated circuit processing techniques, reducing manufacturing difficulty.

[0007] Furthermore, the vacuum hollow structure in the middle of the metal interconnect structure prevents additional thermal expansion during processing, thus avoiding additional thermal stress problems. Moreover, this vacuum hollow structure provides a release space for the stress generated during the deposition of the metal interconnect structure, avoiding the inadequate stress release or stress transfer to other areas of the device, which is common in existing technologies. It also avoids thermal stress caused by temperature changes during subsequent processes, which can easily lead to internal cracks or interface delamination, and even chip breakage and malfunction. Additionally, the transfer of stress to other areas of the chip after stress release can affect the performance of semiconductor devices. Furthermore, the effective stress release within the spindle-shaped via structure enables the realization of ultra-high density spindle-shaped via structures.

[0008] Finally, the semiconductor structure provided by this invention has a simple manufacturing process, high reliability, compatibility with CMOS manufacturing processes, and is easy to use in mass production processes.

[0009] Preferably, along the direction from the sidewall of the spindle-shaped through-hole to the center, the laminated structure includes a second insulating dielectric layer, an adhesive layer, and a barrier layer.

[0010] Preferably, the thickness of the adhesive layer ranges from 0.005 μm to 2 μm, and the thickness of the barrier layer ranges from 0.005 μm to 2 μm.

[0011] Preferably, the second insulating dielectric layer comprises a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a stack formed by any two of the silicon oxide layer, the silicon nitride layer, and the aluminum oxide layer;

[0012] And / or, the adhesive layer includes a titanium layer or a tantalum layer;

[0013] And / or, the barrier layer includes a titanium nitride layer, a tantalum nitride layer, or a stack of titanium nitride and tantalum nitride layers.

[0014] Preferably, the material of the metal interconnect structure is copper, tungsten, copper alloy, or tungsten alloy.

[0015] Preferably, the semiconductor structure further includes a first insulating layer formed on the bottom surface of the semiconductor substrate; the first insulating layer has a plurality of insulating vias communicating with the corresponding spindle-shaped vias, wherein the insulating vias are used to expose at least the metal interconnect structure within the corresponding spindle-shaped via.

[0016] Secondly, the present invention also provides a three-dimensional device, the three-dimensional device comprising the above-described semiconductor structure.

[0017] Thirdly, the present invention also provides a method for preparing a semiconductor structure, the method comprising the following steps:

[0018] A semiconductor substrate is prepared; a spindle-shaped via structure is formed in the semiconductor substrate, the spindle-shaped via structure comprising a plurality of spindle-shaped vias;

[0019] A layered structure is formed on the sidewall of the spindle-shaped through hole;

[0020] Each spindle-shaped through-hole is filled with metal material to form a metal interconnect structure; wherein the metal interconnect structure is in contact with the stacked structure, the top and bottom of the metal interconnect structure are solid structures, and the middle part of the metal interconnect structure is a vacuum hollow structure.

[0021] Preferably, the preparation of the semiconductor substrate includes:

[0022] Provide semiconductor substrates;

[0023] A hard mask layer is formed on the semiconductor substrate;

[0024] A first photolithographic pattern is formed on the hard mask layer to obtain a first photolithographic pattern layer;

[0025] Using the first photolithography layer as a mask, under the first etching condition, the first part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate; under the second etching condition, the second part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate; and under the third etching condition, the third part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate to obtain a spindle-shaped through-hole structure.

[0026] Preferably, the first etching conditions include: the ratio of etching gas to passivating gas is 1:1, and the reflected power is a first power; the second etching conditions include: the ratio of etching gas to passivating gas is 1:0.5, and the reflected power is a second power; the second etching conditions include: the ratio of etching gas to passivating gas is 1:1.5, and the reflected power is a second power; wherein, the second power is greater than the first power. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0028] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a spindle-shaped through hole provided in an embodiment of the present invention;

[0030] Figure 3 This is a three-dimensional schematic diagram of a spindle-shaped through-hole structure on a substrate provided by an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure after forming a stacked structure and a metal interconnect structure in a spindle-shaped through hole, as provided in an embodiment of the present invention;

[0032] Figures 5-8 This is a schematic diagram of the various stages in a semiconductor structure fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0033] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0036] Three-dimensional stacking encapsulates multiple chips into a single unit using Through Silicon Via (TSV) interconnect technology. Currently, with the further increase in chip integration density, the number of TSVs used for vertical interconnects is also increasing. For integrated chips such as high-density memory and high-resolution image sensors, ultra-high-density TSVs are a key structure. This involves filling the TSVs with metal materials to achieve electrical interconnects. Due to the mismatch in thermal expansion coefficients between the metal and the substrate materials, which is generally significant, thermal stress exists within the TSV structure. Additionally, lattice mismatch stress arises during thin-film deposition. Typically, when the TSV aspect ratio reaches 10:1, most areas of the chip are affected by stress. Furthermore, when the TSV spacing is less than three times the diameter, the stress within the chip becomes very significant, often leading to various reliability issues.

[0037] Currently, in conventional TSV structures, the stress generated by metal deposition cannot be fully released, or the released stress is transferred to other areas of the device, which can easily lead to internal cracks or interface delamination, and may even cause chip breakage and malfunction. Furthermore, when the released stress is transferred to other areas of the chip, it may affect the performance of the semiconductor device.

[0038] Based on this, firstly, referring to Figure 1 This invention provides a semiconductor structure for use in a three-dimensional device. The semiconductor structure includes: a semiconductor substrate 10; a spindle-shaped via structure formed in the semiconductor substrate 10, the spindle-shaped via structure including a plurality of spindle-shaped vias; a stacked structure 20 formed on the sidewalls of the spindle-shaped vias; and a metal interconnect structure 30 filling each of the spindle-shaped vias, wherein the metal interconnect structure is in contact with the stacked structure, the top and bottom of the metal interconnect structure 30 are both solid structures, and the middle portion of the metal interconnect structure 30 is a vacuum hollow structure.

[0039] Among them, reference Figure 1The aforementioned semiconductor substrate 10 includes a substrate 101 and a hard mask layer formed on the substrate 101. The substrate 101 can be a silicon substrate or a glass substrate. The hard mask layer is used to form a photolithographic pattern of a spindle-shaped through-hole structure. For example, the hard mask layer can be a silicon oxide thin film.

[0040] Reference Figure 2 and Figure 3 The diagrams show a schematic of a spindle-shaped through-hole and an example diagram of the spindle-shaped through-hole structure. It can be seen that the spindle-shaped through-hole in this embodiment of the invention has the characteristic of small diameters at both ends and a large diameter in the middle. (Refer to...) Figure 4 This diagram illustrates a structure formed in a spindle-shaped through-hole after the formation of a stacked structure and a metal interconnect structure. It shows that after the formation of the stacked structure and metal interconnect structure in the spindle-shaped through-hole, the top and bottom of the metal interconnect structure 30 filling the spindle-shaped through-hole are both solid structures, and the middle portion of the metal interconnect structure 30 has a vacuum hollow structure 301. Furthermore, along the direction from the wall of the spindle-shaped helmet hole to the center, the top and bottom of the spindle-shaped through-hole are sequentially formed with a stacked structure 20 (a second insulating dielectric layer 201, an adhesive layer 202, and a barrier layer 203) and a metal interconnect structure 30. It should be understood that the spindle-shaped through-hole and the structure formed in the spindle-shaped through-hole provided in this embodiment are not limited to the above description. Figures 2-4 The structure shown.

[0041] Based on this, the metal interconnect structure 30 in the embodiment of the present invention fills the openings at both ends of the corresponding spindle-shaped through hole to form a solid structure. This not only ensures that impurities are not introduced into the spindle-shaped through hole structure in subsequent processes, thus avoiding the occurrence of other contamination, but also allows the subsequent manufacturing process to still use conventional integrated circuit processing technology, reducing the manufacturing difficulty.

[0042] Furthermore, the vacuum hollow structure in the middle portion of the metal interconnect structure 30 prevents additional thermal expansion during processing, thus avoiding additional thermal stress problems. This vacuum hollow structure also provides space for stress release during the deposition of the metal interconnect structure 20, avoiding the inadequate stress release or stress transfer to other areas of the device, common in existing technologies. It also avoids thermal stress caused by temperature changes during subsequent processes, which can easily lead to internal cracks or interface delamination, and even chip breakage and malfunction. Additionally, the transfer of stress to other areas of the chip after stress release can affect the performance of semiconductor devices. Moreover, the effective stress release within the spindle-shaped via structure enables the realization of ultra-high density spindle-shaped via structures.

[0043] Finally, the semiconductor structure provided by the embodiments of the present invention has a simple manufacturing process, high reliability, compatibility with CMOS manufacturing process, and is easy to use in mass production processes.

[0044] As an optional embodiment, the material of the above-mentioned metal interconnect structure may include copper, tungsten, copper alloy, or tungsten alloy.

[0045] It should be understood that the above-mentioned metal interconnect structure is used to realize electrical interconnection, and therefore, copper, tungsten, copper alloy or tungsten alloy can be used to realize it.

[0046] Furthermore, to prevent the metal interconnect structure at the bottom of the semiconductor structure from being exposed, the semiconductor structure provided in this embodiment of the invention further includes a first insulating layer forming the bottom surface of the semiconductor substrate. Even further, to achieve electrical interconnection between the bottom of the semiconductor and other structures, a plurality of insulating vias are formed in the first insulating layer, communicating to the corresponding spindle-shaped vias. These insulating vias are used to expose at least the metal interconnect structure within the corresponding spindle-shaped vias.

[0047] The first insulating layer includes a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a stack formed by at least two of the silicon oxide layer, silicon nitride layer, and aluminum oxide layer.

[0048] In this embodiment of the invention, the spindle-shaped vias provide a space for stress release during the deposition of the metal interconnect structure. This avoids the thermal stress that can easily occur in the spindle-shaped vias when filling them with metal material to achieve electrical interconnection, due to the mismatch and generally large difference in the thermal expansion coefficients between the metal and the substrate material. Furthermore, it also avoids the lattice mismatch internal stress caused by lattice mismatch during thin film deposition. Therefore, this embodiment of the invention provides a high-density spindle-shaped via structure with a large aspect ratio.

[0049] As an optional embodiment, the aspect ratio of each spindle-shaped through-hole in the spindle-shaped through-hole structure is less than or equal to 20:1; and / or, the arrangement density of the plurality of spindle-shaped through-holes in the spindle-shaped through-hole structure is less than or equal to 1.5 x 10⁻⁶. 5 .

[0050] For example, the aspect ratio of each spindle-shaped through-hole in the spindle-shaped through-hole structure is 20:1.

[0051] For example, the aspect ratio of each spindle-shaped through-hole in the spindle-shaped through-hole structure is 18:1.

[0052] For example, the arrangement density of the plurality of spindle-shaped through holes in the spindle-shaped through-hole structure is 1.5 x 10⁻⁶. 5 .

[0053] For example, the arrangement density of the plurality of spindle-shaped through holes in the spindle-shaped through-hole structure is 1.45 x 10⁻⁶. 5 .

[0054] In this embodiment of the invention, reference is made to Figure 1 Along the direction from the sidewall of the spindle-shaped through hole to the center, the above-mentioned stacked structure 20 includes a second insulating dielectric layer 201, an adhesive layer 202, and a barrier layer 203.

[0055] The second insulating dielectric layer comprises a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a stack formed by any two of the following: a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. The second insulating dielectric layer is used to insulate the metal interconnect structure from the substrate, preventing leakage between the metal interconnect structure and the substrate.

[0056] The adhesive layer, comprising a titanium or tantalum layer, is used to better adhere the metal interconnect structure to the second insulating dielectric layer. To minimize the size of the spindle-shaped vias, the thickness of the adhesive layer ranges from 0.005 μm to 2 μm. For example, the thickness of the adhesive layer is 0.005 μm, 0.5 μm, or 2 μm.

[0057] The barrier layer comprises a titanium nitride layer, a tantalum nitride layer, or a stack of titanium nitride and tantalum nitride layers, used to prevent the metal interconnect structure from affecting the second insulating layer and the silicon substrate. The thickness of the barrier layer ranges from 0.005 μm to 1 μm. For example, the barrier layer thickness is 0.005 μm, 0.6 μm, or 2 μm.

[0058] Secondly, embodiments of the present invention also provide a three-dimensional device, including the semiconductor structure described above.

[0059] Thirdly, embodiments of the present invention also provide a method for preparing a semiconductor structure, comprising the following steps:

[0060] Reference Figure 5 A semiconductor substrate 10 is prepared; a spindle-shaped via structure is formed in the semiconductor substrate 10, the spindle-shaped via structure including a plurality of spindle-shaped vias 50.

[0061] The preparation of the semiconductor substrate includes:

[0062] Provide a semiconductor substrate; wherein the semiconductor substrate may be a silicon substrate or a glass substrate.

[0063] A hard mask layer is formed on a semiconductor substrate; the hard mask layer can be formed on the semiconductor substrate by deposition, wherein the material of the hard mask layer is silicon oxide.

[0064] A first photolithographic pattern is formed on the hard mask layer to obtain a first photolithographic pattern layer. Forming the first photolithographic pattern on the hard mask layer may include: forming photoresist on the hard mask layer by spin coating, and forming the first photolithographic pattern on the hard mask layer through photolithography and etching processes.

[0065] Using the first photolithographic pattern layer as a mask, deep silicon etching is performed on the semiconductor substrate to obtain a spindle-shaped via structure, wherein the spindle-shaped via structure includes a plurality of spindle-shaped vias.

[0066] In one possible implementation, using the first photolithographic pattern layer as a mask to perform deep silicon etching on the semiconductor substrate to obtain a spindle-shaped via structure may include:

[0067] Using the first photolithography layer as a mask, under the first etching condition, the first part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate; under the second etching condition, the second part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate; and under the third etching condition, the third part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate to obtain a spindle-shaped through-hole structure.

[0068] The first etching condition includes a first ratio of etching gas to passivating gas and a first power for reflected light. The second etching condition includes a second ratio of etching gas to passivating gas and a second power for reflected light. The third etching condition includes a third ratio of etching gas to passivating gas and a third power for reflected light; wherein the first ratio is less than the second ratio, the third ratio is less than the second ratio, and the second power is greater than the first power.

[0069] Based on this, embodiments of the present invention adjust the dimensions of various portions of the spindle-shaped via structure by adjusting the ratio of etching gas to passivation gas and the reflection power during deep silicon etching. It should be understood that the first portion of the semiconductor substrate is used to form the top of the spindle-shaped via, the second portion is used to form the middle portion of the spindle, and the third portion is used to form the bottom of the spindle-shaped via. Specifically, when etching the first portion of the semiconductor substrate, the ratio of etching gas to passivation gas is relatively small, and the reflection power is also relatively small. At this time, etching of the top portion of the spindle-shaped via can be achieved. When etching the second portion of the semiconductor substrate, since the etching depth is deeper and the width of the via portion to be formed is wider, the ratio of etching gas to passivation gas can be increased, and the reflection power can be increased simultaneously. This allows for a larger size of the middle portion of the spindle-shaped via while accelerating the etching rate. When etching the third part of the semiconductor substrate, the etching depth is deeper, but the width of the via to be formed is narrower. At this time, the bottom morphology of the spindle-shaped via can be made to achieve a circular shape by increasing the proportion of passivation gas, that is, decreasing the ratio of etching gas to passivation gas, while keeping the reflection power unchanged, thereby reducing the bottom opening size of the spindle-shaped via.

[0070] It should be further understood that the top opening size of the spindle-shaped through hole and the bottom opening size of the spindle-shaped through hole can be the same or different, but both must be smaller than the size of the middle part of the spindle-shaped through hole.

[0071] In this embodiment of the invention, deep silicon etching can be performed on a semiconductor substrate using the Bosh process.

[0072] As a specific embodiment, the first ratio is 1:1 for etching gas and 1:0.5 for passivation gas, and the third ratio is 1:1.5 for etching gas and 1:1.5 for passivation gas.

[0073] Reference Figure 6 A layered structure 20 is formed on the sidewall of the spindle-shaped through hole.

[0074] Reference Figure 6 In the direction from the sidewall of the spindle-shaped through hole to the center, the stacked structure 20 includes a second insulating dielectric layer 201, an adhesive layer 202, and a barrier layer 203.

[0075] Specifically, forming a layered structure on the sidewall of the spindle-shaped through-hole includes:

[0076] A second insulating dielectric layer, an adhesive layer, and a barrier layer are sequentially formed on the sidewall of the spindle-shaped through-hole using enhanced chemical vapor deposition, atomic layer deposition, or enhanced chemical vapor deposition and atomic layer deposition.

[0077] The second insulating dielectric layer comprises a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a stack formed by any two of the following: a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. The second insulating dielectric layer is used to insulate the metal interconnect structure from the substrate, preventing leakage between the metal interconnect structure and the substrate.

[0078] The adhesive layer, including a titanium or tantalum layer, is used to better adhere the metal interconnect structure to the second insulating dielectric layer. It should be understood that, in order to minimize the size of the spindle-shaped vias, the thickness of the adhesive layer ranges from 0.005 μm to 2 μm. For example, the thickness of the adhesive layer could be 0.005 μm, 0.5 μm, or 2 μm.

[0079] The barrier layer comprises a titanium nitride layer, a tantalum nitride layer, or a stack of titanium nitride and tantalum nitride layers, used to prevent the metal interconnect structure from affecting the second insulating layer and the silicon substrate. The thickness of the barrier layer ranges from 0.005 μm to 2 μm. For example, the barrier layer thickness is 0.005 μm, 0.6 μm, or 2 μm.

[0080] Reference Figure 7 Each of the spindle-shaped through holes is filled with metal material to form a metal interconnect structure 30; wherein the metal interconnect structure is in contact with the stacked structure, the top and bottom of the metal interconnect structure are solid structures, and the middle portion of the metal interconnect structure has a vacuum hollow structure 301. It should be understood that... Figure 7 The shape of the vacuum hollow structure 301 in the diagram is only a schematic diagram and is not intended to specifically limit the vacuum hollow structure provided in the actual embodiment of the present invention.

[0081] Specifically, filling each of the spindle-shaped through holes with metal material to form a metal interconnect structure includes: filling each of the spindle-shaped through holes with metal material using chemical vapor deposition or electroplating until the metal material fills the top of each of the spindle-shaped through holes, thereby obtaining the metal interconnect structure.

[0082] The material of the aforementioned metal interconnect structure may include copper, tungsten, copper alloys, or tungsten alloys.

[0083] In one specific implementation, tungsten is filled into each of the spindle-shaped vias using chemical vapor deposition until the upper opening of the spindle-shaped via is completely filled, thus completing the deposition. The filled metal interconnect structure is then subjected to chemical mechanical polishing (CMP) to remove the surface adhesion layer, barrier layer, and metal interconnect layer, and to flatten the surface.

[0084] In another specific implementation, copper alloy is filled into each of the spindle-shaped vias using electroplating until the upper opening of the spindle-shaped via is completely filled, thus completing the deposition. The filled metal interconnect structure is then subjected to chemical mechanical polishing (CMP) to remove the surface adhesion layer, barrier layer, and metal interconnect layer, and to flatten the surface.

[0085] Better, refer to Figure 8 The method for preparing the above-mentioned semiconductor structure further includes:

[0086] A first insulating material layer 401 is formed on one side of the bottom surface of the substrate using plasma-enhanced chemical vapor deposition, atomic layer deposition, or a combination of plasma-enhanced chemical vapor deposition and atomic layer deposition.

[0087] The first insulating material layer is patterned to obtain a first insulating layer 40, in which a plurality of insulating through holes 402 are formed, which are connected to the corresponding spindle-shaped through holes.

[0088] The first insulating layer is used to prevent the metal interconnect structure at the bottom of the semiconductor structure from being exposed, and the insulating via is used to expose at least the metal interconnect structure within the corresponding spindle-shaped via.

[0089] It is worth noting that before forming the first insulating material layer on the bottom side of the substrate, the silicon substrate or glass substrate needs to be thinned to expose the bottom of the metal interconnect structure in the spindle-shaped via. The thinning process is preferably chemical mechanical polishing (CMP), wet etching, dry etching, or a combination thereof.

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, For use in three-dimensional devices, the semiconductor structure includes: A semiconductor substrate; the semiconductor substrate includes a substrate and a hard mask layer formed on the substrate; the hard mask layer is used to form a photolithographic pattern of a spindle-shaped via structure; the spindle-shaped via structure includes a plurality of spindle-shaped vias; each spindle-shaped via includes a lower portion, a middle portion and an upper portion from bottom to top, the diameter of the middle portion is larger than the diameters of the upper portion and the lower portion, the diameter of the upper portion gradually decreases from bottom to top, and the diameter of the lower portion gradually decreases from top to bottom; the aspect ratio of each spindle-shaped via is less than or equal to 20:1; A stacked structure is formed on the sidewall of each of the spindle-shaped through holes; the stacked structure includes a second insulating dielectric layer, an adhesive layer, and a barrier layer along the direction from the sidewall of the spindle-shaped through hole to the center; And a metal interconnect structure filling each of the spindle-shaped through holes; wherein the metal interconnect structure is spindle-shaped; the metal interconnect structure is in contact with the stacked structure, the top and bottom of the metal interconnect structure have solid structures, the middle part of the metal interconnect structure has a vacuum hollow structure; the top surface of the metal interconnect structure is flush with the top surface of the hard mask layer; The semiconductor structure further includes a first insulating layer formed on the bottom surface of the semiconductor substrate; the first insulating layer has a plurality of insulating vias communicating with the corresponding spindle-shaped vias, wherein the insulating vias are used to expose at least the metal interconnect structure within the corresponding spindle-shaped via.

2. The semiconductor structure according to claim 1, characterized in that, The thickness of the adhesive layer ranges from 0.005 μm to 2 μm, and the thickness of the barrier layer ranges from 0.005 μm to 2 μm.

3. The semiconductor structure according to claim 1, characterized in that, The second insulating dielectric layer includes a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a stack formed by any two of the silicon oxide layer, silicon nitride layer, and aluminum oxide layer; And / or, the adhesive layer includes a titanium layer or a tantalum layer; And / or, the barrier layer includes a titanium nitride layer, a tantalum nitride layer, or a stack of titanium nitride and tantalum nitride layers.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The material of the metal interconnect structure includes copper, tungsten, copper alloys, or tungsten alloys.

5. A three-dimensional device, characterized in that, Includes the semiconductor structure described in any one of claims 1-4.

6. A method for fabricating a semiconductor structure, characterized in that, Applied to the semiconductor structure according to any one of claims 1-4, the method for preparing the semiconductor structure includes the following steps: A semiconductor substrate is prepared; a spindle-shaped via structure is formed in the semiconductor substrate, the spindle-shaped via structure comprising a plurality of spindle-shaped vias; A layered structure is formed on the sidewall of the spindle-shaped through hole; Each spindle-shaped through-hole is filled with metal material to form a metal interconnect structure; wherein the metal interconnect structure is in contact with the stacked structure, the top and bottom of the metal interconnect structure are solid structures, and the middle part of the metal interconnect structure is a vacuum hollow structure.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The preparation of the semiconductor substrate includes: Provide semiconductor substrates; A hard mask layer is formed on the semiconductor substrate; A first photolithographic pattern is formed on the hard mask layer to obtain a first photolithographic pattern layer; Using the first photolithography layer as a mask, under the first etching condition, the first part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate; under the second etching condition, the second part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate; and under the third etching condition, the third part of the semiconductor substrate is etched along the depth direction of the semiconductor substrate to obtain a spindle-shaped through-hole structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The first etching condition includes: the ratio of etching gas to passivating gas is a first ratio, and the reflected power is a first power; the second etching condition includes: the ratio of etching gas to passivating gas is a second ratio, and the reflected power is a second power; the third etching condition includes: the ratio of etching gas to passivating gas is a third ratio, and the reflected power is a second power; wherein, the first ratio is less than the second ratio, the third ratio is less than the second ratio, and the second power is greater than the first power.

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