flash memory

Abstract

The present invention discloses a flash memory, comprising: a gate stack structure, a channel column, a first conductor column and a second conductor column with a gate dielectric layer. The gate stack structure comprises multiple gate layers electrically insulated from each other. Each gate layer comprises: a first gate portion, a second gate portion and a ferroelectric portion. The thickness of the second gate portion is less than the thickness of the first gate portion. The ferroelectric portion is arranged between the side wall of the first gate portion and the side wall of the second gate portion. The channel column runs through the gate stack structure. The first conductor column and the second conductor column are arranged in the channel column and run through the gate stack structure. The first conductor column and the second conductor column are separated from each other and are respectively connected to the channel column. The gate dielectric layer is arranged between the other side wall of the first gate portion and the channel column.

Description

Technical Field

[0001] The invention relates to a non-volatile memory and a manufacturing method thereof. Background Art

[0002] Non-volatile memory (eg, flash memory) has become a widely used memory in personal computers and other electronic devices because it has the advantage that the stored data will not disappear after power failure.

[0003] The three-dimensional flash memory commonly used in the industry at present includes NOR flash memory and NAND flash memory. In addition, another three-dimensional flash memory is AND flash memory, which can be used in multi-dimensional flash memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional flash memory has gradually become the current trend. Summary of the invention

[0004] The present invention provides a flash memory having a ferroelectric part and a double gate, which can avoid the large difference in dielectric constant between the ferroelectric part and the gate dielectric layer causing carriers to tunnel or be injected into the gate dielectric layer, thereby improving the efficiency of read and write operations.

[0005] The present invention provides a flash memory, comprising: a gate stack structure, a channel column, a first conductor column and a second conductor column with a gate dielectric layer. The gate stack structure comprises multiple gate layers electrically insulated from each other. Each gate layer comprises: a first gate portion; a second gate portion adjacent to a side wall of the first gate portion, wherein the thickness of the second gate portion is less than the thickness of the first gate portion; and a ferroelectric portion disposed between the side wall of the first gate portion and the side wall of the second gate portion. A channel column penetrates the gate stack structure. A first conductor column and a second conductor column are disposed in the channel column and penetrate the gate stack structure. The first conductor column and the second conductor column are separated from each other and are respectively connected to the channel column. A gate dielectric layer is disposed between the other side wall of the first gate portion and the side wall of the channel column.

[0006] The embodiment of the present invention also provides another flash memory, comprising: a gate stack structure, a second gate layer, a channel structure, a first gate dielectric layer and a second gate dielectric layer. The gate stack structure is disposed on a substrate. The gate stack structure comprises: a gate layer. The gate layer comprises: a first gate portion; a second gate portion adjacent to a side wall of the first gate portion, wherein the thickness of the second gate portion is less than the thickness of the first gate portion; and a ferroelectric portion disposed between the side wall of the first gate portion and the side wall of the second gate portion. The second gate layer is located between the gate layer and the substrate, and is electrically insulated from the substrate and the gate layer. The channel structure runs through the gate stack structure and is electrically connected to a doped region in the substrate. The first gate dielectric layer is disposed between the side wall of the channel structure and the other side wall of the first gate portion. The second gate dielectric layer is disposed between the side wall of the channel structure and the side wall of the second gate.

[0007] Based on the above, the flash memory of the embodiment of the present invention can avoid the effect of carrier tunneling injection caused by an excessively large electric field across the gate dielectric layer, and improve the problem of mismatch between the capacitance values ​​of the first capacitor and the second capacitor caused by the large difference between the dielectric constant of the gate dielectric layer and the dielectric constant of the ferroelectric part. Therefore, the embodiment of the present invention can not only improve the efficiency of reading and writing, improve the reliability of the flash memory, but also have a larger storage window.

[0008] In addition, in the flash memory manufacturing method of the embodiment of the present invention, the ratio of the coupling area of ​​the first capacitor to the coupling area of ​​the second capacitor can be easily adjusted by designing the thickness of the gate dielectric layer, the floating gate, the control gate layer and the ferroelectric portion.

[0009] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A FIG. 4 is a schematic top view of a three-dimensional flash memory according to a first embodiment of the present invention.

[0011] Figure 1B FIG. 4 is a schematic top view of a three-dimensional flash memory according to an embodiment of the present invention.

[0012] Figure 1C for Figure 1B A stereoscopic image of several three-dimensional flash memories in area A.

[0013] FIG. 2A to FIG. 2H for Figure 1A A schematic cross-sectional view of the manufacturing process of a three-dimensional flash memory along the cut line II'.

[0014] Figure 3 for Figure 2H Middle area B or Figure 5KAn enlarged schematic diagram of the storage unit in area B' rotated 90 degrees.

[0015] Figures 4A to 4K It is a top view schematic diagram of a manufacturing process of a flash memory having two vertical transistors according to a second embodiment of the present invention.

[0016] FIG. 5A to FIG. 5K for Figures 4A to 4K Schematic diagram of the cross section of the tangent line II-II'.

[0017]

Explanation of symbols

[0018] 10, 50: Stacked memory structure

[0019] 12, 52: Storage unit

[0020] 100: Dielectric substrate

[0021] 102, 202: Laminated structure

[0022] 104, 203, 205, 207: Insulation layer

[0023] 106, 206: Sacrificial layer

[0024] 108, 208: opening

[0025] 109, 126, 204, 209, 226: Gate portion

[0026] 110, 210: gate dielectric layer

[0027] 112: channel layer, channel column or channel column

[0028] 114: Insulation filling layer

[0029] 116: Insulation column

[0030] 118, 120: contact hole

[0031] 122: first conductor column

[0032] 124: Second conductor column

[0033] 125, 225: Ministry of Railways and Electricity

[0034] 127, 227: Barrier layer

[0035] 150, 250: Gate layer

[0036] 200: substrate

[0037] 201: Doping area

[0038] 211, 211A, 211C: oxide layer

[0039] 211B: oxide layer, gate dielectric layer

[0040] 212: Channel layer

[0041] 228: Insulation lining

[0042] A, B, B': Area

[0043] CP: Channel Structure

[0044] CP1: Channel plug

[0045] CP2: Channel Column

[0046] CSL: Shared Source Line

[0047] GF: Filling layer

[0048] II', II-II': tangent

[0049] L1, L2, t0, t1, t2 t , t2 b , t2 s , t3: thickness

[0050] MFM: First Capacitor

[0051] MIS: Second capacitor

[0052] MFMIS: Capacitors in series

[0053] PL: Conductor plug

[0054] R1, R2: Concave

[0055] SK1, SK2: Gate stack structure

[0056] SP: Spacer

[0057] SL: Slit opening

[0058] T1, T2: Horizontal opening

[0059] X, Y, Z: direction DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0061] Figure 1A FIG. 4 is a schematic top view of a three-dimensional flash memory according to a first embodiment of the present invention. Figure 1B FIG. 1 is a schematic top view of a three-dimensional flash memory according to one embodiment of the present invention. Figure 1C for Figure 1B A stereogram of a three-dimensional flash memory in area A. Figure 1A The cross-sectional diagram of the tangent line II' is shown in Figure 2H shown. Figure 3 yes Figure 2H An enlarged schematic diagram of a storage unit in area B rotated 90 degrees.

[0062] Reference Figure 1A , Figure 1B and Figure 1C In this embodiment, the three-dimensional flash memory includes a plurality of stacked memory structures 10. These stacked memory structures 10 can be arranged in an array. Figure 1A or Figure 1B In the embodiment, the three-dimensional flash memory has 10 stacked memory structures 10 arranged in an array. In the array, the stacked memory structures 10 in odd columns are aligned with each other, the stacked memory structures 10 in even columns are aligned with each other, and the stacked memory structures 10 in two adjacent columns are staggered with each other. In addition, the number, position, orientation, spacing, etc. of these stacked memory structures 10 are not limited to Figure 1C shown.

[0063] Reference Figure 1A , Figure 1B , Figure 1C and Figure 2H Each stacked memory structure 10 of this embodiment includes a gate stack structure SK1 disposed on a dielectric substrate 100. The gate stack structure SK1 includes multiple gate layers 150 and multiple insulating layers 104 that are alternately stacked. The upper and lower adjacent gate layers 150 are separated from each other by the insulating layer 104. Figure 1A , Figure 1B and Figure 1C The insulating layer 104 and the dielectric substrate 100 are omitted. In the present embodiment, the gate stack structure SK1 includes three gate layers 150 and four insulating layers 104. However, the present invention is not limited thereto, and the gate stack structure SK1 may include more than three or less than three gate layers 150 and more than four or less than four insulating layers 104.

[0064] Each gate layer 150 includes a first gate portion 109, a second gate portion 126, and a ferroelectric portion 125. The first gate portion 109 can be used as a floating gate layer, and the second gate portion 126 can be used as a control gate layer. The ferroelectric portion 125 is sandwiched between the sidewalls of the first gate portion 109 and the sidewalls of the second gate portion 126, and forms a lateral sandwich structure with the two. Moreover, the ferroelectric portion 125 also extends to cover the top and bottom surfaces of the second gate portion 126, forming a longitudinal sandwich structure. In some embodiments, each gate layer 150 also includes a barrier layer 127, which is disposed between the second gate portion 126 and the ferroelectric portion 125.

[0065] Each stacked memory structure 10 of the three-dimensional flash memory also includes a channel layer 112, a gate dielectric layer 110, and a first conductor column 122 and a second conductor column 124. In some embodiments, the channel layer 112 is an annular channel column, which is disposed on the dielectric substrate 100 and is continuous in its extension direction (e.g., Z direction) and vertically penetrates the gate stack structure SK1. The shape of the annular channel column can be circular, elliptical, rectangular or polygonal, but is not limited thereto. The outer side wall of the channel layer 112 is surrounded by the first gate portion 109 and the insulating layer 104. Figure 2H In the diagram, the X, Y, and Z directions are perpendicular to each other.

[0066] The gate dielectric layer 110 is disposed on the dielectric substrate 100, and is continuous in its extension direction and vertically penetrates the gate stack structure SK1. In addition, the gate dielectric layer 110 surrounds the outer sidewall of the channel layer 112. Moreover, the gate dielectric layer 110 is disposed between the first gate portion 109 and the channel layer 112 and contacts both of them, and is disposed between the insulating layer 104 and the channel layer 112 and contacts both of them.

[0067] The first conductive pillar 122 and the second conductive pillar 124 may also be referred to as a first source / drain (S / D) pillar 122 and a second source / drain pillar 124 . The first conductive pillar 122 and the second conductive pillar 124 are in contact with the channel layer 112 .

[0068] In some embodiments, the first source / drain column 122 and the second source / drain column 124 are disposed on the dielectric substrate 100 and are located within the sidewalls of the channel layer 112, and are continuous in their extension direction and penetrate the gate stack structure SK1. The sidewalls of the first conductor column 122 and the second conductor column 124 are respectively connected to the inner sidewalls of the channel layer 112, and the first conductor column 122 and the second conductor column 124 are separated from each other by the insulating column 116, as shown in FIG. Figure 1A shown.

[0069] In some other embodiments, the first source / drain column 122 and the second source / drain column 124 are disposed on the dielectric substrate 100, and are structured to pass through the channel layer 112 and protrude from the outer sidewall of the channel layer 112, such as Figure 1B and Figure 1C For the sake of clarity of the attached figure Figure 1B The insulating column 116 is omitted. In some embodiments, the first conductive column 122 and the second conductive column 124 respectively include a central portion and a peripheral portion surrounding the central portion, and the doping concentration of the central portion is greater than the doping concentration of the peripheral portion. This concentration difference can be used for junction tuning.

[0070] Each gate layer 150 and the surrounding channel layer 112, gate dielectric layer 110, first conductive pillar 122 and second conductive pillar 124 form a memory cell 12. Figure 2H In the embodiment, each stacked memory structure 10 has three memory cells 12 stacked in the vertical direction. However, the number of memory cells 12 in each stacked memory structure 10 is not limited thereto. Each stacked memory structure 10 may include more or fewer memory cells 12 stacked in the vertical direction.

[0071] Reference Figure 3 In the memory cell 12 of the stacked memory structure 10, the second gate portion 126 as a control gate, the ferroelectric portion 125 and the first gate portion 109 as a floating gate form a first capacitor MFM, and the first gate portion 109 as a floating gate, the gate dielectric layer 110 and the channel layer 112 form a second capacitor MIS. The first capacitor MFM and the second capacitor MIS are connected in series to form a capacitor MFMIS.

[0072] In this embodiment, the coupling area A of the first capacitor MFM is F It refers to the overlapping area of ​​the second gate portion 126, the ferroelectric portion 125 and the first gate portion 109 projected on the YZ plane, and the coupling area A of the second capacitor MIS I It refers to the overlapping area of ​​the first gate portion 109, the gate dielectric layer 110 and the channel layer 112 projected on the YZ plane. The coupling area A of the first capacitor MFM F The thickness L2 of the second gate portion 126 is related to the coupling area A of the second capacitor MIS. I The thickness L2 of the second gate portion 126 is smaller than the thickness L1 of the first gate portion 109. Therefore, the coupling area A of the first capacitor MFM is F Smaller than the coupling area A of the second capacitor MIS I . Coupling area A F and coupling area A I The ratio R A It is related to the dielectric constants of the ferroelectric portion 125 and the gate dielectric layer 110. When the ratio of the dielectric constants of the ferroelectric portion 125 and the gate dielectric layer 110 is D The larger (greater than 1), the coupling area A can be controlled by the process. F and coupling area A I The ratio R A The smaller the adjustment is (less than 1). When the ratio of the dielectric constants of the ferroelectric portion 125 and the gate dielectric layer 110 is D The closer it is to 1, the coupling area A can be reduced by process control. F and coupling area A IThe coupling area ratio R A The closer the adjustment is to 1. In some embodiments, the ratio of dielectric constants R D Greater than or equal to 1, the ratio of the coupling area R A In some embodiments, the ratio of the coupling area R A Between 0.2 and 0.5.

[0073] Compared with the second capacitor MIS, the first capacitor MFM has a smaller coupling area A F Therefore, when performing read and write operations, the first capacitor MFM will have a large voltage drop, so the electric field across the second capacitor MIS can be reduced. Therefore, the tunneling injection effect of the gate dielectric layer 110 caused by an excessively large electric field can be avoided, thereby improving the efficiency of reading and writing, improving the reliability of the device, and increasing the memory window. In some embodiments, the coupling area A F and coupling area A I The ratio R A Less than 0.5, the storage window can be greater than 4 volts.

[0074] In the embodiment of the present invention, by controlling the coupling area A F and coupling area A I The coupling area ratio R A To improve the capacitance mismatch problem between the second capacitor MIS and the first capacitor MFM, and further enhance the reliability of the flash memory.

[0075] The above three-dimensional flash memory can be FIG. 2A to FIG. 2H The method for manufacturing is described in detail below.

[0076] Reference Figure 2A, a stacked structure 102 is formed on a dielectric substrate 100. The stacked structure 102 may also be referred to as an insulating stacked structure 102. The dielectric substrate 100 is, for example, a dielectric layer formed on a silicon substrate, such as a silicon oxide layer. In the present embodiment, the stacked structure 102 is composed of an insulating layer 104 and a sacrificial layer 106 which are sequentially and alternately stacked on the dielectric substrate 100. In other embodiments, the stacked structure 102 may be composed of a sacrificial layer 106 and an insulating layer 104 which are sequentially and alternately stacked on the dielectric substrate 100. In addition, in the present embodiment, the topmost layer of the stacked structure 102 is an insulating layer 104. The insulating layer 104 is, for example, a silicon oxide layer. The sacrificial layer 106 is, for example, a silicon nitride layer. In the present embodiment, the stacked structure 102 has 4 layers of insulating layers 104 and 3 layers of sacrificial layers 106, but the present invention is not limited thereto. In other embodiments, more layers of insulating layers 104 and more layers of sacrificial layers 106 may be formed according to actual needs. The thickness t0 of the sacrificial layer 106 is related to the thickness of the subsequently formed gate dielectric layer 110, the ferroelectric portion 125, and the second gate portion 126. In some embodiments, the thickness t0 of the sacrificial layer 106 may range from 20 nm to 200 nm, such as about 80 nm.

[0077] An opening 108 is formed in the stacked structure 102. In the present embodiment, the bottom surface of the opening 108 exposes the dielectric substrate 100, but the present invention is not limited thereto. In other embodiments, when the bottom layer of the stacked structure 102 is the insulating layer 104, the bottom of the opening 108 may be located in the bottom insulating layer 104, that is, the bottom surface of the opening 108 exposes the bottom insulating layer 104 without exposing the dielectric substrate 100. Alternatively, in other embodiments, the bottom of the opening 108 also extends into the dielectric substrate 100. In the present embodiment, the opening 108 has a circular profile from a top view, but the present invention is not limited thereto. In other embodiments, the opening 108 may have a profile of other shapes, such as a polygon.

[0078] Reference Figure 2B , a pull back process is performed to laterally etch the sacrificial layer 106 to form a plurality of recesses R1 at the end of the sacrificial layer 106. The pull back process may be isotropic etching, anisotropic etching or a combination thereof.

[0079] Reference Figure 2C , forming a first gate portion 109 in the cavity R1. The first gate portion 109 is formed by, for example, forming a conductor layer to cover the top surface of the stacked structure 102 and fill the opening 108 and the cavity R1. The material of the conductor layer is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x). In addition, in other embodiments, before forming the first gate portion 109, a buffer layer and a barrier layer may be sequentially formed in the recess R1. Afterwards, a pull-back process, such as an anisotropic etching process, is performed to remove the conductive layer outside the recess R1, so that the top surface of the stacked structure 102 and the sidewalls of the insulating layer 104 in the opening 108 and the bottom surface of the opening 108 are exposed, and then the first gate portion 109 separated from each other is formed. Since the first gate portion 109 is formed in the recess R1, and the height of the recess R1 is approximately equal to the thickness t0 of the sacrificial layer 106, the thickness L1 of the first gate portion 109 can be adjusted by changing the thickness t0 of the sacrificial layer 106.

[0080] Reference Figure 2C and Figure 3 When the thickness t0 of the sacrificial layer 106 is larger, the thickness L1 of the first gate portion 109 is larger. Therefore, the coupling area A of the formed second capacitor MIS is I The larger the coupling area A of the first capacitor MFM is, F The coupling area A with the second capacitor MIS I The coupling area ratio R A When the thickness t0 of the sacrificial layer 106 is smaller, the thickness L1 of the first gate portion 109 is smaller, and the coupling area A of the formed second capacitor MIS is smaller. I The smaller the coupling area A of the first capacitor MFM is, F The coupling area A with the second capacitor MIS I The ratio R A The bigger.

[0081] Reference Figure 2D , a gate dielectric layer 110 is formed on the inner surface of the opening 108. The gate dielectric layer 110 is formed by, for example, first forming a gate dielectric material layer to cover the top surface of the stacked structure 102, and filling the opening 108 to cover the insulating layer 104 and the first gate portion 109. The material of the gate dielectric material layer is, for example, silicon oxide, silicon oxynitride or a combination thereof. Afterwards, an anisotropic etching process is performed to remove the excess gate dielectric material layer, so that the top surface of the stacked structure 102 and the bottom surface of the opening 108 are exposed. The thickness t1 of the gate dielectric layer 110 is, for example, 2nm to 10nm.

[0082] A channel layer 112 is formed on the sidewall of the gate dielectric layer 110. The channel layer 112 is, for example, an undoped polysilicon layer. The channel layer 112 is formed by, for example, forming a channel material layer on the top surface of the stacked structure 102 and on the inner surface and bottom of the opening 108. Then, an anisotropic etching process is performed to remove the channel material layer on the top surface of the stacked structure 102 and the bottom surface of the opening 108. In the present embodiment, since the channel layer 112 is formed on the inner surface of the opening 108, the channel layer 112 can also be referred to as a channel column 112 or an annular channel layer 112. The channel layer 112 is continuous in its extension direction (between the top and bottom of the opening 108). In the present embodiment, since the opening 108 has a circular profile from a top view angle, the channel column also has a circular profile, but the present invention is not limited thereto. In other embodiments, depending on the shape of the opening 108, the channel column may also have a profile of other shapes (e.g., a polygon) from a top view angle. Furthermore, the gate dielectric layer 110 is located between the channel layer 112 and the inner surface of the opening 108 , and thus covers the outer surface of the channel pillar (channel layer 112 ).

[0083] An insulating filling layer 114 is formed in the opening 108. The insulating filling layer 114 is, for example, a silicon oxide layer. The method for forming the insulating filling layer 114 is, for example, a chemical vapor deposition process to form an insulating material layer covering the top surface of the stacked structure 102, the sidewall of the channel layer 112 and the bottom surface of the opening 108. Then, a back etching process is performed to expose the top surface of the stacked structure 102 and the bottom surface of the opening 108. The insulating filling layer 114 does not fill the opening 108, but retains the central part of the opening 108. Afterwards, an insulating column 116 is formed in the opening 108 to fill the central part of the opening 108. The materials of the insulating column 116 and the insulating filling layer 114 have different etching rates. In some embodiments, the material of the insulating column 116 is different from the material of the insulating filling layer 114, for example, a silicon nitride layer. The method for forming the insulating column 116 is, for example, a chemical vapor deposition process. In other embodiments, the opening 108 may be first filled with the insulating filling layer 114 , and then an opening exposing the dielectric substrate 100 is formed in the insulating filling layer 114 and filled with the insulating pillar 116 .

[0084] Reference Figure 2E, contact holes 118 and contact holes 120 are formed in the insulating filling layer 114. The bottom surfaces of the contact holes 118 and the contact holes 120 expose the dielectric substrate 100. In the present embodiment, from a top view, the contact holes 118 and the contact holes 120 have circular contours, but the present invention is not limited to this. In other embodiments, the contact holes 118 and the contact holes 120 may have contours of other shapes, such as polygons. In the present embodiment, the contact holes 118 and the contact holes 120 are respectively formed on opposite sides of the insulating column 116, and are not in contact with the insulating column 116 and the channel layer 112, but the present invention is not limited to this. In other embodiments, the contact holes 118 and the contact holes 120 may be in contact with the insulating column 116 and / or the channel layer 112. The contact holes 118 and the contact holes 120 are used to define the positions of the source and drain of the three-dimensional flash memory of the present embodiment.

[0085] Reference Figure 2F , a hole expansion process is performed to expand the size of the contact hole 118 and the contact hole 120. In some embodiments, the contact hole 118 and the contact hole 120 respectively expose the insulating column 116 and the channel layer 112. In other embodiments, the contact hole 118 and the contact hole 120 respectively expose the channel layer 112, and the insulating column 116 is exposed. The sidewall of the insulating column 116 is covered by the remaining insulating filling layer 114 (as shown by the dotted line). In this embodiment, the method of expanding the size of the contact hole 118 and the contact hole 120 is, for example, to perform an isotropic etching process on the contact hole 118 and the contact hole 120. Specifically, during the isotropic etching process, the insulating pillar 116 (silicon nitride layer) and the channel layer 112 (polysilicon layer) are used as etching stop layers, and the insulating filling layer 114 (silicon oxide layer) around the contact hole 118 and the contact hole 120 is removed, while the insulating filling layer 114 (silicon oxide layer) outside the contact hole 118 and the contact hole 120 is left (e.g., Figure 1A 1B). In this way, the enlarged contact holes 118 and 120 can contact the insulating pillar 116 and the channel layer 112. Then, a doped polysilicon layer is formed in the enlarged contact holes 118 and 120 to form the first conductor pillar 122 and the second conductor pillar 124 of the three-dimensional flash memory of this embodiment. In this way, the first conductor pillar 122 and the second conductor pillar 124 can be electrically connected to the channel pillar 112. In some embodiments, the first conductor pillar 122 and the second conductor pillar 124 are separated from each other by the insulating pillar 116. In other embodiments, the first conductor pillar 122 and the second conductor pillar 124 are separated from each other by the insulating pillar 116 and the remaining insulating filling layer 114.

[0086] Reference Figure 2G, the sacrificial layer 106 in the stacked structure 102 is removed to form a lateral opening T1 between adjacent insulating layers 104. The lateral opening T1 exposes the first gate portion 109 and the insulating layer 104. The method of removing the sacrificial layer 106 is, for example, to form a slit opening (not shown) in the stacked structure 102, and then perform a selective etching process through the slit opening to remove the sacrificial layer 106 without consuming the insulating layer 104.

[0087] Reference Figure 2H After removing the sacrificial layer 106, a ferroelectric portion 125 and a second gate portion 126 are formed in the formed lateral opening T1. The ferroelectric portion 125 does not fill the lateral opening T1; the second gate portion 126 fills the remaining space of the lateral opening T1. The ferroelectric portion 125 covers the sidewalls, top surface and bottom surface of the lateral opening T1. The dielectric constant of the ferroelectric portion 125 is equal to or greater than the dielectric constant of the gate dielectric layer 110. In some embodiments, the ratio of the dielectric constant of the ferroelectric portion 125 to the dielectric constant of the gate dielectric layer 110 is between 1 and 7. The ferroelectric portion 125 is, for example, hafnium oxide (HfO2) doped with Al, Si, Zr, La, Gd or Y. The second gate portion 126 can also be called a control gate layer. The material of the second gate portion 126 is, for example, polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x ). In addition, in other embodiments, after forming the ferroelectric portion 125 and before forming the second gate portion 126, a barrier layer 127 may be sequentially formed in the lateral opening T1. The material of the barrier layer 127 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

[0088] The method for forming the ferroelectric portion 125, the barrier layer 127 and the second gate portion 126 is as described below. A ferroelectric material layer is formed in the lateral opening T1 and the slit opening. The method for forming the ferroelectric material layer is, for example, CVD. The ferroelectric material layer does not fill the lateral opening T1. After the ferroelectric material layer is formed, a barrier layer and a gate material layer are formed on the ferroelectric material layer and in the remaining space of the lateral opening T1. Thereafter, a back etching process is performed to remove the ferroelectric material layer, the barrier layer and the gate material layer outside the lateral opening T1 to form the ferroelectric portion 125, the barrier layer 127 and the second gate portion 126.

[0089] Please refer to Figure 3 In some embodiments, the ferroelectric portion 125 covering the top surface of the second gate portion 126 has a thickness t2 t The ferroelectric portion 125 covering the bottom surface of the second gate portion 126 has a thickness t2 b The ferroelectric portion 125 covering the sidewall of the second gate portion 126 has a thickness t2s Thickness t2 t , thickness t2 b and thickness t2 s The average thickness is t2 。 In some embodiments, the ferroelectric portion 125 is a conformal layer that uniformly and conformally covers the sidewalls, top surface, and bottom surface of the lateral opening T1. t , thickness t2 b and thickness t2 s When the thickness t2 of the ferroelectric portion 125 is larger, the thickness L2 of the second gate portion 126 is smaller, and the coupling area A of the first capacitor MFM formed is F The smaller the coupling area A of the first capacitor MFM is, F The coupling area A with the second capacitor MIS I The ratio R A When the thickness t2 of the ferroelectric portion 125 is smaller, the thickness L2 of the second gate portion 126 is larger, and the coupling area A of the first capacitor MFM formed is F The larger the coupling area A of the first capacitor MFM is, F The coupling area A with the second capacitor MIS I The ratio R A The bigger.

[0090] The thickness L2 of the second gate portion 126 can be determined by adjusting the thickness t2 of the ferroelectric portion 125 and the thickness t0 of the sacrificial layer 106. In some embodiments, the dielectric constant of the ferroelectric portion 125 ranges from 15 to 30, and the dielectric constant of the gate dielectric layer 110 ranges from 3.9 to 9. The thickness t0 of the sacrificial layer 106 and the thickness L1 of the first gate portion 109 range from 20nm to 200nm, and the thickness t1 of the gate dielectric layer 110 ranges from 3nm to 30nm, for example, 5nm. The thickness t2 of the ferroelectric portion 125 ranges from 10nm to 50nm, for example, 20nm. The thickness L2 of the second gate portion 126 ranges from 20nm to 150nm, for example, 40nm.

[0091] Afterwards, a metallization process and other subsequent processes may be performed. For example, when the first conductive pillar 122 is used as a source and the second conductive pillar 124 is used as a drain, the subsequent metallization process may form a source line connected to the first conductive pillar 122 and a bit line connected to the second conductive pillar 124 .

[0092] It is particularly noted that the three-dimensional flash memory of the present invention is not limited to the structure of the stacked memory structure 10, and other various structures will be described below. In the following embodiments, the same elements as those in the first embodiment will be represented by the same element symbols and will not be described again.

[0093] On the other hand, when a more-layered memory cell stack structure is required for high integration and high area utilization, a plurality of three-dimensional flash memory stacks of the present invention may be formed on a substrate. Figure 2H After the stacked memory structure 10 shown, the manufacturing steps of the stacked memory structure 10 can be repeated once or multiple times to stack another or more stacked memory structures 10 on the stacked memory structure 10. In this way, the process complexity of the multi-layer three-dimensional flash memory can be effectively reduced. In this case, the connection between the upper stacked memory structure and the lower stacked memory structure can be achieved by contacting the conductor pillars of the upper stacked memory structure with the conductor pillars of the lower stacked memory structure. Since the conductor pillars in the stacked memory structure of the present invention have a larger size than other components, the upper stacked memory structure and the lower stacked memory structure can be easily aligned without the problem of misalignment, and the channel pillars of the upper stacked memory structure and the channel pillars of the lower stacked memory structure do not need to be completely aligned.

[0094] Figure 4K FIG. 4 is a top view of a NOR flash memory according to a second embodiment of the present invention. Figure 5K yes Figure 4K Schematic diagram of the cross section of the tangent line II-II'. Figure 3 yes Figure 5K An enlarged schematic diagram of a storage unit in area B' rotated 90 degrees.

[0095] Reference Figure 4K In this embodiment, the flash memory having two vertical transistors includes a plurality of stacked memory structures 50. These stacked memory structures 50 may be arranged in an array. Figure 4K In the embodiment, the NOR flash memory has five stacked memory structures 50 arranged in an array. In the array, the stacked memory structures 50 in odd columns are aligned with each other, the stacked memory structures 50 in even columns are aligned with each other, and the stacked memory structures 50 in two adjacent columns are staggered with each other. In addition, the number, position, orientation, spacing, etc. of these stacked memory structures 50 are not limited to Figure 4K shown.

[0096] Reference Figure 4K and 5K Each stacked memory structure 50 includes a gate stack structure SK2 disposed on a substrate 200. The gate stack structure SK2 includes a gate layer 204 and a gate layer 250 that are insulated from each other. The gate layer 204 can be used as a select gate, which is located between the substrate 200 and the gate layer 250, and is electrically insulated from the substrate 200 by an insulating layer 203, and is electrically insulated from the gate layer 250 by an insulating layer 205.

[0097] Reference Figure 3 and Figure 5K The gate layer 250 is located between the insulating layers 205 and 207, and includes a first gate portion 209, a ferroelectric portion 225, and a second gate portion 226. The first gate portion 209 can be used as a floating gate, and the second gate portion 226 can be used as a control gate. The ferroelectric portion 225 is sandwiched between the sidewalls of the first gate portion 209 and the sidewalls of the second gate portion 226, and forms a lateral sandwich structure with the two. The ferroelectric portion 225 also extends to cover and contact the top and bottom surfaces of the second gate portion 226, forming a longitudinal sandwich structure.

[0098] Reference Figure 5K , the stacked memory structure 50 also includes a channel structure CP. The channel structure CP runs through the gate stack structure SK2 and is electrically connected to the doped region 201 in the substrate 200. The channel structure CP includes a channel plug CP1 and a channel column CP2. The channel plug CP1 is disposed below the channel column CP2 and runs through part of the insulating layer 205, the gate layer 204, and the insulating layer 203. The top surface of the channel plug CP1 is electrically connected to the bottom surface of the channel column CP2, and the bottom surface of the channel plug CP1 is electrically connected to the doped region 201 formed in the substrate 200. The channel column CP2 is located above the channel plug CP1 and is continuous in its extension direction. The channel column CP2 also runs through the insulating layer 207, the gate layer 250, and another part of the insulating layer 205. In some embodiments, the channel column CP2 includes a channel column 212, a filling layer GF, and a conductor plug PL. The sidewall of the channel column 212 is continuous in its extension direction and penetrates the insulating layer 207, the gate layer 250 and another part of the insulating layer 205. The bottom surface of the channel column 212 is electrically connected to the top surface of the channel plug CP1. The filling layer GF is located in the channel column 212. The conductor plug PL is located above the filling layer GF, and the sidewall of the conductor plug PL is electrically connected to the sidewall of the channel column 212. In addition, the top surface of the conductor plug PL can be coplanar with the top surfaces of the channel column 212, the gate dielectric layer 210 and the insulating layer 207, but is not limited thereto.

[0099] The stacked memory structure 50 further includes a gate dielectric layer 211B and a gate dielectric layer 210. The gate dielectric layer 211B is disposed on the dielectric substrate 100, surrounds the outer sidewall of the channel plug CP1, and is between the channel plug CP1 and the gate layer 204. The gate dielectric layer 210 is disposed above the channel plug CP1, surrounds the outer sidewall of the channel pillar CP2. The gate dielectric layer 210 is continuous in its extension direction, and vertically penetrates the insulating layer 207, the gate layer 250, and another portion of the insulating layer 205. Moreover, the gate dielectric layer 210 is disposed between the first gate portion 209 and the channel pillar 212 and contacts both of them, and is disposed between the insulating layer 207 and the channel pillar 212 and contacts both of them.

[0100] Reference Figure 4Kand 5K The stacked memory structure 50 further includes a shared source line CSL that penetrates the gate stack structure SK2 and is electrically connected to the doped region 201 in the substrate 200. The shared source line CSL is electrically insulated from the gate stack structure SK2 by the insulating liner 228.

[0101] Reference Figure 3 and Figure 5K According to the second embodiment of the present invention, in the memory cell 52 of the stacked memory structure 50, the second gate portion 226 as the control gate, the ferroelectric portion 225 and the first gate portion 209 as the floating gate form a first capacitor MFM, and the first gate portion 209 as the floating gate, the gate dielectric layer 210 and the channel pillar 212 form a second capacitor MIS. The first capacitor MFM and the second capacitor MIS are connected in series to form a capacitor MFMIS. The contents of the first capacitor MFM and the second capacitor MIS can refer to the above description.

[0102] The flash memory with two vertical transistors can be referred to as Figures 4A to 4K as well as FIG. 5A to FIG. 5K The method shown is fabricated as detailed below.

[0103] Reference Figure 4A and Figure 5A , a stacked structure 202 is formed on a substrate 200. The substrate 200 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, a doped region (e.g., an N+ doped region or an N-type well region) 201 may be formed in the substrate 200 according to design requirements. The stacked structure 202 includes an insulating layer 203, a gate layer 204, an insulating layer 205, a sacrificial layer 206, and an insulating layer 207 sequentially stacked on the substrate 200. The insulating layers 203, 205, and 207 include silicon oxide. The gate layer 204 is, for example, a doped polysilicon layer. The sacrificial layer 206 is, for example, a silicon nitride layer. In some embodiments, the thickness t0 of the sacrificial layer 206 may range from 20 nm to 200 nm, for example, about 800 nm.

[0104] Next, an opening 208 is formed in the stacked structure 202. In the present embodiment, the opening 208 extends along the Z direction, and its bottom exposes the surface of the doped region 201 in the dielectric substrate 100, but the present invention is not limited thereto. Alternatively, in other embodiments, the bottom of the opening 208 also extends into the doped region 201 of the dielectric substrate 100. In the present embodiment, the opening 208 has a circular profile from a top view, but the present invention is not limited thereto. In other embodiments, the opening 208 may have a profile of other shapes, such as a polygon.

[0105] Then, refer to Figure 4C and Figure 5C, a gate dielectric layer 211B is formed on the sidewall of the gate layer 204. The gate dielectric layer 211B can be silicon oxide or a dielectric material with a high dielectric constant. A dielectric material with a high dielectric constant refers to a material with a dielectric constant greater than or equal to 4, such as silicon oxynitride or aluminum oxide. The gate dielectric layer 211B can be formed by the following method.

[0106] First, refer to Figure 4B and Figure 5B , a thermal oxidation process is performed to oxidize the surface of the sidewall of the substrate 200 and the gate layer 204 exposed by the opening 208 to form an oxide layer 211. The oxide layer 211 includes oxide layers 211A and 211B. The oxide layer 211A is formed on the surface of the doped region 201 in the substrate 200. The oxide layer 211B is formed on the sidewall of the gate layer 204, and the sidewall of the oxide layer 211B can be flush with the sidewall of the insulating layer 203, 205, or protrude from the sidewall of the insulating layer 203, 205. In some embodiments, an oxide layer 211C is also formed on the sidewall of the sacrificial layer 206, so the oxide layer 211 also includes the oxide layer 211C. Compared with the gate layer 204 and the substrate 200 , the oxidation rate of the sacrificial layer 206 is slower, so the thickness of the oxide layer 211C generated from the sacrificial layer 206 is thinner than the thickness of the oxide layer 211A or 211B generated from the gate layer 204 and the substrate 200 .

[0107] Afterwards, a spacer SP is formed on the sidewall of the opening 208. The material of the spacer SP is different from the material of the oxide layer 211C, and has a different etching rate in the subsequent etching process. The material of the spacer SP can be a nitride, for example, a nitride. The method for forming the spacer SP is, for example, to form a spacer material layer on the top surface of the insulating layer 207 and the sidewall and bottom of the opening 208. Then, an anisotropic etching process is performed on the spacer material layer to remove the spacer material layer on the top surface of the insulating layer 207 and the bottom of the opening 208.

[0108] Then, refer to Figure 4B , Figure 4C , Figure 5B and Figure 5C , using the spacer SP as a mask, the oxide layer 211A on the surface of the substrate 200 is removed. Next, the spacer SP is removed, and then the oxide layer 211C is removed to expose the sidewalls of the sacrificial layer 206. The oxide layer 211B remaining on the sidewalls of the gate layer 204 is used as a gate dielectric layer 211B. The thickness t3 of the gate dielectric layer 211B is, for example, 5 nm to 30 nm.

[0109] Then, refer to Figure 4D and Figure 5D, a channel plug CP1 is formed in the opening 208. The channel plug CP1 is, for example, doped epitaxial silicon formed by a selective epitaxial growth process. The channel plug CP1 is electrically connected to the doped region 201 in the substrate 200. The height of the top surface of the channel plug CP1 is, for example, between the top surface and the bottom surface of the insulating layer 205. Next, a pull-back process is performed to laterally etch the sacrificial layer 206 to form a recess R2 at the end of the sacrificial layer 206. The pull-back process can be isotropic etching, anisotropic etching, or a combination thereof.

[0110] Reference Figure 4E and Figure 5E , forming a first gate portion 209 in the cavity R2. The first gate portion 209 may also be referred to as a floating gate layer. The first gate portion 209 may be formed by, for example, forming a conductor layer to cover the top surface of the stacked structure 202 and fill the opening 208 and the cavity R2. The conductor layer may be made of, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x ). In addition, in other embodiments, before forming the first gate portion 209, a barrier layer (not shown) may be formed in the recess R2. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. Afterwards, a pull-back process, such as an anisotropic etching process, is performed to remove the barrier layer and the conductor layer outside the recess R2, so that the top surface of the stacked structure 202 and the side walls of the insulating layers 205 and 207 in the opening 208 and the top surface of the channel plug CP1 are exposed. Since the first gate portion 209 is formed in the recess R2, and the height of the recess R2 is approximately equal to the thickness t0 of the sacrificial layer 206, the thickness L1 of the first gate portion 209 can be adjusted by changing the thickness t0 of the sacrificial layer 206.

[0111] Reference Figure 4F and Fig. 5F , a gate dielectric layer 210 is formed on the inner surface of the opening 208. The gate dielectric layer 210 is formed by, for example, first forming a gate dielectric material layer to cover the top surface of the stacked structure 202 and filling the opening 208 to cover the insulating layer 207, the first gate portion 209 and the insulating layer 205. The material of the gate dielectric material layer is, for example, silicon oxide or a dielectric material with a high dielectric constant, such as silicon oxynitride, aluminum oxide or a combination thereof. Afterwards, an anisotropic etching process is performed to remove the excess gate dielectric material layer, so that the top surface of the stacked structure 202 and the top surface of the channel plug CP1 are exposed.

[0112] Reference Figure 4G and Figure 5G, a channel column CP2 is formed in the opening 208. The channel column CP2 includes a channel column 212, a filling layer GF and a conductor plug PL. The channel column 212 is, for example, an undoped polysilicon layer. The filling layer GF includes an insulating material, such as silicon oxide. The channel plug PL is, for example, doped polysilicon. The method for forming the channel column 212, the filling layer GF and the conductor plug PL is, for example, to form a channel material layer and a filling material layer in sequence on the top surface of the insulating layer 207 and the inner surface of the opening 208 and the top surface of the conductor plug PL, and then perform a chemical mechanical polishing process to remove the filling material layer and the channel material layer on the top surface of the insulating layer 207. Thereafter, an anisotropic etching process is performed on the filling material layer so that the top surface of the remaining filling layer GF is lower than the top surface of the channel column 212, and a groove (not shown) is formed above the filling layer GF. Thereafter, a conductor material layer is deposited to cover the top surface of the insulating layer 207 and fill the groove on the filling layer GF. Next, a chemical mechanical polishing process is performed to remove the conductive material layer on the top surface of the insulating layer 207 to form a conductive plug PL.

[0113] Reference Figure 4H and Figure 5H , photolithography and etching processes are performed to form a slit opening SL in the stacked structure 202. The slit opening SL is in the shape of a long strip, which extends continuously along the Y direction. The sidewall of the slit opening SL exposes the insulating layer 207, the sacrificial layer 206, the insulating layer 205, the gate layer 204, and the insulating layer 203, while the bottom surface of the slit opening SL exposes the doped region 201 in the substrate 200.

[0114] Reference Fig.5I , an isotropic etching process is performed to remove the sacrificial layer 206 in the stacked structure 202 by an etchant passing through the slit opening SL to form a lateral opening T2 exposing the insulating layers 205, 207 and the first gate portion 209. The method of removing the sacrificial layer 206 includes a selective etching process.

[0115] Reference Figure 4J and Figure 5J After removing the sacrificial layer 206, a ferroelectric portion 225 and a second gate portion 226 are formed in the lateral opening T2. The second gate portion 226 can also be called a control gate layer. The dielectric constant of the ferroelectric portion 225 is equal to or greater than the dielectric constant of the gate dielectric layer 210. In some embodiments, the ratio of the dielectric constant of the ferroelectric portion 225 to the dielectric constant of the gate dielectric layer 210 is between 1 and 7. The material of the ferroelectric portion 225 is, for example, hafnium oxide (HfO2) doped with Al, Si, Zr, La, Gd or Y. The material of the second gate portion 226 is, for example, polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi xIn some embodiments, a barrier layer 227 is further included between the ferroelectric portion 225 and the second gate portion 226. The material of the barrier layer 227 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof.

[0116] The method for forming the ferroelectric portion 225, the barrier layer 227 and the second gate portion 226 is as described below. A ferroelectric material layer is formed in the lateral opening T2 and the slit opening SL. The method for forming the ferroelectric material layer is, for example, chemical vapor deposition. The ferroelectric material layer does not fill the lateral opening T2. After the ferroelectric material layer is formed, a barrier layer and a gate material layer are formed on the ferroelectric material layer and in the remaining space of the lateral opening T2. Thereafter, a back etching process is performed to remove the ferroelectric material layer, the barrier layer and the gate material layer outside the lateral opening T2 to form the ferroelectric portion 225, the barrier layer 227 and the second gate portion 226.

[0117] Reference Figure 4K and Figure 5K , forming an insulating liner 228 and a shared source line CSL in the slit opening SL. The insulating liner 228 is formed by, for example, forming an insulating material layer on the top surface of the insulating layer 207 and in the slit opening SL, and then performing an anisotropic etching process to remove the insulating material layer on the top surface of the insulating layer 207 and the bottom surface of the slit opening SL to form an insulating liner 228 that exposes the bottom surface of the slit opening SL. The shared source line CSL is formed by, for example, forming a conductive material layer on the top surface of the insulating layer 207 and the remaining space of the slit opening SL, and then performing an anisotropic etching process to remove the conductive material layer on the top surface of the insulating layer 207 to form a shared source line CSL.

[0118] Afterwards, a metallization process and other subsequent processes may be performed. For example, the subsequent metallization process may form a bit line and a dielectric layer electrically connected to the conductor plug PL to complete the three-dimensional flash memory.

[0119] The flash memory of the embodiment of the present invention designs the coupling area of ​​the first capacitor formed by the control gate layer, the ferroelectric part and the floating gate layer to be smaller than the coupling area of ​​the second capacitor formed by the floating gate layer, the gate dielectric layer and the channel layer, so that the first capacitor has a larger voltage drop to reduce the electric field across the second capacitor. In this way, the effect of carrier tunneling injection caused by an excessively large electric field across the gate dielectric layer can be avoided, and the problem of mismatching the capacitance values ​​of the first capacitor and the second capacitor caused by the large difference in the dielectric constant of the gate dielectric layer and the dielectric constant of the ferroelectric part can be improved. Therefore, the embodiment of the present invention can not only improve the efficiency of reading and writing, improve the reliability of the flash memory, but also have a larger storage window.

[0120] In addition, in the flash memory manufacturing method of the embodiment of the present invention, the ratio of the coupling area of ​​the first capacitor to the coupling area of ​​the second capacitor can be easily adjusted by designing the thickness of the gate dielectric layer, the floating gate, the control gate layer and the ferroelectric portion.

[0121] In addition, the three-dimensional flash memory of the present invention has high integration and high area utilization, and meets the requirement of high operating speed.

[0122] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A flash memory, wherein: include: The gate stack structure is disposed on a dielectric substrate and includes multiple gate layers electrically insulated from each other, each gate layer including: a first gate portion; a second gate portion, disposed adjacent to a side wall of the first gate portion, wherein a thickness of the second gate portion is less than a thickness of the first gate portion; a ferroelectric portion disposed between the side wall of the first gate portion and the side wall of the second gate portion; and A channel column, disposed on the dielectric substrate and penetrating the gate stack structure; A first conductor column and a second conductor column are disposed in the channel column and penetrate the gate stack structure, wherein the first conductor column and the second conductor column are separated from each other and are respectively connected to the channel column; and The gate dielectric layer is disposed between the other sidewall of the first gate portion and the sidewall of the channel column.

2. The flash memory according to claim 1, wherein: The first overlapping area of ​​the second gate portion, the ferroelectric portion and the first gate portion projected on the YZ plane is smaller than the second overlapping area of ​​the first gate portion, the side wall of the gate dielectric layer and the channel column projected on the YZ plane; wherein the second gate portion is arranged adjacent to the side wall of the first gate portion along the X direction, the Z direction is the extension direction of the channel column on the dielectric substrate, and the X, Y and Z directions are perpendicular to each other.

3. The flash memory according to claim 2, wherein: The ratio of the first overlapping area to the second overlapping area is between 0.2 and 0.

5.

4. The flash memory according to claim 1, wherein: A barrier layer is also included, located between the ferroelectric portion and the gate layer.

5. A flash memory, wherein: include: The gate stack structure is arranged on the substrate and includes: The first gate layer comprises: a first gate portion; a second gate portion adjacent to a sidewall of the first gate portion; and a ferroelectric portion disposed between a side wall of the first gate portion and a side wall of the second gate portion, wherein a thickness of the second gate portion is smaller than a thickness of the first gate portion; and a second gate layer, located between the first gate layer and the substrate, and electrically insulated from the substrate and the first gate layer; A channel structure, penetrating the gate stack structure and electrically connected to the substrate; a first gate dielectric layer disposed between a sidewall of the channel structure and another sidewall of the first gate portion; and a second gate dielectric layer disposed between the sidewall of the channel structure and the sidewall of the second gate layer; wherein a first overlapping area projected on the YZ plane between the second gate portion, the ferroelectric portion and the first gate portion is smaller than a second overlapping area projected on the YZ plane between the first gate portion, the first gate dielectric layer and the channel structure; a ratio of the first overlapping area to the second overlapping area is between 0.2 and 0.5; wherein the second gate portion is arranged adjacent to a side wall of the first gate portion along the X direction, the Z direction is an extension direction of the channel structure on the substrate, and the X, Y and Z directions are perpendicular to each other.

6. The flash memory according to claim 5, wherein: Also includes: A shared source line, which passes through the gate stack structure and is electrically connected to the substrate; as well as An insulating liner is located between the gate stack structure and the shared source line.

7. The flash memory according to claim 5, wherein: The channel structure comprises: a channel column penetrating the first gate layer, wherein an outer sidewall of the channel column is surrounded by the first gate dielectric layer; and A channel plug is arranged below the channel column and penetrates the second gate layer, wherein the sidewalls of the channel plug are surrounded by the second gate dielectric layer, the top surface of the channel plug is electrically connected to the bottom surface of the channel column, and the bottom surface of the channel plug is electrically connected to the doped region in the substrate. 8 . The flash memory according to claim 5 , further comprising a barrier layer located between the ferroelectric portion and the second gate layer.

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