Three-dimensional semiconductor device with support pattern in contact with plug side surface

Abstract

A three-dimensional semiconductor device having a support pattern in contact with a side surface of a contact plug is provided. A semiconductor device includes a substrate having a cell region and a via region; a transistor and a logic interconnect disposed on the substrate; a lower insulating layer covering the transistor and the logic interconnect; a lower conductive layer on the lower insulating layer in the cell region; a support pattern disposed on the lower insulating layer in the via region; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnect; a word line stack disposed on the lower conductive layer in the cell region; a dielectric layer stack disposed on the support pattern in the via region; a vertical channel pillar penetrating the word line stack to connect to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more specifically, to a three-dimensional (3D) semiconductor device having a support pattern in contact with the side surface of a contact plug. Background Technology

[0002] As the integration density of semiconductor devices increases, the pitch and spacing between interconnects and contact plugs are greatly reduced. In particular, technical challenges arise in the vertical alignment of fine contact plugs with large aspect ratios. Furthermore, due to the multiple CMP (chemical mechanical polishing) processes performed, flatness issues such as the formation of dishing surfaces can affect the alignment between contact plugs. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device including a support pattern that mitigates concave appearance and improves alignment margin between contact plugs.

[0004] Embodiments of this disclosure provide various systems for semiconductor devices including support patterns that mitigate concave phenomena and improve alignment margins between contact plugs.

[0005] Embodiments of this disclosure provide a method for manufacturing a semiconductor device including a support pattern that mitigates concave appearance and improves alignment margin between contact plugs.

[0006] A semiconductor device according to embodiments of the present disclosure may include: a substrate having cell regions and via regions; transistors and logic interconnects disposed on the substrate; a lower insulating layer covering the transistors and logic interconnects; a lower conductive layer located on the lower insulating layer in the cell regions; a support pattern disposed on the lower insulating layer in the via regions; a lower via plug having a side surface in the via regions that contacts the support pattern and a bottom surface that contacts the logic interconnects; a word line stack disposed on the lower conductive layer in the cell regions; a dielectric layer stack disposed on the support pattern and the lower insulating layer in the via regions; a vertical channel post penetrating the word line stack in the cell regions to connect to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack in the via regions to be aligned vertically with the lower via plug.

[0007] A semiconductor device according to an embodiment of the present disclosure can include a logic device layer and a memory device layer stacked on the logic device layer. The logic device layer can include a substrate having a cell region and a via region, a logic interconnect disposed on the substrate, a lower conductive layer disposed over the logic interconnect in the cell region, a lower via plug in contact with the logic interconnect in the via region, and a support pattern in contact with a side surface of the lower via plug in the via region. The memory device layer can include a word line stack disposed on the lower conductive layer in the cell region, the word line stack including alternately stacked first insulating layers and word lines, a vertical channel pillar penetrating the word line stack in the cell region to connect to the lower conductive layer in a vertical direction, a dielectric layer stack in the via region, an upper peripheral contact plug penetrating the dielectric layer stack in the via region to be vertically aligned with the lower via plug in the vertical direction. A top surface of the support pattern and a top surface of the lower via plug can be coplanar. A height of the lower via plug in the vertical direction can be greater than a height of the support pattern in the vertical direction.

[0008] A semiconductor device according to an embodiment of the present disclosure can include a substrate having a cell region, an extension region, and a via region, a transistor and a logic interconnect disposed on the substrate, a lower conductive layer disposed over the logic interconnect and the transistor in the cell region and the extension region, a support pattern and a lower via plug disposed on a lower insulating layer in the via region, a word line stack disposed on the lower conductive layer in the cell region and the extension region, a vertical channel pillar penetrating the word line stack in the cell region to connect to the lower conductive layer in a vertical direction, a word line contact plug electrically connected to word lines of the word line stack, respectively, in the extension region, a dielectric layer stack disposed on the support pattern, the lower via plug, and the lower insulating layer in the via region, and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug in the vertical direction. A side surface of the support pattern and a side surface of the lower via plug can be in contact with each other. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1A is a schematic longitudinal cross-sectional view illustrating a three-dimensional (3D) semiconductor device according to an embodiment of the present disclosure.

[0010] FIG. 1B is a schematic longitudinal cross-sectional view illustrating a 3D semiconductor device according to an embodiment of the present disclosure. FIG. 1A is a layout illustrating alignment of a lower via plug, an upper via plug, and a support pattern of the 3D semiconductor device illustrated in FIG. 1.

[0011] FIG. 1Cis a layout showing an arrangement of support patterns of a 3D semiconductor device according to an embodiment of the present disclosure.

[0012] FIG. 1D is a longitudinal sectional view showing misalignment of a lower via plug and an upper via plug.

[0013] FIG. 2A is a schematic longitudinal sectional view showing a 3D semiconductor device according to an embodiment of the present disclosure.

[0014] FIG. 2B is a layout showing alignment of a lower via plug, an upper via plug, and a support pattern, and FIG. 2C and FIG. 2D is a layout showing an arrangement of support patterns of a 3D semiconductor device according to an embodiment of the present disclosure.

[0015] FIG. 2E is a layout showing alignment of a lower via plug, an upper via plug, and a support pattern according to an embodiment of the present disclosure.

[0016] FIG. 3A to FIG. 3C is a schematic longitudinal sectional view showing a 3D semiconductor device according to each embodiment of the present disclosure.

[0017] FIG. 4A to FIG. 9C is a diagram showing each method of manufacturing a 3D semiconductor device according to an embodiment of the present disclosure.

[0018] FIG. 10 and FIG. 11 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0019] FIG. 12 and FIG. 13 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Various examples and implementations of the disclosed technology are described in detail below with reference to the accompanying drawings. The drawings can not be drawn to scale and, in some instances, the proportions of at least some of the structures in the drawings can be exaggerated for clarity of presentation and to illustrate certain features of the examples or implementations being described. Where a particular example is presented in a multi-layered structure in the drawings or description, the relative positional relationship of the layers as shown in the figure or the order in which the layers are arranged reflects a particular implementation for the example being described or illustrated, and different relative positional relationships or orders in which the layers are arranged are possible. In addition, the example of the multi-layered structure being described or illustrated can not reflect all of the layers present in that particular multi-layered structure (e.g., one or more additional layers can be present between two of the layers shown). As a particular example, when a first layer in a multi-layered structure being described or illustrated is referred to as being "on" or "over" a second layer or a substrate, the first layer can be formed directly on the second layer or substrate, however, in other implementations or examples, a multi-layered structure in which one or more other intervening layers are present between the first and second layers or substrate can also be included.

[0021] FIG. 1A is a schematic longitudinal sectional view illustrating a 3D semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 1A The 3D semiconductor device 100A according to the embodiment of the present disclosure can include a logic device layer LD and a memory device layer MD stacked on the logic device layer LD. The logic device layer LD, the memory device layer MD, and the substrate 10 of the 3D semiconductor device 100A can be organized into a cell area CA, an extension area EA, and a via area VA.

[0022] The logic device layer LD can include logic circuit components 11 to 13, a lower insulating layer 14, a lower conductive layer 15, a support pattern 16, and a lower via plug 21 disposed on the substrate 10. The logic circuit components 11 to 13 can include MOS transistors 11, logic interconnects 12, and logic via plugs 13. The logic interconnects 12 can include a conductor and can transmit an electrical signal in a horizontal direction. The logic interconnects 12 can be formed and disposed in a plurality of conductive layers. The logic via plugs 13 can include a conductor and can transmit an electrical signal in a vertical direction. The lower insulating layer 14 can cover and surround the MOS transistors 11, the logic interconnects 12, and the logic via plugs 13. The lower insulating layer 14 can include an insulating material such as silicon oxide.

[0023] The lower conductive layer 15 can be disposed at an upper portion of the cell region CA of the logic device layer LD. For example, the lower conductive layer 15 can be buried in the lower insulating layer 14. In a top view, the lower conductive layer 15 can have a plate shape that occupies a majority of the cell region CA. The lower conductive layer 15 can also be disposed on the extension region EA of the logic device layer LD. The lower conductive layer 15 can be a common source region. For example, the lower conductive layer 15 can include polysilicon doped with N-type ions. In one embodiment, the lower conductive layer 15 can include at least one of a metal such as tungsten (W), a metal silicide such as titanium silicide (TiSi), or a metal compound such as titanium nitride (TiN).

[0024] The support pattern 16 can have the same material and the same vertical thickness as the lower conductive layer 15. The lower via plug 21 can include at least one of a metal such as tungsten (W), a metal compound such as titanium nitride, and a conductor such as polysilicon doped with N-type ions.

[0025] A side surface of the lower via plug 21 can be in contact with the support pattern 16. Accordingly, the lower via plug 21 in contact with the support pattern 16 can be electrically connected to the support pattern 16. A bottom surface of the lower via plug 21 can be in contact with some of the logic interconnects 12 disposed in the top layer or the uppermost layer. Accordingly, the lower via plug 21 can be directly electrically connected to some of the logic interconnects 12. A top surface of the support pattern 16 and a top surface of the lower via plug 21 can be coplanar. The lower via plug 21 can have a greater vertical thickness or vertical height than the support pattern 16. The bottom surface of the lower via plug 21 can be located at a lower level than a level of the bottom surface of the support pattern 16.

[0026] The memory device layer MD can include a word line stack WS, a dielectric layer stack DS, vertical channel pillars 30, vertical channel studs 40, word line contact plugs 35, word line contact studs 45, through via plugs 36, through via studs 46, upper via plugs 31, and via studs 41.

[0027] The word line stack WS can include first insulating layers 25, 25B, and 25T and word lines 33. The first insulating layers 25, 25B, and 25T can be alternately stacked with the word lines 33. The word line stack WS can extend from the cell region CA to the extension region EA.

[0028] The dielectric layer stack DS can include first insulating layers 25 and second insulating layers 26 alternately stacked. The dielectric layer stack DS can be disposed only in the via region VA.

[0029] The first insulating layers 25 can include silicon oxide. The lowermost first insulating layer 25B can insulate the word lines 33 and the lower conductive layers 15. The intermediate first insulating layers 25 can insulate the respective word lines 33. The uppermost first insulating layer 25T can insulate the word lines 33 and the vertical channel pillar heads 40.

[0030] The second insulating layers 26 can include silicon nitride. The second insulating layers 26 can be disposed at the same level as the respective word lines 33 in the vertical direction.

[0031] In the extension region EA, the word lines 33 can form a staircase. The intermediate insulating layers 28 can cover the staircase word lines 33. The intermediate insulating layers 28 can include the same material as the first insulating layers 25.

[0032] The vertical channel pillars 30 can vertically penetrate the word line stack WS to electrically connect the lower conductive layers 15 to the vertical channel pillar heads 40. Lower ends of the vertical channel pillars 30 can protrude into the lower conductive layers 15. The vertical channel pillars 30 can include a core insulating layer at the center, a channel layer surrounding a side surface of the core insulating layer, and a memory layer surrounding the channel layer. The memory layer can include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. The core insulating layer and the tunnel insulating layer can include silicon oxide, the charge storage layer can include silicon nitride or a high-k dielectric material, and the blocking insulating layer can include a metal oxide. In one embodiment, the memory layer can further include a barrier metal layer such as titanium nitride (TiN) between the vertical channel pillar 30 and the word line 33.

[0033] The word line contact plugs 35 vertically penetrate the intermediate insulating layers 28 in the extension region EA to individually contact end portions of the respective staircase word lines 33. The via plugs 36 can vertically penetrate the intermediate insulating layers 28 in the extension region EA to connect to the lower conductive layers 15. The via plugs 36 can be electrically insulated from, without contacting, the word line contact plugs 35. The via plugs 36 can not be electrically connected to, and can be electrically insulated from, the word lines 33. For example, the via plugs 36 can not vertically penetrate the word lines 33. That is, the via plugs 36 can be horizontally spaced apart from the word lines 33.

[0034] The upper via plugs 31 can vertically penetrate the dielectric stack DS to respectively connect to the respective lower via plugs 21 in the via region VA. That is, the respective upper via plugs 31 can be vertically aligned with the respective lower via plugs 21, respectively.

[0035] The word line contact plugs 35, the via plugs 36, and the upper via plugs 31 can include a conductor such as polysilicon doped with N-type ions, a metal, a metal silicide, or a metal compound.

[0036] The vertical channel stems 40 can electrically connect the respective vertical channel pillars 30 to respective upper interconnects (not shown), respectively. The word line contact stems 45 can electrically connect the respective word line contact plugs 35 to respective upper interconnects, respectively. The via stems 46 can electrically connect the via plugs 36 to the upper interconnects. The via stems 41 can electrically connect the upper via plugs 31 to the upper interconnects. The vertical channel stems 40, the word line contact stems 45, the via stems 46, and the via stems 41 can be surrounded by an upper insulating layer 29 that can be disposed on the uppermost interlayer insulating layer 25T. The vertical channel stems 40, the word line contact stems 45, the via stems 46, and the via stems 41 can include a conductor such as polysilicon doped with N-type ions, a metal, a metal silicide, or a metal compound. The upper insulating layer 29 can include an insulating material such as silicon oxide.

[0037] FIG. 1B is a layout illustrating an arrangement of a lower via plug, an upper via plug, and a support pattern of a 3D semiconductor device according to an embodiment of the present disclosure. FIG. 1A is a layout illustrating an arrangement of a lower via plug, an upper via plug, and a support pattern of a 3D semiconductor device according to an embodiment of the present disclosure. FIG. 1B In the embodiment, it is assumed that each of the lower via plugs 21 has a smooth rectangular cross section, and each of the upper via plugs 31 has a circular cross section, so that the technical idea of the present disclosure can be easily understood. However, in other embodiments, such a structure can have a different cross-sectional shape. For example, the lower via plugs 21 can have a circular cross section. In FIG. 1B , it is assumed that the lower end of the upper via plug 31 completely overlaps the upper surface of the lower via plug 21. Referring to FIG. 1B , each of the support patterns 16 can be disposed to abut one side surface of each of the lower via plugs 21. As shown in , the length of the support pattern 16 can be greater than the length of one side of the lower via plug 21. The support pattern 16 and the lower via plug 21 can be disposed to partially overlap each other in the vertical direction. In the embodiment, the length of the support pattern 16 can be shorter than the length of one side of the lower via plug 21.

[0038] FIG. 1C is a layout illustrating an arrangement of a support pattern of a 3D semiconductor device according to an embodiment of the present disclosure. FIG. 1C , the support patterns 16 can be arranged in a matrix form in the row direction and the column direction. The support patterns 16 can have a rectangular segment shape or a square shape. That is, the support patterns 16 can be spaced apart from each other in the row direction and the column direction.

[0039] FIG. 1Dis a longitudinal sectional view showing misalignment of the lower via plug and the upper via plug in the 3D semiconductor device. Referring to FIG. 1D Even if the lower via plug 21 and the upper via plug 31 are misaligned, the upper via plug 31 can be kept in electrical connection with the lower via plug 21 through the conductive support pattern 16. That is, each support pattern 16 can increase the effective contact area between each lower via plug 21 and each upper via plug 31. Accordingly, each support pattern 16 can improve the alignment margin between each lower via plug 21 and each upper via plug 31. Thus, the support pattern 16 can mitigate the increase in the contact resistance between the lower via plug 21 and the upper via plug 31 when the lower via plug 21 and the upper via plug 31 are misaligned.

[0040] In FIG. 1A to 1D , the support pattern 16 is provided only on the right side of the lower via plug 21, but the support pattern 16 can also be provided on the left side of the lower via plug 21. In other embodiments, the support pattern 16 can be provided on the front side, the back side, or both the front side and the back side of the lower via plug 21.

[0041] FIG. 2A is a schematic longitudinal sectional view showing a 3D semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 2A , compared to the 3D semiconductor device 100A shown in FIG. 1A , the 3D semiconductor device 100B can include the support pattern 16 provided on both sides of the lower via plug 21. FIG. 2A The other elements in FIG. 1A are substantially the same as those in

[0042] FIG. 2B is a layout showing the alignment of the lower via plug, the upper via plug, and the support pattern, and FIG. 2C and FIG. 2D are layouts showing the support pattern of the 3D semiconductor device 100B according to an embodiment of the present disclosure.

[0043] Referring to FIG. 2B , each support pattern 16 can have a segment shape with a longer side than the corresponding side of the lower via plug 21. Each lower via plug 21 can be provided at the center of the corresponding pair of support patterns 16. For example, the support pattern 16 can be divided into a pair of support patterns 16 by the corresponding lower via plug 21.

[0044] Referring to FIG. 2C , the support pattern 16 can have a segment shape or a square shape, and can be arranged in a matrix form. Further referring to FIG. 2A and2B The lower via plug 21 can be disposed to overlap the middle region of the support pattern 16 in the row direction, the column direction, or both the row direction and the column direction.

[0045] Referring to FIG. 2D A pair of support patterns 16 can be disposed in contact with two corresponding side walls of the lower via plug 21. That is, FIG. 2C Each support pattern 16 illustrated can be divided into two. The lower via plug 21 can be disposed between the two support patterns 16. The lower via plug 21 can partially overlap the two support patterns 16 in the vertical direction. The pairs of support patterns 16 can be arranged in a matrix form.

[0046] FIG. 2E is a layout illustrating alignment of the lower via plug 21, the upper via plug 31, and the support pattern 16 of the 3D semiconductor device according to an embodiment of the disclosure. Referring to FIG. 2E Each support pattern 16 can be disposed to surround four side edges of each lower via plug 21. That is, the support pattern 16 can have a frame-like shape in a plan view. Each lower via plug 21 can be disposed to completely vertically overlap each support pattern 16.

[0047] In the embodiments disclosed herein, the support pattern 16 can compensate for a pattern density of the via in the via region VA. In addition, when the lower conductive layer 15 is formed in the cell region CA, a series of patterns in the via region VA can be formed at the same time and with the same material to form the support pattern 16, which can alleviate a patterning loading effect resulting from the pattern density of the via in the via region VA.

[0048] FIG. 3A to FIG. 3C is a longitudinal sectional view schematically illustrating a 3D semiconductor device according to various embodiments of the disclosure. Referring to FIG. 3A to FIG. 3C Each of the 3D semiconductor devices 100C-100E according to various embodiments of the disclosure can include a cell region CA, an extension region EA, and a via region VA between the cell region CA and the extension region EA. In one embodiment, the via region VA can be disposed in the cell region CA. In one embodiment, the via region VA can be disposed in the extension region EA.

[0049] Referring to FIG. 3A The 3D semiconductor device 100C is compared with FIG. 1AThe 3D semiconductor device 100A shown makes a comparison. The 3D semiconductor device 100C can include the dielectric layer stack DS, the lower via plug 21, the support pattern 16, the upper via plug 31, and the via post head 41 in the via region VA between the cell region CA and the extension region EA. The dielectric layer stack DS can include the first insulating layer 25 and the third insulating layer 27 that are alternately stacked. The third insulating layer 27 can include an insulating material that has etching selectivity with the first insulating layer 25. For example, the third insulating layer 27 can include the same material as the second insulating layer 26. The elements not described will be understood with reference to FIG. 1A FIG. 1A FIG. 3A In the above-described embodiments, the word lines 33 in the cell region CA and the word lines 33 in the extension region EA are shown as being separate, but these word lines can be electrically and physically connected.

[0050] With reference to FIG. 3B , the 3D semiconductor device 100D according to the embodiments of the present disclosure can further include the word lines 33 horizontally disposed between the third insulating layers 27 in the via region VA. In a top view or plan view, the third insulating layers 27 can have a ring-like shape that surrounds the sidewalls of the upper via plugs 31. The word lines 33 can surround the side surfaces of the third insulating layers 27. Thus, the word lines 33 can be horizontally electrically connected to each other and physically connected to each other. The elements not described will be understood with reference to FIG. 1A and FIG. 3A

[0051] With reference to FIG. 3C , the 3D semiconductor device 100E according to the embodiments of the present disclosure can further include the gap fill insulating layer 38 that surrounds the side surfaces of the upper via plugs 31 in the via region VA. The upper via plugs 31 can be disposed to vertically penetrate the gap fill insulating layer 38. The gap fill insulating layer 38 can include the same material as the middle insulating layer 28. The elements not described will be understood with reference to FIG. 1A and FIG. 3A

[0052] With reference to FIG. 1B to FIG. 1D and FIG. 2B to 2E The inventive concepts described with reference to the embodiments can be generally applied to the 3D semiconductor devices 100C-100E described with reference to FIG. 3A to FIG. 3C

[0053] FIG. 4A to FIG. 4I is a diagram illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the present disclosure. With reference to FIG. 4A , the method of manufacturing a 3D semiconductor device can include a step of forming the logic circuit components 11 to 13, the lower insulating layer 14, the lower conductive layer 15, and the support pattern 16 on the substrate 10.

[0054] ​​​​​The substrate 10 can include a semiconductor wafer. For example, the substrate 10 can include one of a silicon wafer, a silicon-on-insulator (SOI), an epitaxially grown semiconductor layer, or various other semiconductor layers. The substrate 10 can include a cell region CA, an extension region EA, and a via region VA.

[0055] The logic circuit components 11 to 13 can include MOS transistors 11, logic interconnects 12, and logic via plugs 13. The logic interconnects 12 and the logic via plugs 13 can include a conductor such as metal. A deposition process can be performed to form a lower insulating layer 14 that can include an insulating material such as silicon oxide.

[0056] The steps of forming the lower conductive layer 15 and the support pattern 16 can include forming a polysilicon layer doped with N-type ions on the lower insulating layer 14. The method can further include a step of performing a chemical mechanical polishing (CMP) process to planarize top surfaces of the lower conductive layer 15, the support pattern 16, and the lower insulating layer 14 to be coplanar. The lower conductive layer 15 and the support pattern 16 can serve as a CMP stopper or a CMP resistor. The support pattern 16 can prevent or mitigate the first insulating layer 14 in the via region VA from being concave due to the CMP process. The lower conductive layer 15 can be formed in a plate shape in the cell region CA and the extension region EA. Referring to FIG. 1C In a layout or a top view, the support pattern 16 can have one of a segment shape, a bar shape, and a square shape, and the support pattern 16 can be arranged in a matrix shape.

[0057] Referring to FIG. 4B The method can further include a step of forming a lower via hole 21H. The lower via hole 21H can selectively expose a surface of a portion of the logic interconnects 12 of the via region VA. The support pattern 16 can be contiguous with the lower via hole 21H. For example, a portion of the support pattern 16 can be removed. Accordingly, a sidewall of the support pattern 16 can be exposed on an inner sidewall of the lower via hole 21H.

[0058] Referring to FIG. 4CThe method can further include a step of filling the conductor in the lower via hole 21H to form a lower via hole plug 21. The lower via hole plug 21 can include at least one of polysilicon doped with N-type ions, a metal, a metal silicide, or a metal compound. In one embodiment, the lower via hole plug 21 can include at least one of tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), copper (Cu), or other transition metals or refractory metals. In one embodiment, the lower via hole plug 21 can include at least one of tungsten silicide (WSi), titanium silicide (TiSi), tantalum silicide (TaSi), nickel silicide (NiSi), cobalt silicide (CoSi), or other various metal silicides. In one embodiment, the lower via hole plug 21 can include one of tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), or other various metal nitrides. In one embodiment, the lower via hole plug 21 can include polysilicon doped with N-type ions. In one embodiment, a barrier layer can be formed between each lower via hole plug 21 and each support pattern 16. The barrier layer can include a metal silicide layer or a metal nitride layer. The method can further include performing a CMP process to planarize top surfaces of the lower via hole plugs 21. Accordingly, top surfaces of the lower via hole plugs 21, the lower conductive layer 15, the support patterns 16, and the lower insulating layer 14 can be coplanar. In the CMP process, the support patterns 16 can serve as a CMP stopper or a CMP blocker. That is, the support patterns 16 can prevent and mitigate the top surfaces of the lower via hole plugs 21 and the lower insulating layer 14 in the via area VA from being dented (forming a concave surface) due to the CMP process. The support patterns 16 can include the same material as the lower conductive layer 15. The support patterns 16 can have the same vertical thickness as the lower conductive layer 15.

[0059] Referring to FIG. 4D The method can further include a step of forming a dielectric layer stack DS on the logic device layer LD. The step of forming the dielectric layer stack DS can include a step of alternately stacking first insulating layers 25 and second insulating layers 26. For example, the first insulating layers 25 can include silicon oxide, and the second insulating layers 26 can include silicon nitride. The first insulating layers 25B and 25T stacked at the lowermost and uppermost of the dielectric layer stack DS can be formed relatively thicker than the other first insulating layers 25.

[0060] Referring to FIG. 4EThe method can include a step of patterning the first insulating layer 25 and the second insulating layer 26 in the extension area EA to form the staircase. Subsequently, in the extension area EA, the first insulating layer 25, 25B, and 25T and the second insulating layer 26 can be removed, and the intermediate insulating layer 28 can be used to fill the area from which the first insulating layer 25, 25B, and 25T and the second insulating layer 26 have been removed. The intermediate insulating layer 28 can include the same material as the first insulating layer 25.

[0061] Referring to FIG. 4F The method can further include a step of forming the vertical channel pillar 30 in the cell area CA. The vertical channel pillar 30 can include a central core insulating layer, a channel layer surrounding the core insulating layer, a memory layer surrounding the channel layer, and a tunnel insulating layer surrounding the memory layer. The vertical channel pillar 30 can be electrically connected to the lower conductive layer 15. For example, a lower end of the vertical channel pillar 30 can protrude into the lower conductive layer 15.

[0062] Referring to FIG. 4G The method can include a step of replacing the second insulating layer 26 with a conductive word line 33 in the cell area CA and the extension area EA to form a word line stack WS. For example, the method can include a step of performing a wet pull-back process to remove the second insulating layer 26, and a step of performing a deposition process to form a conductor such as silicon or metal in the space from which the second insulating layer 26 has been removed. However, in this step, the second insulating layer 26 in the via area VA can not be removed.

[0063] Referring to FIG. 4H The method can further include a step of forming a word line contact plug 35 in the extension area EA. The word line contact plug 35 can contact and connect with the end portions of the respective word lines 33 in the staircase, respectively. For example, the step of forming the word line contact plug 35 can include a step of forming a contact hole that penetrates the intermediate insulating layer 28 vertically and exposes an upper surface of the end portion of the word line 33, and a step of filling the contact hole with a conductive material.

[0064] Referring to FIG. 4IThe method can further include a step of forming the via plug 36 and the upper contact plug 31. The via plug 36 can be formed in the extension area EA. For example, the step of forming the via plug 36 can include a step of forming a via that penetrates the middle insulating layer 28 vertically and exposes a portion of the lower conductive layer 15 in the extension area EA, and a step of filling the via with a conductive material. The upper contact plug 31 can be formed in the via area VA. The step of forming the upper contact plug 31 can include a step of forming an upper via hole that penetrates the first insulating layer 25 and the second insulating layer 26 vertically and exposes a surface of the lower via plug 21 in the via area VA, and a step of filling the upper via hole with a conductive material.

[0065] Referring to FIG. 1A The method can include a step of sequentially forming the upper insulating layer 29, the vertical channel stem 40, the word line contact stem 45, the via stem 46, and the via stem 41.

[0066] The upper insulating layer 29 can include silicon oxide. The vertical channel stem 40 can penetrate the upper insulating layer 29 vertically to contact and electrically connect with each of the vertical channel pillars 30, respectively. The word line contact stem 45 can penetrate the upper insulating layer 29 vertically to contact and electrically connect with each of the word line contact plugs 35, respectively. The via stem 46 can penetrate the upper insulating layer 29 vertically to contact and electrically connect with the via plug 36. The via stem 41 can penetrate the upper insulating layer 29 vertically to contact and electrically connect with each of the upper via plugs 31, respectively. The vertical channel stem 40, the word line contact stem 45, the via stem 46, and the via stem 41 can include at least one of polysilicon doped with N-type ions, a metal, a metal silicide, or a metal compound.

[0067] FIG. 5A to FIG. 5C FIG. 1 is a diagram illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the disclosure. Referring to FIG. 5A The method of manufacturing a 3D semiconductor device can include a step of forming the logic circuit components 11 to 13, the lower insulating layer 14, the lower conductive layer 15, and the support pattern 16 on the substrate 10. Referring to FIG. 2C In a layout or a top view, the support pattern 16 can be arranged in a matrix form. The support pattern 16 can have one of a segment shape, a bar shape, and a square shape. In one embodiment, referring to FIG. 2E Each of the support patterns 16 can surround four side edges of each of the lower via plugs 21. For example, each of the support patterns 16 can form a frame of each of the lower via plugs 21 and contact the four side edges of each of the lower via plugs 21.

[0068] Referring to FIG. 2C and FIG. 5BThe method can include a step of forming lower via holes 21H vertically penetrating the support pattern 16 to expose a portion of the logic interconnect 12, the lower via holes 21H can have a square or rectangular shape. The support pattern 16 can be exposed on at least two inner sidewalls of the lower via holes 21H.

[0069] Referring to FIG. 5C , the method can include a step of forming lower via hole plugs 21 by filling the lower via holes 21H with a conductor. The sidewalls of each lower via hole 21H can be in contact with each support pattern 16.

[0070] The method can include sequentially performing the processes described above with reference to FIG. 4D to 4I to manufacture FIG. 2A the remaining elements of the 3D semiconductor device 100B shown. Elements not described in detail can be understood with reference to other figures.

[0071] FIG. 6 is a diagram illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the disclosure. Referring to FIG. 6 , the method of manufacturing a 3D semiconductor device according to an embodiment of the disclosure includes a step of forming logic circuit components 11 to 13, a lower insulating layer 14, a lower conductive layer 15, and a support pattern 16 on a substrate 10. Referring to FIG. 2D , in a layout or top view, two support patterns 16 can each have one of a segment shape, a bar shape, or a square shape in contact with one of two sidewalls of a lower via hole plug 21. For example, a pair of support patterns 16 can be disposed in contact with two corresponding sidewalls of one lower via hole plug 21 that can be disposed between the two support patterns 16. The lower via hole plug 21 can partially overlap the two support patterns 16 in a vertical direction. Elements and processes not described in detail can be understood with reference to other figures.

[0072] FIG. 7A to FIG. 7D is a diagram illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the disclosure. Referring to FIG. 7A , the method of manufacturing a 3D semiconductor device can include a step of performing the processes described with reference to FIG. 4A to FIG. 4H to form via holes 31H. The via holes 31H can vertically penetrate the word line stack WS in the via area VA to expose a surface of the lower via hole plug 21.

[0073] Referring to FIG. 7B , the method can further include a step of removing a word line 33 of the word line stack WS through the via hole 31H. For example, the word line 33 in the via area VA can be removed through a pullback process. The word line 33 can be removed to form a space S between the first insulating layers 25.

[0074] Referring toFIG. 7C The method can further include a step of forming the third insulating layer 27 in the space S using the via holes 31H. Although not shown, the third insulating layer 27 can also be formed on the inner walls of the via holes 31H.

[0075] Referring to FIG. 7D The method can include a step of forming the upper via plug 31 in the via holes 31H.

[0076] Referring to FIG. 3A The method further includes a step of sequentially forming the upper insulating layer 29, the vertical channel stem 40, the word line contact stem 45, the through hole stem 46, and the via stem 41. Elements and processes not described in detail can be understood with reference to other figures.

[0077] In one embodiment, the through hole plug 36 in the extension region EA can be formed simultaneously with the word line contact plug 35. In one embodiment, the through hole plug 36 in the extension region EA can be formed simultaneously with the upper via plug 31.

[0078] FIG. 8A And FIG. 8B is a diagram illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the disclosure. Referring to FIG. 8A The method of manufacturing a 3D semiconductor device can include a step of performing the processes described with reference to FIG. 4A to FIG. 4H And FIG. 7A to partially remove the word lines 33 through the via holes 31H, thereby forming a space S in the via region VA between the cell region CA and the extension region EA. For example, a portion of the word lines 33 can remain between the via holes 31H.

[0079] Referring to FIG. 8B The method can further include a step of forming the third insulating layer 27 in the space S through the via holes 31H.

[0080] Referring to FIG. 3B The method can further include a step of sequentially forming the upper insulating layer 29, the vertical channel stem 40, the word line contact stem 45, the through hole stem 46, and the via stem 41. Elements and processes not described in detail can be understood with reference to other figures.

[0081] FIG. 9A to FIG. 9C is a diagram illustrating a method of manufacturing a 3D semiconductor device according to an embodiment of the disclosure.

[0082] Referring to FIG. 9A The method of manufacturing a 3D semiconductor device can include a step of performing the processes described with reference to FIG. 4A to 4HThe described process removes the word line stack WS and fills the space from which the word line stack WS was removed with a gap fill insulating layer 38 in the via area VA.

[0083] Referring to FIG. 9B The method can further include a step of forming a via hole 31H that penetrates the gap fill insulating layer 38 vertically to expose a surface of the lower via plug 21.

[0084] Referring to FIG. 9C The method can further include a step of forming an upper via plug 31 that fills the via hole 31H.

[0085] Referring to FIG. 3C The method can further include a step of sequentially forming an upper insulating layer 29, a vertical channel stem 40, a word line contact stem 45, a via contact stem 46, and a via stem 41. Elements and processes not described in detail can be understood with reference to other figures.

[0086] FIG. 10 is a block diagram illustrating a configuration of a memory system according to an embodiment of the disclosure. Referring to FIG. 10 , the memory system 1000 can include a memory device 1200 and a controller 1100. The memory device 1200 can be used to store data information having various data forms such as text, graphics, and software code. The memory device 1200 can be a non-volatile memory. Further, the memory device 1200 can include FIG. 1A , FIG. 2A and FIG. 3A to FIG. 3CAt least one of the illustrated 3D semiconductor devices 100A-100E. The controller 1100 can be coupled to the host Host and the memory device 1200. The controller 1100 can access the memory device 1200 in response to a request from the host Host. For example, the controller 1100 can control reading, writing, erasing, and background operations of the memory device 1200. The controller can include at least one of a random access memory (RAM) 1110, a central processing unit (CPU) 1120, a host interface 1130, an error correction code (ECC) circuit 1140, and a memory interface 1150. The RAM 1110 can be used as an operation memory of the CPU 1120, a cache memory between the memory device 1200 and the host Host, and a buffer memory between the memory device 1200 and the host Host, etc. For reference, the RAM 1110 can be replaced with a static random access memory (SRAM) or a read only memory (ROM), etc. The CPU 1120 can control the overall operation of the controller 1100. For example, the CPU 1120 can operate firmware such as a flash translation layer (FTL) stored in the RAM 1110. The host interface 1130 can be interfaced with the host Host. For example, the controller 1100 can communicate with the host Host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol. The ECC circuit 1140 can detect and correct errors in data read from the memory device 1200 using an error correction code (ECC). The memory interface 1150 can be interfaced with the memory device 1200. For example, the memory interface 1150 can include a NAND interface or a NOR interface. For example, the controller 1100 can further include a buffer memory (not shown) for temporarily storing data. The buffer memory can be used to temporarily store data to be transferred from the host interface 1130 to an external device or data to be transferred from the memory interface 1150 to the memory device 1200. In addition, the controller 1100 can further include a ROM storing code data for interfacing with the host Host. Since the memory system 1000 according to the present embodiment can include the memory device 1200 having improved integration and characteristics due to the embodiments of the present disclosure, the integration and characteristics of the memory system 1000 can also be improved.

[0087] FIG. 11is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure. Hereinafter, duplicated explanations will be omitted if considered redundant. Referring to FIG. 11 , the memory system 1000' according to an embodiment can include a memory device 1200' and a controller 1100. Further, the controller 1100 can include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, and a memory interface 1150, etc. The memory device 1200' can include a non-volatile memory. Further, the memory device 1200' can have a 3D semiconductor device 100A-100E as illustrated in FIGS. 1, 2, 3, 4, and 5. In addition, the memory device 1200' can include a multi-chip package having a plurality of memory chips. The plurality of memory devices are divided into a plurality of groups. The plurality of groups can communicate with the controller 1100 through a first channel CH1 to a k-th channel CHk (where k is an integer). The memory chips of each group communicate with the controller 1100 through a common channel. For reference, the memory system 1000' can be modified such that each single memory chip is coupled to a corresponding single channel. As described above, since the memory system 1000' according to the present embodiment can include the memory device 1200' having improved integration and characteristics due to the embodiments of the present disclosure, the integration and characteristics of the memory system 1000' can also be improved. In particular, the memory device 1200' can include a multi-chip package, and thus the data storage capacity and operation speed thereof can be improved. FIG. 1A , FIG. 2A and FIG. 3A to FIG. 3C The memory device 1200' can include a 3D semiconductor device 100A-100E as illustrated in FIGS. 1, 2, 3, 4, and 5. In addition, the memory device 1200' can include a multi-chip package having a plurality of memory chips. The plurality of memory devices are divided into a plurality of groups. The plurality of groups can communicate with the controller 1100 through a first channel CH1 to a k-th channel CHk (where k is an integer). The memory chips of each group communicate with the controller 1100 through a common channel. For reference, the memory system 1000' can be modified such that each single memory chip is coupled to a corresponding single channel. As described above, since the memory system 1000' according to the present embodiment can include the memory device 1200' having improved integration and characteristics due to the embodiments of the present disclosure, the integration and characteristics of the memory system 1000' can also be improved. In particular, the memory device 1200' can include a multi-chip package, and thus the data storage capacity and operation speed thereof can be improved.

[0088] FIG. 12 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. Hereinafter, duplicated explanations will be omitted if considered redundant. Referring to FIG. 12 , the computing system 2000 according to an embodiment of the present disclosure can include a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, and a system bus 2600, etc. The memory device 2100 stores data provided via the user interface 2400, data processed by the CPU 2200, etc. Further, the memory device 2100 can be electrically coupled to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, etc. by the system bus 2600. For example, the memory device 2100 can be connected to the system bus 2600 through a controller (not shown), or can be directly connected to the system bus 2600. In the case where the memory device 2100 is directly coupled to the system bus 2600, the functions of the controller can be performed by the CPU 2200, the RAM 2300, etc. The memory device 2100 can include a non-volatile memory. The memory device 2100 can includeFIG. 1A , FIG. 2A and FIG. 3A to FIG. 3C at least one of the 3D semiconductor devices 100A-100E shown in FIGS. 1A-1E. Further, the memory device 2100 can include a multi-chip package including a plurality of memory chips as described with reference to FIG. 11 . The computing system 2000 can include one of a computer, an ultra-mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, one of various electronic devices capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, a computer network, or a remote management network, or an RFID device. As described above, since the computing system 2000 according to the present embodiment includes the memory device 2100 having improved integration and characteristics due to the embodiments of the present disclosure, the characteristics of the computing system 2000 can also be improved.

[0089] FIG. 13 is a block diagram illustrating a computing system according to an embodiment of the present disclosure. Referring to FIG. 13The computing system 3000 according to embodiments of this disclosure may include a software layer having an operating system 3200, applications 3100, a file system 3300, and a translation layer 3400, etc. Furthermore, the computing system 3000 may include a hardware layer such as a memory device 3500. The operating system 3200 can manage the software and hardware resources of the computing system 3000, and can control the program execution of the CPU. The applications 3100 may be various application programs executed in the computing system 3000, and may be utilities executed by the operating system 3200. The file system 3300 may refer to a logical structure for controlling data, files, etc., existing in the computing system 3000, and can organize files or data to be stored in the memory device 3500, etc., according to given rules. The file system 3300 may be determined according to the operating system 3200 used in the computing system 3000. For example, if the operating system 3200 is a Microsoft Windows system, the file system 3300 may be a File Allocation Table (FAT) or an NT File System (NTFS), etc. If the operating system 3200 is a Unix / Linux system, then the file system 3300 can be an Extended File System (EXT), a UNIX File System (UFS), or a Journal File System (JFS), etc. Although the operating system 3200, application 3100, and file system 3300 are represented by separate blocks in the accompanying drawings, application 3100 and file system 3300 can be included within the operating system 3200. In response to a request from the file system 3300, the translation layer 3400 can translate an address into a suitable form for the memory device 3500. For example, the translation layer 3400 can translate a logical address generated by the file system 3300 into a physical address of the memory device 3500. The mapping information between logical and physical addresses can be stored in an address translation table. For example, the translation layer 3400 can be a Flash Translation Layer (FTL) or a Universal Flash Storage Link Layer (ULL), etc. The memory device 3500 can be non-volatile memory. Furthermore, the memory device 3500 may include... FIG. 1A , FIG. 2A and FIG. 3A to FIG. 3C At least one of the 3D semiconductor devices 100A to 100E shown. As described above, since the computing system 3000 according to this embodiment may include a memory device 3500 with improved integration and characteristics due to the embodiments of this disclosure, the characteristics of the computing system 3000 can also be improved.

[0090] According to embodiments of this disclosure, the performance of semiconductor devices can be improved because the support pattern can prevent the formation of concave surfaces that occur in the CMP process and can increase the alignment margin of the contact plugs.

[0091] While this disclosure contains many specifics, these should not be construed as limiting the scope of the present teachings or of what can be claimed, but as describing features that can be specific to particular embodiments of the teachings. Certain features that are, for clarity, described above and below in the context of separate embodiments, can also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, can also be provided separately or in any suitable subcombination. In addition, while the above description has been made with respect to particular embodiments and illustrative examples, it is to be recognized that the application is not limited to the specific examples and embodiments described. The scope of the application includes various modifications, equivalents, and alternatives to the described embodiments and examples within the scope of the claims appended hereto. Furthermore, the application can take other alternative forms than the specific embodiments and examples described.

[0092] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring such order nor that all illustrated operations be performed, to achieve desirable results. In addition, the separation of various system components in the implementations described in this patent document should not be understood as requiring such separation in all implementations. Only a few implementations and examples are described and illustrated herein. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

[0093] Cross Reference to Related Applications

[0094] This application claims priority to Korean Patent Application No. 10-2020-0134946, filed on October 19, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate having a unit area and a through-hole area; Transistors and logic interconnects disposed on the substrate; A lower insulating layer that covers the transistor and the logic interconnect; A lower conductive layer, wherein the lower conductive layer is located on the lower insulating layer in the unit region; A support pattern is disposed on the lower insulating layer in the through-hole region; A lower through-hole plug, wherein the lower through-hole plug has a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnect in the through-hole region; The word lines are stacked, and the word lines are stacked on the lower conductive layer in the unit region; A dielectric layer is stacked on the support pattern and the lower insulating layer in the via region; Vertical channel posts, which penetrate the word line stack in the cell region to connect to the lower conductive layer; and An upper through-hole plug, wherein the upper through-hole plug penetrates the dielectric layer stack in the through-hole region to be aligned vertically with the lower through-hole plug.

2. The semiconductor device according to claim 1, wherein, The word line stack includes alternating layers of a first insulating layer and word lines, and The dielectric layer stack includes alternating layers of a first insulating layer and a second insulating layer.

3. The semiconductor device according to claim 2, wherein, The lower insulating layer and the first insulating layer comprise silicon oxide, and The second insulating layer comprises silicon nitride.

4. The semiconductor device according to claim 2, in, Each word line in the word line stack is at the same horizontal level as the corresponding second insulating layer in the dielectric layer stack in the vertical direction.

5. The semiconductor device according to claim 1, in, The lower conductive layer and the support pattern are made of the same material.

6. The semiconductor device according to claim 1, in, The lower conductive layer and the support pattern are positioned at the same horizontal level in the vertical direction.

7. The semiconductor device according to claim 1, in, The lower conductive layer and the support pattern have the same thickness in the vertical direction.

8. The semiconductor device according to claim 1, in, The side surface of the support pattern and the side surface of the lower through-hole plug are in contact with each other.

9. The semiconductor device according to claim 1, in, The thickness of the lower through-hole plug in the vertical direction is greater than the thickness of the support pattern in the vertical direction.

10. The semiconductor device according to claim 1, in, The lower conductive layer has a plate-like shape that occupies the unit area.

11. The semiconductor device according to claim 1, in, The top surface of the lower conductive layer, the top surface of the support pattern, the top surface of the lower through-hole plug, and the top surface of the lower insulating layer are coplanar.

12. The semiconductor device according to claim 1, in, The support pattern has a pair of segments shaped to contact at least two side surfaces of the lower through-hole plug, which has multiple side surfaces.

13. The semiconductor device according to claim 1, in, The support pattern has a frame shape in cross-section surrounding the lower through-hole plug.

14. The semiconductor device of claim 1, further comprising: The extended area and the word line contact plug disposed in the extended area, in, The word line contact plug is connected to the end of the word line in the extension region. The word line stack and the lower conductive layer extend toward the via region. The word line contact plug does not contact the lower conductive layer.

15. The semiconductor device of claim 14, further comprising: A via plug, wherein the via plug is connected to the lower conductive layer in the extended region. The through-hole plug does not contact the word lines that are stacked on top of each other.

16. The semiconductor device according to claim 14, in, The extended region is disposed between the unit region and the through-hole region.

17. The semiconductor device according to claim 1, in, The through-hole region is located in the unit region.

18. A semiconductor device comprising: Logic device layer and memory device layer stacked on the logic device layer, The logic device layer includes: A substrate having a unit area and a through-hole area; A logic interconnect disposed on the substrate; A lower conductive layer is disposed above the logic interconnect in the cell region; Lower through-hole plug, the lower through-hole plug contacting the logic interconnect in the through-hole region; and A support pattern is provided, wherein the support pattern contacts the side surface of the lower through-hole plug in the through-hole region. The storage device layer includes: The word line stack is disposed on the lower conductive layer in the unit region, and the word line stack includes alternating layers of a first insulating layer and word lines; A vertical channel post that penetrates the word line stack in the vertical direction in the cell region to connect to the lower conductive layer; A dielectric layer is stacked, and the dielectric layer stack is located in the via region; An upper peripheral contact plug, wherein the upper peripheral contact plug perpendicularly penetrates the dielectric layer stack in the through-hole region to be perpendicularly aligned with the lower through-hole plug. Wherein, the top surface of the supporting pattern and the top surface of the lower through-hole plug are coplanar, and The lower through-hole plug is higher in the vertical direction than the support pattern.

19. The semiconductor device according to claim 18, in, The dielectric layer stack includes alternating layers of a first insulating layer and a second insulating layer, and The first insulating layer and the second insulating layer are etch-selective relative to each other.

20. A semiconductor device comprising: A substrate having a unit region, an extension region, and a through-hole region; Transistors and logic interconnects disposed on the substrate; A lower conductive layer is disposed above the logic interconnect and the transistor in the cell region and the extended region; A support pattern and a lower through-hole plug are disposed on a lower insulating layer in the through-hole area; The word lines are stacked, and the word lines are stacked on the lower conductive layer in the unit area and the extension area; Vertical channel posts, which vertically penetrate the word line stack in the cell region to connect to the lower conductive layer; Word line contact plugs, the word line contact plugs being electrically connected to the word lines of the word line stack in the extended region respectively; A dielectric layer is stacked on top of the support pattern, the lower through-hole plug, and the lower insulating layer in the through-hole region; and An upper through-hole plug, wherein the upper through-hole plug vertically penetrates the dielectric layer stack to be vertically aligned with the lower through-hole plug. The side surface of the support pattern and the side surface of the lower through-hole plug are in contact with each other.

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