Level conversion circuit

Abstract

A level conversion circuit includes an input subcircuit, a first voltage supply subcircuit, a second voltage supply subcircuit, and an output subcircuit. The first voltage supply subcircuit is configured to connect the input and output subcircuits and provide a corresponding drain voltage for the CMOS transistors in the input subcircuit. The second voltage supply subcircuit is coupled to the first and second output terminals and is configured to provide a bias voltage to the first voltage supply subcircuit based on the level of the logic signals output by the first and second output terminals. The high level of the logic signals output by the first and second output terminals is greater than the high level of the first and second logic signals. Application of the above solution can improve the reliability of low-voltage CMOS transistors in the level conversion circuit.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a level conversion circuit. Background Art

[0002] Semiconductor memories generally include a level conversion circuit for converting a low-voltage logic signal into a high-voltage logic signal.

[0003] Figure 1 FIG. 1 is a schematic diagram of the structure of an existing level conversion circuit 10. Figure 1 As shown, the level conversion circuit 10 includes: PMOS transistors phvt1 to phvt4, and NMOS transistors nlvt1 and nlvt2. Among them, the PMOS transistors phvt1 to phvt4 are high-voltage CMOS transistors, and the NMOS transistors nlvt1 and nlvt2 are low-voltage CMOS transistors.

[0004] Taking the output voltage value of the power supply voltage output terminal VDDIO as 1.8V as an example, in the above-mentioned level conversion circuit 10, the drain voltage of the NMOS transistors nlvt1 and nlvt2 will exceed the nominal voltage (0.8V). At this time, the drain-gate voltage difference or the source-drain voltage difference of the NMOS transistors nlvt1 and nlvt2 will be overdriven, affecting the reliability of the NMOS transistors nlvt1 and nlvt2, and ultimately causing the level conversion circuit 10 to fail to operate normally. Summary of the Invention

[0005] The technical problem solved by the present invention is to improve the reliability of a low-voltage CMOS tube in a level conversion circuit.

[0006] To solve the above technical problems, an embodiment of the present invention provides a level conversion circuit, comprising: an input sub-circuit, a first voltage providing sub-circuit, a second voltage providing sub-circuit, and an output sub-circuit; wherein:

[0007] The input sub-circuit has a first input terminal and a second input terminal, adapted to input a first logic signal and a second logic signal with opposite phases;

[0008] The output sub-circuit has a first output terminal and a second output terminal, and is adapted to convert the levels of the first logic signal and the second logic signal to required level values and output them at the first output terminal and the second output terminal;

[0009] The first voltage providing subcircuit is used to connect the input subcircuit and the output subcircuit, and provide an appropriate drain voltage for the CMOS transistor in the input subcircuit;

[0010] The second voltage providing subcircuit is coupled to the first output terminal and the second output terminal, and is adapted to provide a bias voltage for the first voltage providing subcircuit based on the level values of the logic signals outputted by the first output terminal and the second output terminal;

[0011] The high level values of the logic signals outputted by the first output terminal and the second output terminal are greater than the high level values of the first logic signal and the second logic signal.

[0012] Optionally, the second voltage providing sub-circuit includes:

[0013] a first bias voltage providing module, coupled to the second output terminal, and adapted to output a first signal to be compared based on a level value of a logic signal outputted by the second output terminal;

[0014] a second bias voltage providing module, coupled to the first output terminal, and adapted to output a second signal to be compared based on a level value of the logic signal outputted by the first output terminal;

[0015] The comparison module has an input end connected to the first bias voltage providing module and the second bias voltage providing module, and is suitable for comparing the level values of the first signal to be compared and the second signal to be compared, selecting the larger one as the bias voltage, and outputting it to the first voltage providing sub-circuit.

[0016] Optionally, the first bias voltage providing module includes: two or more ninth NMOS transistors, one tenth NMOS transistor, and one eleventh NMOS transistor connected in series in sequence;

[0017] The gate and drain of the ninth NMOS transistor are connected, the gate of the tenth NMOS transistor is coupled to the second power supply voltage output terminal; the gate of the eleventh NMOS transistor is coupled to the first input terminal, and the source of the eleventh NMOS transistor is grounded.

[0018] Optionally, the first bias voltage providing module further includes: a twelfth NMOS transistor connected in series between the ninth NMOS transistor and the tenth NMOS transistor.

[0019] Optionally, the number of the ninth NMOS tubes is 3.

[0020] Optionally, the structure of the first bias voltage providing module is the same as that of the second bias voltage providing module.

[0021] Optionally, the comparison module includes: a first PMOS transistor and a second PMOS transistor;

[0022] The drain of the first PMOS transistor is coupled to the source of the ninth NMOS transistor in the first bias voltage providing module; the drain of the second PMOS transistor is coupled to the source of the ninth NMOS transistor in the second bias voltage providing module; the gate of the first PMOS transistor is coupled to the drain of the second PMOS transistor, and the gate of the second PMOS transistor is coupled to the drain of the first PMOS transistor; and the sources of the first and second PMOS transistors are coupled to the first voltage providing sub-circuit.

[0023] Optionally, the input sub-circuit includes: a first NMOS transistor and a second NMOS transistor; wherein:

[0024] The gate of the first NMOS transistor serves as the first input terminal, and the gate of the second NMOS transistor serves as the second input terminal; the drains of the first NMOS transistor and the second NMOS transistor are coupled to the first voltage providing sub-circuit; and the sources of the first NMOS transistor and the second NMOS transistor are grounded.

[0025] Optionally, the first voltage providing sub-circuit includes: a third NMOS transistor and a fourth NMOS transistor, wherein:

[0026] The gates of the third NMOS transistor and the fourth NMOS transistor are coupled to the second voltage providing sub-circuit; the source of the third NMOS transistor is coupled to the first NMOS transistor, the source of the fourth NMOS transistor is coupled to the second NMOS transistor, and the drains of the third NMOS transistor and the fourth NMOS transistor are coupled to the output sub-circuit.

[0027] Optionally, the first voltage providing sub-circuit further includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; wherein:

[0028] The drains of the fifth and sixth NMOS transistors are coupled to the output sub-circuit; the source of the fifth NMOS transistor is coupled to the third NMOS transistor, and the source of the sixth NMOS transistor is coupled to the fourth NMOS transistor; the gates of the fifth and sixth NMOS transistors are coupled to the first power supply voltage output terminal;

[0029] The drain of the seventh NMOS transistor is coupled to the third NMOS transistor, the drain of the eighth NMOS transistor is coupled to the fourth NMOS transistor, the source of the seventh NMOS transistor is coupled to the first NMOS transistor, the source of the eighth NMOS transistor is coupled to the second NMOS transistor, and the gates of the seventh and eighth NMOS transistors are coupled to the second power supply voltage output terminal;

[0030] The voltage value outputted by the second power supply voltage output terminal is smaller than the voltage value outputted by the first power supply voltage output terminal.

[0031] Optionally, the output sub-circuit includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; wherein:

[0032] The sources of the third and fourth PMOS transistors are coupled to the first power supply voltage output terminal; the third PMOS transistor is connected in series with the fifth PMOS transistor, and the gate of the third PMOS transistor is coupled to the drain of the sixth PMOS transistor; the fourth PMOS transistor is connected in series with the sixth PMOS transistor, and the gate of the fourth PMOS transistor is coupled to the drain of the fifth PMOS transistor.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0034] With the above solution, the first voltage-supplying subcircuit connects the input and output subcircuits and provides an appropriate drain voltage for the CMOS transistors in the input subcircuit. This prevents overdriving of the drains of the CMOS transistors in the input subcircuit, improving the reliability of the CMOS transistors in the input subcircuit and, consequently, the reliability of the level shifter circuit. Furthermore, the second voltage-supplying subcircuit provides a bias voltage for the first voltage-supplying subcircuit based on the levels of the logic signals output by the first and second output terminals. This ensures the reliability of each component in the first voltage-supplying subcircuit, avoids the need for an additional bias voltage source, and minimizes circuit area. Therefore, the solution of the present invention improves the reliability of the level shifter circuit while minimizing circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural diagram of a level conversion circuit;

[0036] Figure 2 1 is a schematic structural diagram of a level conversion circuit according to an embodiment of the present invention;

[0037] Figure 3 is a schematic structural diagram of another level conversion circuit in an embodiment of the present invention;

[0038] Figure 4 FIG. 4 is a schematic structural diagram of another level conversion circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] like Figure 1As shown, the level conversion circuit 10 includes: PMOS transistors phvt1 to phvt4, and NMOS transistors nlvt1 and nlvt2. Among them, the PMOS transistors phvt1 to phvt4 are high-voltage CMOS transistors, and the NMOS transistors nlvt1 and nlvt2 are low-voltage CMOS transistors.

[0040] The gates of the PMOS transistor phvt1 and the NMOS transistor nlvt1 are both connected to the first input terminal IN. The gates of the PMOS transistor phvt2 and the NMOS transistor nlvt2 are both connected to the second input terminal INb. The gate of the PMOS transistor phvt3 is connected to the drain of the PMOS transistor phvt2 and serves as the first output terminal Out. The gate of the PMOS transistor phvt4 is connected to the drain of the PMOS transistor phvt1 and serves as the second output terminal Outb.

[0041] When the voltage of the logic signal input to the first input terminal IN is high, the NMOS transistor nlvt1 is turned on, causing the PMOS transistor phvt4 to be turned on. The NMOS transistor nlvt2 is turned off, and the PMOS transistor phvt2 is turned on, causing the voltage of the first output terminal OUT to be high. Correspondingly, the voltage of the second output terminal OUTb is low.

[0042] When the voltage of the logic signal input to the first input terminal IN is low, the NMOS transistor nlvt1 is turned off, the PMOS transistor phvt1 is turned on, the NMOS transistor nlvt2 is turned on, and the PMOS transistor phvt3 is turned on, ultimately making the voltage of the second output terminal Outb high. Correspondingly, the voltage of the first output terminal Out is low.

[0043] In a specific implementation, taking the voltage value output by the power supply voltage output terminal VDDIO as 1.8V as an example, in the above-mentioned level conversion circuit 10, the drain voltage of the NMOS transistors nlvt1 and nlvt2 will exceed the nominal voltage (0.8V). At this time, the NMOS transistors nlvt1 and nlvt2 themselves will be overdriven, affecting the reliability of the NMOS transistors nlvt1 and nlvt2, and ultimately causing the level conversion circuit 10 to fail to operate normally.

[0044] To address the aforementioned issues, embodiments of the present invention provide a level conversion circuit. The level conversion circuit includes a first voltage supply subcircuit, which connects an input subcircuit and an output subcircuit and provides a suitable drain voltage for the CMOS transistors in the input subcircuit. This prevents overdriving of the CMOS transistors in the input subcircuit due to a drain-to-gate voltage difference or a drain-to-source voltage difference, thereby improving the reliability of the CMOS transistors in the input subcircuit. Furthermore, a second voltage supply subcircuit provides a bias voltage to the first voltage supply subcircuit based on the level values of the logic signals output by the first and second output terminals. This ensures the reliability of each component in the first voltage supply subcircuit, avoids the need for an additional bias voltage source, and minimizes circuit area. Therefore, the present invention improves the reliability of the level conversion circuit while minimizing circuit area.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Reference Figure 2 , an embodiment of the present invention provides a level conversion circuit 20 for converting an input low-voltage logic signal into a high-voltage logic signal.

[0047] Specifically, the level conversion circuit 20 may include: an input sub-circuit 21, a first voltage providing sub-circuit 22, a second voltage providing sub-circuit 23 and an output sub-circuit 24.

[0048] The input sub-circuit 21 has a first input terminal IN and a second input terminal INb, adapted to input a first logic signal and a second logic signal with opposite phases;

[0049] The output sub-circuit 24 has a first output terminal OUT and a second output terminal OUTb, and is adapted to convert the levels of the first logic signal and the second logic signal to required levels and output them at the first output terminal OUT and the second output terminal OUTb;

[0050] The first voltage providing subcircuit 22 is used to connect the input subcircuit 21 and the output subcircuit 24, and provide an appropriate drain voltage for the CMOS transistor in the input subcircuit 21;

[0051] The second voltage providing sub-circuit 23 is coupled to the first output terminal OUT and the second output terminal OUTb, and is adapted to provide a bias voltage to the first voltage providing sub-circuit 22 based on the level values of the logic signals outputted by the first output terminal OUT and the second output terminal OUTb;

[0052] The high level value of the logic signal output by the first output terminal OUT and the second output terminal OUTb is greater than the high level value of the first logic signal and the second logic signal

[0053] Since the first voltage providing subcircuit 22 can connect the input subcircuit 21 and the output subcircuit 24 and provide an appropriate drain voltage for the CMOS transistor in the input subcircuit 21, the overdriving problem caused by the excessive drain voltage of the CMOS transistor in the input subcircuit 21 can be avoided, thereby improving the reliability of the CMOS transistor in the input subcircuit 21.

[0054] In a specific implementation, the high level of the first logic signal and the second logic signal can be greater than or equal to 0.54 V, and the low level is 0 V. The high level of the logic signals output by the first output terminal OUT and the second output terminal OUTb can be approximately 1.8 V, for example, 1.98 (i.e., 1.8+10%*1.8) V or 1.62 (i.e., 1.8-10%*1.8) V.

[0055] Since the high-level values of the logic signals output by the first output terminal OUT and the second output terminal OUTb are determined by the voltage value output by the first power supply voltage output terminal VDDIO, the voltage value output by the first power supply voltage output terminal VDDIO is the same as the high-level values of the logic signals output by the first output terminal OUT and the second output terminal OUTb, which should also be approximately 1.8V.

[0056] In one embodiment of the present invention, Figure 3 As shown, the input sub-circuit 21 may include: a first NMOS transistor lvt1 and a second NMOS transistor lvt2.

[0057] The gate of the first NMOS transistor lvt1 serves as the first input terminal IN, and the gate of the second NMOS transistor lvt2 serves as the second input terminal INb; the drains of the first NMOS transistor lvt1 and the second NMOS transistor lvt2 are coupled to the first voltage providing sub-circuit 22; and the sources of the first NMOS transistor lvt1 and the second NMOS transistor lvt2 are grounded GND.

[0058] The gate of the first NMOS transistor lvt1 can receive a first logic signal, and the gate of the second NMOS transistor lvt2 can receive a second logic signal. The first and second logic signals have opposite phases. When the voltage value of the first logic signal is high and the voltage value of the second logic signal is low, the first NMOS transistor lvt1 can amplify the first logic signal and transmit it to the first output terminal OUT. When the voltage value of the first logic signal is low and the voltage value of the second logic signal is high, the second NMOS transistor lvt2 can amplify the second logic signal and transmit it to the second output terminal OUTb.

[0059] In practice, CMOS transistors can be divided into high-voltage and low-voltage CMOS transistors based on the thickness of the gate oxide layer and the actual manufacturing process. Compared to low-voltage CMOS transistors, high-voltage CMOS transistors can operate normally in a higher voltage range.

[0060] The higher the voltage a CMOS transistor can operate at, the higher its threshold voltage. For example, at the 14nm process node, the threshold voltage of a high-voltage CMOS transistor is approximately 0.4V, while the threshold voltage of a low-voltage CMOS transistor is approximately 0.3V.

[0061] In an embodiment of the present invention, the first NMOS transistor lvt1 and the second NMOS transistor lvt2 are low-voltage CMOS transistors.

[0062] In a specific implementation, the first voltage providing sub-circuit 22 can be implemented using a variety of circuit structures, which are not specifically limited.

[0063] In one embodiment of the present invention, the first voltage providing sub-circuit 22 may only include: a third NMOS transistor nhvt1 and a fourth NMOS transistor nhvt2.

[0064] The gates of the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2 are coupled to the second voltage providing sub-circuit 23; the source of the third NMOS transistor nhvt1 is coupled to the first NMOS transistor lvt1, the source of the fourth NMOS transistor nhvt2 is coupled to the second NMOS transistor lvt2, and the drains of the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2 are coupled to the output sub-circuit 24.

[0065] In some application scenarios, only the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2 are provided between the output sub-circuit 24 and the input sub-circuit 21, so as to provide an appropriate drain voltage for the first NMOS transistor lvt1 and the second NMOS transistor lvt2, thereby avoiding the overdriving problem of the first NMOS transistor lvt1 and the second NMOS transistor lvt2.

[0066] For example, the threshold voltage of the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2 is Vtn. When the voltage outputted by the first power supply voltage output terminal VDDIO is low, i.e., the difference between the voltage outputted by the first power supply voltage output terminal VDDIO and the high level value of the input logic signal is small, the actual drain voltage of the first NMOS transistor lvt1 and the second NMOS transistor lvt2 is the difference between the voltage outputted by the first power supply voltage output terminal VDDIO and the threshold voltage Vtn. This difference enables the first NMOS transistor lvt1 and the second NMOS transistor lvt2 to operate normally, avoiding overdrive issues. In other words, by only using the third NMOS transistor nhvt1 or the fourth NMOS transistor nhvt2 to step down the voltage outputted by the first power supply voltage output terminal VDDIO, an appropriate drain voltage can be provided for the first NMOS transistor lvt1 and the second NMOS transistor lvt2.

[0067] In a specific implementation, the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2 are high-voltage CMOS transistors.

[0068] In another embodiment of the present invention, Figure 3 As shown, in addition to the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2, the first voltage supply sub-circuit 22 may further include: a fifth NMOS transistor nhvt3, a sixth NMOS transistor nhvt4, a seventh NMOS transistor lvt3 and an eighth NMOS transistor lvt4.

[0069] The drains of the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4 are coupled to the output sub-circuit 24; the source of the fifth NMOS transistor nhvt3 is coupled to the third NMOS transistor nhvt1, and the source of the sixth NMOS transistor nhvt4 is coupled to the fourth NMOS transistor nhvt2; the gates of the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4 are coupled to the first power supply voltage output terminal VDDIO.

[0070] A drain of the seventh NMOS transistor lvt3 is coupled to the third NMOS transistor nhvt1, a drain of the eighth NMOS transistor lvt4 is coupled to the fourth NMOS transistor nhvt2, a source of the seventh NMOS transistor lvt3 is coupled to the first NMOS transistor lvt1, a source of the eighth NMOS transistor lvt4 is coupled to the second NMOS transistor lvt2, and gates of the seventh NMOS transistor lvt3 and the eighth NMOS transistor lvt4 are coupled to the second power supply voltage output terminal VDD.

[0071] The voltage value outputted by the second power supply voltage output terminal VDD is smaller than the voltage value outputted by the first power supply voltage output terminal VDDIO.

[0072] In a specific implementation, the voltage value output by the second power supply voltage output terminal VDD is the same as the high level value of the first logic signal and the second logic signal. For example, when the high level value of the first logic signal and the second logic signal is 0.54V, the voltage value output by the second power supply voltage output terminal VDD can also be 0.54V.

[0073] In a specific implementation, the seventh NMOS transistor lvt3 is used to protect the first NMOS transistor lvt1, preventing the first NMOS transistor lvt1 from overdriving. The eighth NMOS transistor lvt4 is used to protect the second NMOS transistor lvt2, preventing the second NMOS transistor lvt2 from overdriving. The third NMOS transistor nhvt1 is used to protect the seventh NMOS transistor lvt3, preventing the seventh NMOS transistor lvt3 from overdriving. The fourth NMOS transistor nhvt2 is used to protect the eighth NMOS transistor lvt4, preventing the eighth NMOS transistor lvt4 from overdriving. The fifth NMOS transistor nhvt3 is used to protect the seventh NMOS transistor lvt3 and the first NMOS transistor lvt1, preventing the seventh NMOS transistor lvt3 and the first NMOS transistor lvt1 from overdriving. The sixth NMOS transistor nhvt4 is used to protect the eighth NMOS transistor lvt4 and the second NMOS transistor lvt2, preventing the eighth NMOS transistor lvt4 and the second NMOS transistor lvt2 from overdriving.

[0074] During the actual level conversion process, each NMOS transistor in the first voltage providing subcircuit 22 is always conductive. This allows the output terminal to quickly perform a logic conversion when the level of the logic signal inputted at the input terminal changes, thereby improving the level conversion speed. For example, when the level value of the first output terminal OUT is high and the level value of the second output terminal OUTb is low, if the level of the input logic signal changes, the first voltage providing subcircuit 22 can quickly change the level value of the first output terminal OUT from high to low, and the level value of the second output terminal OUTb from low to high.

[0075] In a specific implementation, the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4 are high-voltage CMOS transistors, and the seventh NMOS transistor lvt3 and the eighth NMOS transistor lvt4 are low-voltage NMOS transistors.

[0076] It is understandable that when the first power supply voltage output terminal VDDIO is relatively large, the number of NMOS transistors in the first voltage providing sub-circuit 22 can be reasonably set according to the voltage value of the voltage output by the first power supply voltage output terminal VDDIO, as long as it can be ensured that the NMOS transistors in the first voltage providing sub-circuit 22 and the input sub-circuit 21 operate at appropriate voltages and avoid overdriving problems.

[0077] In a specific implementation, the second bias voltage providing module 23 can be implemented using a variety of circuit structures without specific limitation, as long as it can provide a bias voltage for the first voltage providing sub-circuit 22 based on the level value of the logic signal output by the first output terminal OUT and the second output terminal OUTb.

[0078] In one embodiment of the present invention, referring to Figure 2 The second voltage providing subcircuit 23 may include: a first bias voltage providing module 231, a second bias voltage providing module 232 and a comparison module 233.

[0079] The first bias voltage providing module 231 is coupled to the second output terminal OUTb and is adapted to output a first comparison signal A based on a level value of a logic signal outputted by the second output terminal OUTb;

[0080] The second bias voltage providing module 232 is coupled to the first output terminal OUT, and is adapted to output a second comparison signal B based on the level value of the logic signal outputted by the first output terminal OUT;

[0081] The comparison module 233 has its input end connected to the first bias voltage providing module 231 and the second bias voltage providing module 232, and is adapted to compare the level values of the first signal to be compared A and the second signal to be compared B, select the larger one as the bias voltage, and output it to the first voltage providing sub-circuit 22.

[0082] In a specific implementation, the circuit structures of the first bias voltage providing module 231 and the second bias voltage providing module 232 can be the same or different, without any specific limitation, as long as they can output corresponding signals to be compared based on the level values of the logic signals output by the corresponding output terminals.

[0083] To reduce design difficulty, in the embodiment of the present invention, the first bias voltage providing module 231 and the second bias voltage providing module 232 have the same circuit structure.

[0084] In one embodiment of the present invention, referring to Figure 3The first bias voltage providing module 231 may include: two or more ninth NMOS transistors, a tenth NMOS transistor lvtb3 and an eleventh NMOS transistor lvtb1 connected in series in sequence;

[0085] The gate and drain of the ninth NMOS transistor are connected, the gate of the tenth NMOS transistor lvtb3 is coupled to the second power supply voltage output terminal VDD; the gate of the eleventh NMOS transistor lvtb1 is coupled to the first input terminal IN, and the source of the eleventh NMOS transistor lvtb1 is grounded.

[0086] In a specific implementation, the number of the ninth NMOS transistors may be only two, or three or more, and may be set specifically according to the voltage value output by the first power supply voltage output terminal VDDIO. Figure 3 In the embodiment, the number of the ninth NMOS transistors is three, namely the ninth NMOS transistors hvtb3, hvtb5 and hvtb7.

[0087] The ninth NMOS transistors hvtb3, hvtb5, and hvtb7 can, when the level value of the second output terminal OUTb is high, step down the high level value of the second output terminal OUTb, so that the tenth NMOS transistor lvtb3 can obtain an appropriate drain voltage, thereby avoiding an overdrive problem of the tenth NMOS transistor lvtb3.

[0088] The eleventh NMOS transistor lvtb1 is controlled to be turned on or off by the first logic signal inputted by the first input terminal IN. Thus, when the first logic signal is at a high level, the first bias voltage providing module 231 is turned on, that is, the second output terminal OUTb is connected to the ground line, on the one hand, providing a bias voltage for the first voltage providing sub-circuit 22, and on the other hand, quickly pulling down the second output terminal OUTb to a low level.

[0089] The tenth NMOS transistor lvtb3 is used to protect the eleventh NMOS transistor lvtb1 to prevent the eleventh NMOS transistor lvtb1 from being overdriven.

[0090] Likewise, if Figure 3 As shown, the second bias voltage providing module 232 may also include three ninth NMOS transistors (i.e., ninth NMOS transistors hvtb8, hvtb6, and hvtb4), one tenth NMOS transistor lvtb4, and one eleventh NMOS transistor lvtb2. The gate of the tenth NMOS transistor lvtb4 is coupled to the second power supply voltage output terminal VDD. The gate of the eleventh NMOS transistor lvtb2 is coupled to the second input terminal INb.

[0091] The ninth NMOS transistors hvtb8, hvtb6 and hvtb4 can, when the level value of the first output terminal OUT is high, step down the high level value of the first output terminal OUT, so that the tenth NMOS transistor lvtb4 can obtain an appropriate drain voltage, thereby avoiding an overdrive problem of the tenth NMOS transistor lvtb4.

[0092] The eleventh NMOS transistor lvtb2 is controlled to be turned on or off by the second logic signal inputted by the second input terminal INb, thereby turning on the second bias voltage providing module 232 when the first logic signal is at a high level, that is, connecting the first output terminal OUT to the ground line, on the one hand providing a bias voltage for the first voltage providing sub-circuit 22, and on the other hand quickly pulling the first output terminal OUT down to a low level.

[0093] The tenth NMOS transistor lvtb4 is used to protect the eleventh NMOS transistor lvtb2 to prevent the eleventh NMOS transistor lvtb2 from being overdriven.

[0094] In a specific implementation, the ninth NMOS transistors hvtb3 to hvtb8 are high-voltage NMOS transistors, the tenth NMOS transistors lvtb3 and lvtb4 are low-voltage NMOS transistors, and the eleventh NMOS transistors lvtb1 and lvtb2 are low-voltage NMOS transistors.

[0095] In another embodiment of the present invention, Figure 4 As shown, the first bias voltage providing module 231 may further include: a twelfth NMOS transistor hvtb1 connected in series between the ninth NMOS transistor hvtb3 and the tenth NMOS transistor lvtb3.

[0096] In a specific implementation, the gate of the twelfth NMOS transistor hvtb1 can be coupled to the control signal output terminal VDD18. The control signal output terminal VDD18 can output a high-level control signal to control the twelfth NMOS transistor hvtb1 to be turned on when the first power supply voltage output terminal VDDIO normally outputs a voltage, that is, outputs a stable power supply voltage.

[0097] Likewise, if Figure 4 As shown, the second bias voltage providing module 232 may include a twelfth NMOS transistor hvtb2 connected in series between the ninth NMOS transistor hvtb4 and the tenth NMOS transistor lvtb4. The gate of the twelfth NMOS transistor hvtb2 is also connected to the control signal output terminal VDD18. The twelfth NMOS transistor hvtb2 is configured to protect the tenth NMOS transistor lvtb4 and the eleventh NMOS transistor lvtb2, thereby preventing overdrive of the tenth NMOS transistor lvtb4 and the eleventh NMOS transistor lvtb2.

[0098] In a specific implementation, the voltage value of the control signal is equal to the power supply voltage value output by the first power supply voltage output terminal VDDIO. The twelfth NMOS transistor hvtb1 can protect the eleventh NMOS transistor lvtb1 and the tenth NMOS transistor lvtb3, avoiding overdriving problems of the eleventh NMOS transistor lvtb1 and the tenth NMOS transistor lvtb3.

[0099] In a specific implementation, the comparison module 232 can be implemented using a variety of circuit structures, which are not specifically limited.

[0100] In one embodiment of the present invention, the comparison module 232 may include: a first PMOS transistor phvtc1 and a second PMOS transistor phvtc2.

[0101] The drain of the first PMOS transistor phvtc1 is coupled to the source of the ninth NMOS transistor in the first bias voltage providing module 231; the drain of the second PMOS transistor phvtc2 is coupled to the source of the ninth NMOS transistor in the second bias voltage providing module 233; the gate of the first PMOS transistor phvtc1 is coupled to the drain of the second PMOS transistor phvtc2, and the gate of the second PMOS transistor phvtc2 is coupled to the drain of the first PMOS transistor phvtc1; the sources of the first PMOS transistor phvtc1 and the second PMOS transistor phvtc2 are coupled to the first voltage providing sub-circuit.

[0102] In a specific implementation, the first PMOS transistor phvtc1 and the second PMOS transistor phvtc2 may both be connected to the first power supply voltage output terminal VDDIO.

[0103] In a specific implementation, there may be multiple ninth NMOS transistors in the first bias voltage providing module 231. Specifically, the first PMOS transistor phvtc1 may be connected to the source of one of the ninth NMOS transistors according to the voltage value output by the first power supply voltage output terminal VDDIO. As long as the bias voltage provided by the first comparison result can prevent the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4 from being overdriven when the comparison module 232 outputs the first comparison result to provide a bias voltage for the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4, it is sufficient.

[0104] Similarly, there may be multiple ninth NMOS transistors in the second bias voltage providing module 233. Specifically, the second PMOS transistor phvtc2 may be connected to the source of one of the ninth NMOS transistors according to the voltage value output by the first power supply voltage output terminal VDDIO. As long as the bias voltage provided by the second result to be compared can prevent the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4 from being overdriven when the comparison module 232 outputs the second result to be compared to provide a bias voltage for the fifth NMOS transistor nhvt3 and the sixth NMOS transistor nhvt4, it is sufficient.

[0105] For example, in Figure 3 and Figure 4 When the voltage output by the first power supply voltage output terminal VDDIO is about 1.8V, the drain of the first PMOS transistor phvtc1 can be connected to the source of the ninth NMOS transistor hvtb4, and the drain of the first PMOS transistor phvtc1 can be connected to the source of the ninth NMOS transistor hvtb3.

[0106] Thus, when the first logic signal is at a low level, the second output terminal OUTb outputs a logic high level signal, and the source voltage of the twelfth NMOS transistor hvtb1 is at most: V1-Vtn, where V1 is the voltage value output by the control signal output terminal VDD18, V1 is equal to the voltage value output by the first power supply voltage output terminal VDDIO, and Vtn is the threshold voltage of the first PMOS transistor phvtc1.

[0107] That is, after the logic-high level output by the second output terminal OUTb is stepped down by the ninth NMOS transistors hvtb3, hvtb5, and hvtb7, the resulting voltage is at most V1-Vtn. The logic-high level output by the second output terminal OUTb is the voltage value output by the first power supply voltage output terminal VDDIO, that is, V1. Therefore, the ninth NMOS transistors hvtb3, hvtb5, and hvtb7 effectively reduce the logic-high level output by the second output terminal OUTb by [V1-(V1-Vtn)]=Vtn. Therefore, when there are three ninth NMOS transistors, the voltage of the logic-high level output by the second output terminal OUTb decreases by Vtn / 3 each time it passes through a ninth NMOS transistor. Therefore, the logic-high level of the first comparison result signal A should be V1-Vtn / 3.

[0108] Likewise, when the second logic signal is at a low level, the logic high level of the second comparison result signal B should also be V1 - Vtn / 3.

[0109] The comparison module 232 selects the one with the higher logic level between the first comparison result signal A and the second comparison result signal B, and outputs it to the gates of the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2 to provide bias voltage for the third NMOS transistor nhvt1 and the fourth NMOS transistor nhvt2.

[0110] It can be understood that when the first bias voltage providing module 231 and the second bias voltage providing module 232 respectively include N or more ninth NMOS transistors, the voltage of the logic high level output by the second output terminal OUTb drops by Vtn / N each time it passes through a ninth NMOS transistor, where N is a positive integer greater than or equal to 4. Specifically, the number of ninth NMOS transistors can be set according to the voltage value output by the first power supply voltage output terminal VDDIO.

[0111] In one embodiment of the present invention, the output sub-circuit 24 includes: a third PMOS transistor phvt3, a fourth PMOS transistor phvt4, a fifth PMOS transistor phvt1, and a sixth PMOS transistor phvt2.

[0112] The sources of the third PMOS transistor phvt3 and the fourth PMOS transistor phvt4 are coupled to the first power supply voltage output terminal VDDIO; the third PMOS transistor phvt3 is connected in series with the fifth PMOS transistor phvt1, and the gate of the third PMOS transistor phvt3 is coupled to the drain of the sixth PMOS transistor phvt2; the fourth PMOS transistor phvt4 is connected in series with the sixth PMOS transistor phvt2, and the gate of the fourth PMOS transistor phvt4 is coupled to the drain of the fifth PMOS transistor phvt1.

[0113] In a specific implementation, the gate of the fifth PMOS transistor phvt1 is connected to the first input terminal IN, and the gate of the sixth PMOS transistor phvt2 is connected to the second input terminal INb. The fifth PMOS transistor phvt1 is used to turn on or off the fourth PMOS transistor phvt4. The sixth PMOS transistor phvt2 is used to turn on or off the third PMOS transistor phvt3.

[0114] Specifically, when the first logic signal input to the first input terminal IN is at a high level and the second logic signal input to the second input terminal INb is at a low level, the first output terminal OUT outputs a high level, the second output terminal OUTb outputs a low level, the fifth PMOS transistor phvt1 is turned off, the sixth PMOS transistor phvt2 is turned on, and the third PMOS transistor phvt3 is turned on, providing a high level for the first output terminal OUT. Conversely, when the first logic signal input to the first input terminal IN is at a low level, the fifth PMOS transistor phvt1 is turned on and the fourth PMOS transistor phvt4 is turned on, providing a high level for the second output terminal OUTb.

[0115] In a specific implementation, each PMOS transistor in the output sub-circuit 24 can be a high-voltage CMOS transistor.

[0116] In a specific implementation, an inverter may be provided between the first input terminal IN and the second input terminal INb. The inverter inverts the input first logic signal to generate a second logic signal, which is then input to the second input terminal INb. The output voltage of the first voltage output terminal VDDIO may serve as the operating voltage of the inverter.

[0117] As can be seen from the foregoing, the level shifter circuit 20 in the embodiment of the present invention, by providing the first voltage supply sub-circuit 22 and the second voltage supply sub-circuit 23, can ensure that each CMOS transistor in the level shifter circuit 20 is provided with an appropriate operating voltage, thereby avoiding overdriving issues. Furthermore, no additional bias voltage source is introduced, effectively saving circuit area.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A level conversion circuit, characterized in that: include: An input subcircuit, a first voltage providing subcircuit, a second voltage providing subcircuit, and an output subcircuit; wherein: The input sub-circuit has a first input terminal and a second input terminal, adapted to input a first logic signal and a second logic signal with opposite phases; The output sub-circuit has a first output terminal and a second output terminal, and is adapted to convert the levels of the first logic signal and the second logic signal to required level values and output them at the first output terminal and the second output terminal; The first voltage providing subcircuit is used to connect the input subcircuit and the output subcircuit, and provide an appropriate drain voltage for the CMOS transistor in the input subcircuit; The second voltage providing subcircuit is coupled to the first output terminal and the second output terminal, and is adapted to provide a bias voltage for the first voltage providing subcircuit based on the level values of the logic signals outputted by the first output terminal and the second output terminal; The high level values of the logic signals outputted by the first output terminal and the second output terminal are greater than the high level values of the first logic signal and the second logic signal; The second voltage providing sub-circuit includes: a first bias voltage providing module, coupled to the second output terminal, and adapted to output a first signal to be compared based on a level value of a logic signal outputted by the second output terminal; a second bias voltage providing module, coupled to the first output terminal, and adapted to output a second signal to be compared based on a level value of the logic signal outputted by the first output terminal; The comparison module has an input end connected to the first bias voltage providing module and the second bias voltage providing module, and is suitable for comparing the level values of the first signal to be compared and the second signal to be compared, selecting the larger one as the bias voltage, and outputting it to the first voltage providing sub-circuit.

2. The level conversion circuit according to claim 1, wherein: The first bias voltage providing module includes: two or more ninth NMOS transistors, one tenth NMOS transistor, and one eleventh NMOS transistor connected in series in sequence; The gate and drain of the ninth NMOS transistor are connected, the gate of the tenth NMOS transistor is coupled to the second power supply voltage output terminal; the gate of the eleventh NMOS transistor is coupled to the first input terminal, and the source of the eleventh NMOS transistor is grounded.

3. The level conversion circuit according to claim 2, wherein: The first bias voltage providing module further includes: a twelfth NMOS transistor connected in series between the ninth NMOS transistor and the tenth NMOS transistor.

4. The level conversion circuit according to claim 2, wherein: The number of the ninth NMOS tubes is 3.

5. The level conversion circuit according to any one of claims 2 to 4, wherein: The structure of the first bias voltage providing module is the same as that of the second bias voltage providing module.

6. The level conversion circuit according to claim 5, wherein: The comparison module includes: a first PMOS tube and a second PMOS tube; The drain of the first PMOS transistor is coupled to the source of the ninth NMOS transistor in the first bias voltage providing module; the drain of the second PMOS transistor is coupled to the source of the ninth NMOS transistor in the second bias voltage providing module; the gate of the first PMOS transistor is coupled to the drain of the second PMOS transistor, and the gate of the second PMOS transistor is coupled to the drain of the first PMOS transistor; and the sources of the first and second PMOS transistors are coupled to the first voltage providing sub-circuit.

7. The level conversion circuit according to claim 1, wherein: The input sub-circuit includes: a first NMOS transistor and a second NMOS transistor; wherein: The gate of the first NMOS transistor serves as the first input terminal, and the gate of the second NMOS transistor serves as the second input terminal; the drains of the first NMOS transistor and the second NMOS transistor are coupled to the first voltage providing sub-circuit; and the sources of the first NMOS transistor and the second NMOS transistor are grounded.

8. The level conversion circuit according to claim 7, wherein: The first voltage providing sub-circuit includes: a third NMOS transistor and a fourth NMOS transistor, wherein: The gates of the third NMOS transistor and the fourth NMOS transistor are coupled to the second voltage providing sub-circuit; the source of the third NMOS transistor is coupled to the first NMOS transistor, the source of the fourth NMOS transistor is coupled to the second NMOS transistor, and the drains of the third NMOS transistor and the fourth NMOS transistor are coupled to the output sub-circuit.

9. The level conversion circuit according to claim 8, wherein: The first voltage providing sub-circuit further includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor; wherein: The drains of the fifth and sixth NMOS transistors are coupled to the output sub-circuit; the source of the fifth NMOS transistor is coupled to the third NMOS transistor, and the source of the sixth NMOS transistor is coupled to the fourth NMOS transistor; the gates of the fifth and sixth NMOS transistors are coupled to the first power supply voltage output terminal; The drain of the seventh NMOS transistor is coupled to the third NMOS transistor, the drain of the eighth NMOS transistor is coupled to the fourth NMOS transistor, the source of the seventh NMOS transistor is coupled to the first NMOS transistor, the source of the eighth NMOS transistor is coupled to the second NMOS transistor, and the gates of the seventh and eighth NMOS transistors are coupled to the second power supply voltage output terminal; The voltage value outputted by the second power supply voltage output terminal is smaller than the voltage value outputted by the first power supply voltage output terminal.

10. The level conversion circuit according to claim 1, wherein: The output sub-circuit includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor; wherein: The sources of the third and fourth PMOS transistors are coupled to the first power supply voltage output terminal; the third PMOS transistor is connected in series with the fifth PMOS transistor, and the gate of the third PMOS transistor is coupled to the drain of the sixth PMOS transistor; the fourth PMOS transistor is connected in series with the sixth PMOS transistor, and the gate of the fourth PMOS transistor is coupled to the drain of the fifth PMOS transistor.

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