Signal processor and signal processing method

Abstract

A signal processor comprises a signal receiving circuit, a preprocessing circuit, a cycle acquisition circuit and a decoding circuit. The signal receiving circuit is used to receive an input signal. The preprocessing circuit is coupled to the signal receiving circuit and is used to generate a square wave signal according to the input signal. The cycle acquisition circuit is coupled to the preprocessing circuit and is used to capture multiple signal cycles of the square wave signal, wherein the multiple signal cycles include multiple signal cycle groups, and the multiple signal cycle groups respectively include at least two adjacent signal cycles in the multiple signal cycles. The decoding circuit is coupled to the cycle acquisition circuit and is used to perform decoding according to the time length of the multiple signal cycle groups and the number of voltage value changes to obtain a decoding result.

Description

Technical Field

[0001] The embodiments described in the present disclosure are related to a signal processor and a signal processing method, and more particularly to a signal processor and a signal processing method that are resistant to radio frequency interference. Background Art

[0002] The automotive electronic system has stricter requirements for safety and needs protection design against radio frequency interference (RFI). In order to simplify the circuit, based on the comparison circuit, after receiving the Differential Manchester Encoding (DME) defined by IEEE802.3cg, after RFI compensation and capturing the signal cycle, the decoding rule of the received signal is determined to see if it meets the DME definition to obtain the decoding result.

[0003] If only the comparison circuit is used to receive the signal, RFI will seriously affect the DME signal transmitted on the channel, causing the voltage change and period deformation of the DME signal. In addition, the comparison circuit will also cause signal distortion when passing through the comparison circuit. If the received signal is directly decoded without processing, the DME decoding mechanism will not converge. Summary of the invention

[0004] Some embodiments of the present disclosure are related to a signal processor, including a signal receiving circuit, a preprocessing circuit, a cycle acquisition circuit and a decoding circuit. The signal receiving circuit is used to receive an input signal. The preprocessing circuit is coupled to the signal receiving circuit to generate a square wave signal according to the input signal. The cycle acquisition circuit is coupled to the preprocessing circuit to capture multiple signal cycles of the square wave signal, wherein the multiple signal cycles include multiple signal cycle groups, and the multiple signal cycle groups respectively include at least two adjacent signal cycles in the multiple signal cycles. The decoding circuit is coupled to the cycle acquisition circuit to perform decoding according to the time length of the multiple signal cycle groups and the number of voltage value changes to obtain a decoding result.

[0005] Some embodiments of the present disclosure relate to a signal processing method, comprising the following steps: receiving an input signal through a signal receiving circuit; generating a square wave signal based on the input signal through a preprocessing circuit; capturing multiple signal cycles of the square wave signal through a period acquisition circuit, wherein the multiple signal cycles include multiple signal cycle groups, and the multiple signal cycle groups respectively include at least two adjacent signal cycles in the multiple signal cycles; and decoding through a decoding circuit based on the time length of the multiple signal cycle groups and the number of voltage value changes to obtain a decoding result.

[0006] In summary, the signal processor and signal processing method disclosed in the present invention provide a decoding circuit that is resistant to radio frequency interference without using an additional signal processing circuit, and resist circuit startup caused by radio frequency interference, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows:

[0008] Figure 1 is a schematic diagram of a signal processor according to some embodiments of the present disclosure;

[0009] Figure 2 is a flowchart of a signal processing method according to some embodiments of the present disclosure;

[0010] Figure 3 is a schematic diagram of a square wave signal depicted according to some embodiments of the present disclosure;

[0011] Figure 4 is a schematic diagram of an interfered square wave signal according to some embodiments of the present disclosure; and

[0012] Figure 5 is a schematic diagram of a filtered signal according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] As used herein, the term “coupled” may also refer to “electrically coupled”, and the term “connected” may also refer to “electrically connected.” “Coupled” and “connected” may also refer to two or more elements cooperating or interacting with each other.

[0014] refer to Figure 1 . Figure 1 is a schematic diagram of a signal processor 100 according to some embodiments of the present disclosure. For example, the signal processor 100 may be a vehicle-used electronic differential Manchester code detector and radio frequency interference canceller.

[0015] by Figure 1For example, the signal processor 100 includes a signal receiving circuit 110, a comparison circuit 120, a preprocessing circuit 130, a cycle acquisition circuit 140, a decoding circuit 150, a comparison circuit 160, and a signal detection circuit 170. In terms of connection relationship, the signal receiving circuit 110 is coupled to the comparison circuit 120 and the comparison circuit 160. The comparison circuit 120 is coupled to the preprocessing circuit 130. The comparison circuit 160 is coupled to the signal detection circuit 170. The preprocessing circuit 130 is coupled to the comparison circuit 120. The cycle acquisition circuit 140 is coupled to the preprocessing circuit 130. The decoding circuit 150 is coupled to the cycle acquisition circuit 140. The signal detection circuit 170 is coupled to the preprocessing circuit 130, the cycle acquisition circuit 140, and the decoding circuit 150.

[0016] In some embodiments, the comparison circuit 120 is a low threshold comparison circuit, and the comparison circuit 160 is a high threshold comparison circuit.

[0017] The above configuration of the signal processor 100 is for illustrative purposes only, and various configurations of the signal processor 100 are within the scope of the present disclosure. Figure 2 Explain together.

[0018] Figure 2 FIG. 2 is a flow chart of a signal processing method 200 according to some embodiments of the present disclosure. The signal processing method 200 may be applied to Figure 1 Please refer to the signal processor 100 below. Figure 1 as well as Figure 2 .

[0019] In step S210, an input signal is received by a signal receiving circuit. In some embodiments, the input signal is transmitted by a signal transmitter (not shown) and received by the signal receiving circuit 110. In some embodiments, after receiving the input signal, the signal receiving circuit 110 transmits the input signal to the comparison circuit 120. The comparison circuit 120 is used to compare the input signal voltage and transmit the compared input signal to the pre-processor 130.

[0020] In step S230, a square wave signal is generated according to the input signal by the pre-processing circuit. In some embodiments, the pre-processing circuit 130 generates a square wave signal according to the input signal after receiving the compared input signal.

[0021] Please also read Figure 3 . Figure 3 FIG. 4 is a schematic diagram of a square wave signal S2 according to some embodiments of the present disclosure. Figure 3As shown, the square wave signal S2 is generated according to the input signal S1. Specifically, in some embodiments, when the voltage value of the input signal S1 is greater than the high voltage threshold TH, the pre-processing circuit 130 sets the voltage value to the high voltage value H1. Conversely, when the voltage value of the input signal S1 is less than the low voltage threshold TL, the pre-processing circuit 130 sets the voltage value to the high voltage value L1.

[0022] In some embodiments, the input signal is processed using differential Manchester encoding, but the present invention is not limited to this encoding method.

[0023] However, it should be noted that due to the influence of radio frequency interference and the comparison circuit 120, the signal period processed by the pre-processing circuit 130 is different from the signal period of the input signal. Figure 4 . Figure 4 FIG. 4 is a schematic diagram of an interfered square wave signal S3 according to some embodiments of the present disclosure. Figure 4 As shown, after being affected by interference, the periods of 0 and 1 encrypted by differential Manchester coding in the square wave signal may become the same size or deformed. Therefore, decoding cannot be performed by simply observing the period of the existing interfered square wave signal S3.

[0024] In step S250, a plurality of signal cycles of the square wave signal are captured by a cycle acquisition circuit. In some embodiments, Figure 1 The period acquisition circuit 140 captures Figure 4 For example, Figure 4 The signal periods T1 to T7 in the signal acquisition circuit 140 are obtained by the period acquisition circuit 140. Since the period in the interfered square wave signal S3 has been deformed due to interference, the time lengths of the multiple signal periods T1 to T7 are not exactly the same. The multiple signal periods T1 to T7 are divided into multiple signal period groups, and the multiple signal period groups respectively include at least two adjacent signal periods in the multiple signal periods T1 to T7. In some embodiments, the signal period groups overlap with each other.

[0025] For example, when Figure 4 When the signal periods T1 to T3 are the first signal period group and the signal periods T3 to T4 are the second signal period group, the first signal period group and the second signal period group overlap with each other.

[0026] In step S270, a decoding circuit performs decoding according to the time length of the plurality of signal cycle groups and the number of times the voltage value changes to obtain a decoding result. Figure 1The decoding circuit 150 determines the decoding result according to the time length and the number of voltage value changes of each signal cycle group. In some embodiments, the decoding circuit 150 stores a comparison table. The decoding circuit 150 compares the time length and the number of voltage value changes with the comparison table to determine the decoding result.

[0027] In some embodiments, the comparison table is a decoding mechanism established by simulating and statistically analyzing periodic changes of different differential Manchester coding combinations.

[0028] In some embodiments, the time length of the signal period group is at least twice, or about twice, the differential Manchester code. For example, when the period time length of a differential Manchester code symbol is 80ns (nanoseconds), if it is affected by radio frequency interference, the rate of change of the period is relatively large. However, if the period of two or more consecutive differential Manchester code symbols is taken to observe the time length of 160ns, the rate of change after being affected by radio frequency interference is relatively small, so the differential Manchester code symbol can be more accurately solved.

[0029] For example, see Figure 4 . Assuming that the signal cycles T1 to T3 are included in about 160ns (i.e., a signal cycle group), the decoding circuit 150 can know based on the coding rules obtained by simulation statistics that these three signal cycles T1 to T3 are composed of 0 in a differential Manchester code and 1 in a differential Manchester code. Next, assuming that the signal cycles T3 to T4 are included in about 160ns (i.e., a signal cycle group), the decoding circuit 150 can know based on the coding rules obtained by simulation statistics that these two signal cycles T3 to T4 are composed of 0 in two differential Manchester codes. Therefore, the decoding circuit 150 can determine that the signal cycles T1 to T4 contain 1, 0, 0, which are the decoding results of differential Manchester codes.

[0030] It should be noted that the above implementation is based on the example of 160 ns as the detection boundary, but the implementation of the present invention is not limited thereto.

[0031] Please continue reading Figure 1 In some embodiments, the comparison circuit 160 is used to filter the input signal to generate a filtered signal. Figure 5 . Figure 5 is a schematic diagram of a filtered signal S4 according to some embodiments of the present disclosure. In some embodiments, the comparison circuit 160 is also used to determine whether the absolute value of the voltage value of the input signal is less than the voltage value threshold, and when the absolute value of the voltage value of the input signal is less than the voltage value threshold, the voltage value is filtered.

[0032] For example, in Figure 5In the embodiment, when the voltage value of the input signal S1 is not greater than the voltage value threshold TH or not less than the voltage value threshold TL, the voltage value is filtered to set the voltage value to 0. When the voltage value of the input signal S1 is greater than the voltage value threshold TH, the voltage value is set to H2, and when the voltage value of the input signal S1 is less than the voltage value threshold TL, the voltage value is set to L2.

[0033] In some embodiments, the signal detection circuit 170 determines whether the filtered signal S4 contains a valid signal. In some embodiments, when the voltage value of the filtered signal S4 is not 0, it is determined that the signal contains a valid signal. In some embodiments, when the voltage value of the filtered signal S4 is greater than a voltage value threshold, it is determined that the signal contains a valid signal.

[0034] In some embodiments, when it is determined that a valid signal is included, the signal detection circuit 170 controls the preprocessing circuit 130, the cycle acquisition circuit 140, and the decoding circuit 150 to start. On the contrary, when it is determined that no valid signal is included, the signal detection circuit 170 controls the preprocessing circuit 130, the cycle acquisition circuit 140, and the decoding circuit 150 to not start, and clears the preprocessing circuit 130, the cycle acquisition circuit 140, and the decoding circuit 150.

[0035] Specifically, even if the differential Manchester coded signal is affected by radio frequency interference, there will still be enough voltage to exceed the comparison threshold of the comparator 160. Therefore, as long as the output of the comparator 160 is observed to have a positive or negative change within the estimated time, it can be expected that there may be a differential Manchester coded signal next, and then the preprocessing circuit 130, the period acquisition circuit 140 and the decoding circuit 150 are turned on. On the other hand, when radio frequency interference or noise occurs, because most of the voltage is not enough to exceed the comparison threshold of the comparator 160, even when a DC bias appears on the channel of the input signal, so that the voltage of the input signal after radio frequency interference sometimes exceeds the comparison threshold of the comparator 160, the output of the comparator 160 will not have a positive or negative change. At this time, the preprocessing circuit 130, the period acquisition circuit 140 and the decoding circuit 150 will not try to decode the signal on the channel, so as to save unnecessary power consumption, and also avoid the phenomenon that when the frequency of the radio frequency interference signal is close to that of the differential Manchester coded signal, the decoding circuit mistakenly decodes the radio frequency interference signal as a differential Manchester coded signal. Embodiments of the present invention can detect automotive electronic differential Manchester encoding and eliminate radio frequency interference.

[0036] In summary, the present disclosure provides a signal processor and a signal processing method, which captures the multiples of the period of the code element of the differential Manchester coded signal for observation and decoding, so as to overcome the period variation of the differential Manchester coded signal caused by radio frequency interference and correctly interpret the coded content of the differential Manchester coded signal. In addition, the input signal is filtered by a comparator with a high comparison threshold, and the subsequent decoding circuit is controlled to perform a decoding operation according to the filtering result, so as to save unnecessary power consumption.

[0037] Various functional elements have been disclosed herein. For those skilled in the art, the functional elements can be implemented by circuits (whether dedicated circuits or general-purpose circuits operating under the control of one or more processors and coded instructions).

[0038] Although the present disclosure has been disclosed in the above-mentioned embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make various changes and improvements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0039] Description of reference numerals:

[0040] 100:Signal Processor

[0041] 110: Signal receiving circuit

[0042] 120: Comparison circuit

[0043] 130: Preprocessing circuit

[0044] 140: Periodic acquisition circuit

[0045] 150:Decoding circuit

[0046] 160: Comparison circuit

[0047] 170:Signal detection circuit

[0048] 200:Signal Processing Methods

[0049] S210, S230, S250, S270: Steps

[0050] S1: Input signal

[0051] S2: Square wave signal

[0052] S3: disturbed square wave signal

[0053] S4: Filtered signal

[0054] T1, T2, T3, T4, T5, T6, T7: signal cycle

[0055] TH,TL:Threshold

[0056] H1,H2,L1,L2: voltage value

Claims

1. A signal processor, comprising: A signal receiving circuit, used for receiving an input signal; A preprocessing circuit, coupled to the signal receiving circuit, for generating a square wave signal according to the input signal; A period acquisition circuit, coupled to the preprocessing circuit, for capturing a plurality of signal periods of the square wave signal, wherein the signal periods include a plurality of signal period groups, and the signal period groups respectively include at least two adjacent signal periods among the signal periods; as well as The decoding circuit is coupled to the cycle acquisition circuit and is used for decoding according to the time length of the signal cycle groups and the number of times the voltage value changes to obtain a decoding result.

2. The signal processor as claimed in claim 1, wherein the decoding circuit is further used to store a comparison table, and the decoding circuit is further used to compare the time length and the number of times the voltage value changes with the comparison table to determine the decoding result.

3. The signal processor of claim 1, further comprising: The comparison circuit is coupled between the signal receiving circuit and the pre-processing circuit, and is used for comparing the voltage value of the input signal.

4. The signal processor of claim 1, further comprising: A comparison circuit, coupled between the signal receiving circuit and the pre-processing circuit, for filtering the input signal to generate a filtered signal; When the absolute value of the voltage value of the input signal is less than a voltage value threshold, the voltage value is filtered.

5. The signal processor of claim 4, further comprising: A signal detection circuit, used for determining whether the filtered signal contains a valid signal; When the valid signal is included, the preprocessing circuit, the period acquisition circuit and the decoding circuit are started; When the valid signal is not included, the preprocessing circuit, the period acquisition circuit and the decoding circuit are not started. 6 . The signal processor of claim 5 , wherein when a voltage value of the filtered signal is not 0 or is greater than a voltage value threshold, it is determined that the valid signal is contained. The signal processor as claimed in claim 1 , wherein the signal cycle groups overlap with each other.

8. A signal processing method, comprising: receiving an input signal through a signal receiving circuit; Generate a square wave signal according to the input signal through a preprocessing circuit; Capturing multiple signal cycles of the square wave signal by a cycle acquisition circuit, wherein the signal cycles include multiple signal cycle groups, and the signal cycle groups respectively include at least two adjacent signal cycles among the signal cycles; and The decoding circuit performs decoding according to the time length of the signal cycle groups and the number of times the voltage value changes to obtain a decoding result.

9. The signal processing method according to claim 8, further comprising: filtering the input signal through a comparison circuit to generate a filtered signal; Determine whether the absolute value of the voltage value of the input signal is less than a voltage value threshold; as well as When the absolute value of the voltage value of the input signal is less than the voltage value threshold, the voltage value is filtered.

10. The signal processing method according to claim 9, further comprising: Determining whether the filtered signal contains a valid signal; When it is determined that the valid signal is contained, the preprocessing circuit, the period acquisition circuit and the decoding circuit are started; as well as When it is determined that the valid signal is not included, the preprocessing circuit, the period acquisition circuit and the decoding circuit are not started.

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