A packaging structure and a manufacturing method thereof

Abstract

The application provides a packaging structure and a manufacturing method thereof, and relates to the technical field of chip packaging. First, a first connecting layer is arranged based on a copper substrate, then a chip is attached based on the first connecting layer, and then the first connecting layer and the chip are sintered to realize interconnection, then a second connecting layer is arranged based on a bonding position on the surface of the chip, and then the second connecting layer and the chip are sintered, and finally, a bonding wire is used to connect the second connecting layer and a preset position of the copper substrate, wherein the manufacturing materials of the first connecting layer, the second connecting layer and the bonding wire all include copper materials. The packaging structure and the manufacturing method thereof have the advantages of smaller bonding pressure and stronger stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a packaging structure and a manufacturing method thereof. BACKGROUND

[0002] Power electronics technology is a technology that converts input DC or AC power into the required form of power and outputs it. Semiconductor chips are important components of power electronic conversion, but a single chip cannot perform any function, and the chip needs to be fixed and protected, circuit connected, and suitable working environment provided through packaging technology, such as good heat dissipation and insulation from the outside world.

[0003] In chip packaging, the interconnection of the chip mainly involves two parts. One is the connection of the chip and the substrate, and the other is the connection of the electrode of the chip and the lead frame. With the development of power electronics technology in the fields of new energy vehicles, high-speed rail, communication, etc., chips are developing towards higher power density, switching frequency, and smaller chip size, which puts higher requirements on packaging technology.

[0004] For the connection of the chip and the substrate, copper has the advantages of high electrical conductivity, thermal conductivity, and good mechanical properties, and compared with gold and silver, copper is abundant in resources and has a lower cost. Therefore, at present, according to the "size effect", micro-nano copper is considered to be the most promising chip interconnection technology through low-temperature sintering interconnection. For the connection between the chip and the lead frame, the overcurrent capacity of the bonding lead is crucial, and when aluminum wire bonding is used, the overcurrent capacity is relatively weak, which may cause the risk of melting of the bonding wire due to overcurrent. Copper wire, which has strong electrical conductivity and high hardness, is an ideal chip bonding material compared with aluminum wire.

[0005] However, at present, since the surface of the power chip is generally treated with an aluminum plating layer, aluminum wire is still commonly used for bonding. Since the wire hardness of aluminum wire is large, the bonding pressure required during bonding is larger, and direct copper wire bonding on the surface of the chip is easy to cause damage to the chip and result in chip scrap.

[0006] In summary, the prior art has the problem of large bonding pressure when using aluminum wire bonding. SUMMARY

[0007] The purpose of the present application is to provide a packaging structure and a manufacturing method thereof to solve the problem of large bonding pressure when using aluminum wire bonding in the prior art.

[0008] In order to achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0009] On the one hand, the packaging structure manufacturing method provided by the embodiments of the present application comprises:

[0010] setting a first connecting layer based on the copper substrate;

[0011] mounting a chip based on the first connecting layer;

[0012] sintering the first connecting layer and the chip to realize interconnection;

[0013] setting a second connecting layer based on the bonding position on the surface of the chip;

[0014] sintering the second connecting layer and the chip;

[0015] connecting the second connecting layer and a preset position of the copper substrate by a bonding wire respectively;

[0016] wherein the first connecting layer, the second connecting layer and the bonding wire are made of copper material.

[0017] Optionally, before the step of sintering the second connecting layer and the chip, the method further comprises:

[0018] setting a buffer layer based on the surface of the second connecting layer, so that the buffer layer covers the surface of the second connecting layer.

[0019] Optionally, the step of setting a second connecting layer based on the bonding position on the surface of the chip comprises:

[0020] setting a printing steel mesh with openings on the surface of the chip, wherein the openings expose the bonding position of the chip;

[0021] applying copper paste on the surface of the chip along the printing steel mesh;

[0022] removing the printing steel mesh to form a second connecting layer at the bonding position on the surface of the chip.

[0023] Optionally, the step of setting a second connecting layer based on the bonding position on the surface of the chip comprises:

[0024] attaching a copper film based on the bonding position on the surface of the chip to form a second connecting layer.

[0025] Optionally, the steps of sintering the first connecting layer and the chip and sintering the second connecting layer and the chip comprise:

[0026] sintering at 200-300℃ in an anti-oxidation environment with a sintering pressure of 0-30MPa for 1-30min; or

[0027] sintering at 200-300℃ in an anti-oxidation environment for 1-90min.

[0028] In another aspect, the application provides a packaging structure, comprising:

[0029] a copper substrate;

[0030] a first connecting layer connected to the copper substrate;

[0031] a chip connected to the first connecting layer;

[0032] a second connecting layer connected to a bonding position on the surface of the chip; and

[0033] a bonding wire respectively connecting the second connecting layer and a preset position of the copper substrate;

[0034] wherein the first connecting layer, the second connecting layer and the bonding wire are made of copper material.

[0035] Optionally, the area of the first connecting layer is larger than that of the chip.

[0036] Optionally, the thickness of the second connecting layer is 20-1000 microns.

[0037] Optionally, the first connecting layer and the second connecting layer are made of the same material.

[0038] Optionally, the material for making the first connecting layer and the second connecting layer comprises micron copper particle paste, nanometer copper particle paste, micro-nano mixed copper particle paste, silver-coated copper micro-nano particle paste, silver / copper mixed paste, sintered copper film, copper-based adhesive glue / paste.

[0039] Compared with the prior art, the application has the following beneficial effects:

[0040] The application provides a packaging structure and a manufacturing method thereof. First, a first connecting layer is arranged based on a copper substrate, then a chip is attached based on the first connecting layer, and then the first connecting layer and the chip are sintered to realize interconnection. Then, a second connecting layer is arranged based on a bonding position on the surface of the chip, and the second connecting layer and the chip are sintered. Finally, a bonding wire is used to respectively connect the second connecting layer and a preset position of the copper substrate, wherein the first connecting layer, the second connecting layer and the bonding wire are made of copper material. On the one hand, since the first connecting layer, the second connecting layer and the bonding wire all include copper material, compared with the bonding method of aluminum wire in the prior art, the overcurrent capacity of the bonding lead is improved, the reliable connection between the chip and the bonding wire is realized, and the copper material can withstand a large bonding pressure. On the other hand, since the first connecting layer, the second connecting layer and the bonding wire are made of copper material, their thermal expansion coefficients are the same, so the packaging structure has higher stability when working.

[0041] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart illustrating the packaging structure fabrication method provided in an embodiment of this application.

[0044] Figure 2 This is a cross-sectional schematic diagram of a copper substrate provided in an embodiment of this application.

[0045] Figure 3 This is a cross-sectional schematic diagram corresponding to S102 provided in the embodiments of this application.

[0046] Figure 4 This is a cross-sectional schematic diagram corresponding to S104 provided in the embodiments of this application.

[0047] Figure 5 This is a cross-sectional schematic diagram corresponding to S108 provided in the embodiments of this application.

[0048] Figure 6 This is a cross-sectional schematic diagram corresponding to S112 provided in the embodiments of this application.

[0049] Figure 7 This is a schematic diagram of the packaging structure provided in an embodiment of this application.

[0050] In the diagram: 100 - package structure; 110 - copper substrate; 120 - first interconnect layer; 130 - chip; 140 - second interconnect layer; 150 - bonding wire. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0053] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0054] It should be noted that in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0055] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0056] As described in the background section, aluminum wire bonding is generally used to bond chips to substrates, which results in high bonding pressure and can easily damage the chips.

[0057] In view of this, this application provides a packaging structure fabrication method that utilizes copper wire bonding, which can withstand greater bonding pressure and protect the chip from damage.

[0058] The following provides an example illustrating the method for fabricating the packaging structure provided in this application:

[0059] As one implementation method, please refer to Figures 1 to 7 The method includes:

[0060] S102, a first interconnect layer is provided based on a copper substrate.

[0061] S104, a chip is mounted on the first interconnect layer.

[0062] S106, the first interconnect layer and the chip are sintered to achieve interconnection.

[0063] S108, a second connection layer is set based on the bonding positions on the chip surface.

[0064] S110, the second interconnect layer is sintered with the chip.

[0065] S112, the second connection layer and the copper substrate are connected to preset positions using bonding wires; wherein, the materials used to manufacture the first connection layer, the second connection layer and the bonding wires all include copper.

[0066] The copper substrate 110 provided in this application can be a pure copper substrate, a direct-bonding ceramic substrate (DBC), including alumina DBC, aluminum nitride DBC, silicon nitride active metal brazing (AMB), and copper leadframe materials, etc., which are not limited here.

[0067] The material used to make the first connecting layer 120 can be micron copper particle paste, nano copper particle paste, micro-nano mixed copper particle paste, silver-coated copper micro-nano particle paste, silver / copper mixed paste, as well as sintered copper film, copper-based adhesive / paste, and copper pre-placed connecting layer, etc.

[0068] Based on this, step S102 may include:

[0069] S1021, the first interconnect layer is disposed on the copper substrate by printing, patching or pre-setting.

[0070] S1022 is dried in a drying oven.

[0071] When the material of the first connection layer 120 is copper paste, the first connection layer 120 is formed on the copper substrate 110 by printing. When the first connection layer 120 is copper film, the first connection layer 120 is formed by surface mounting or by pre-setting.

[0072] Optionally, during drying, the drying temperature of the drying oven is 90℃~150℃, and the drying time is 5min~30min.

[0073] It should be noted that the first connection layer 120 is used to connect the chip 130 and the copper substrate 110 and achieve ohmic contact. In order to achieve a tighter connection effect, the thickness of the first connection layer 120 can be 10μm to 500μm.

[0074] It should also be noted that, in order to make the mounting of chip 130 more convenient and accurate, the area of ​​the first interconnect layer 120 is generally larger than the area of ​​chip 130.

[0075] The chip 130 provided in this application can be a power chip. For example, the chip 130 can be an uncontrollable device chip 130 made from silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), zinc selenide (ZnSe) as raw materials, such as power rectifier diodes, Schottky diodes (SBD), fast recovery diodes (FRD), and semi-controlled device chips such as thyristors (SCR), bidirectional thyristors (TRIAC), as well as fully controlled device chips such as insulated gate dual transistors (IGBT), power field-effect transistors (MOSFET), gate turn-off thyristors (GTO), power transistors (GTR), bipolar junction transistors (BJT), etc.

[0076] The purpose of sintering the first interconnect layer 120 and the chip 130 is to interconnect them and form an ohmic contact. When sintering the first interconnect layer 120 and the chip 130, pressure sintering and pressureless sintering can be used. When pressure sintering is used, it is sintered in an anti-oxidation environment of 200℃~300℃ and sintering pressure of 0MPa~30MPa for 1min~30min. When pressureless sintering is used, it is sintered in an anti-oxidation environment of 200℃~300℃ for 1min~90min.

[0077] The anti-oxidation environment described in this application includes environments such as the atmosphere, Ar, N2, H2, mixed gases (H2 / Ar, H2 / N2), and formic acid, and is not limited to these.

[0078] For ease of manufacturing, the material of the second interconnect layer 140 is the same as that of the first interconnect layer 120. However, unlike the first interconnect layer 120, the second interconnect layer 140 needs to be disposed at a specific position on the surface of the chip 130.

[0079] S108 includes:

[0080] S1081, the second interconnect layer is printed, mounted, or pre-placed at the bonding position on the chip surface.

[0081] S1082, dried in a drying oven.

[0082] The bonding sites on the surface of chip 130 refer to the electrodes of chip 130. Similar to the setting of the first connection layer 120, the drying temperature of the drying oven is 90℃~150℃ and the drying time is 5min~30min.

[0083] Understandably, in addition to establishing the connection relationship and enabling ohmic contact between the chip and the bonding wire, the second connection layer 140 also serves as an electrode of the chip 130. In order to ensure a stable connection with the bonding wire 150, the thickness of the second connection layer 140 is greater than the thickness of the first connection layer 120, and its thickness can be 20μm to 1000μm.

[0084] Furthermore, since the second interconnect layer 140 needs to be set at a specific location on the chip 130, the process differs from that used to fabricate the first interconnect layer 120. Specifically, when copper paste is used to fabricate the second interconnect layer 140, step S108 includes:

[0085] S1083, a printed stencil with openings is provided on the chip surface, wherein the openings expose the bonding positions of the chip.

[0086] S1084, copper paste is applied to the chip surface along the printed stencil.

[0087] S1085, Remove the printed stencil to form a second interconnect layer 140 at the bonding site on the chip surface.

[0088] When the second interconnect layer 140 is fabricated using a copper film, S108 includes:

[0089] S1086, a copper film is attached based on the bonding position on the chip surface to form a second interconnect layer 140.

[0090] In addition, to protect the second connection layer, prior to S110, the method further includes:

[0091] S1087, A buffer layer is provided on the surface of the second connecting layer so that the buffer layer covers the surface of the second connecting layer.

[0092] Alternatively, the cushioning layer can be made of Teflon tape.

[0093] It should be noted that the process of sintering the second connection layer 140 and the chip 130 is the same as the process of sintering the first connection layer 120 and the chip 130 described above. Both can be pressure sintering or pressureless sintering processes, which will not be elaborated here.

[0094] As one implementation, when connecting the second interconnecting layer 140 and the copper substrate 110 to predetermined positions using bonding wires 150, the bonding wires 150 are interconnected via ultrasonic welding. Throughout the bonding process, a mixture of H2, H2 / Ar, or H2 / N2 gas is continuously used for protection to prevent oxidation of the copper wires. The bonding wires 150 can be pure copper wire, pure copper strip / foil, copper electrodes, or silver-clad copper wire, etc.

[0095] In the above embodiments, the packaging structure 100 can be fabricated in at least two ways:

[0096] The first method involves using a high-precision screen printing table equipped with a printing stencil on a copper-clad ceramic substrate (DBC). A squeegee is used to manually print micro-nano copper paste onto the DBC substrate, and the paste is then dried in a drying oven at a specific temperature to allow some of the organic carriers in the micro-nano copper paste to evaporate.

[0097] Then, after aligning the chip 130 with the dried micro-nano copper paste, the chip 130 is accurately attached to the micro-nano copper paste using a certain mounting pressure. Low-temperature pressure sintering is then performed under specific sintering temperature, pressure, and time. During the sintering process, an N2 atmosphere is maintained to prevent oxidation.

[0098] Next, on the surface of chip 130 after sintering and interconnecting chip 130 with copper substrate 110, a printing stencil with openings corresponding to the bonding electrode positions of chip 130 is used. A squeegee is then used to print the second interconnect layer 140 micro-nano copper paste onto the surface of chip 130. Before sintering, a layer of Teflon tape is placed over the second interconnect layer 140 micro-nano copper paste printed on the surface of chip 130 as a buffer layer. Then, low-temperature pressure sintering is performed under specific sintering temperature, pressure, and time. Throughout the sintering process, an N2 atmosphere is maintained to prevent oxidation. Finally, ultrasonic welding is used to bond chip 130 to the substrate using bonding wires 150, with the bonding wire solder joints on chip 130 aligned with the second interconnect layer 140 micro-nano copper paste (bonding copper foil).

[0099] The second method involves setting a micro / nano particle copper film as the first connecting layer 120 on a copper-clad ceramic substrate (DBC). The prepared micro / nano particle copper film is then mounted onto the DCB substrate. Next, after aligning the chip 130 with the micro / nano particle copper film, a certain mounting pressure is used to accurately mount the chip 130 onto the micro / nano particle copper film. Low-temperature pressure sintering is then performed under specific sintering temperatures, pressures, and times. Throughout the sintering process, an N2 atmosphere is maintained to prevent oxidation.

[0100] Next, on the surface of chip 130 after sintering and interconnecting chip 130 with the DBC substrate, a second interconnect layer 140 of appropriate size, consisting of micro / nano-particle copper film, is attached to the electrode positions of chip 130. Of course, before sintering, a layer of Teflon tape is placed on the second interconnect layer 140 micro / nano-particle copper film attached to the surface of chip 130 as a buffer layer. Then, low-temperature pressure sintering is performed under specific sintering temperature, pressure, and time. Throughout the sintering process, an N2 atmosphere is maintained to prevent oxidation.

[0101] Finally, ultrasonic welding is used to bond the chip 130 to the substrate with copper wire bonding 150, wherein the copper wire bonding joints at the chip 130 end are aligned with the second connection layer 140 layer of micro-nano particle copper film (bonding copper foil).

[0102] The packaging structure fabrication method provided in this application improves the current-carrying capacity of the bonding wires, achieving a reliable connection between the chip and the bonding wires, and the copper material can withstand greater bonding pressure. Furthermore, since the first interconnect layer, the second interconnect layer, and the bonding wires all contain copper, which has the same coefficient of thermal expansion, this packaging structure exhibits higher stability during operation.

[0103] Based on the above implementation, this application also provides an encapsulation structure, which is fabricated using the above method. Please continue reading. Figure 6 and Figure 7 The packaging structure 100 includes: a copper substrate 110; a first connection layer 120 connected to the copper substrate 110; a chip 130 connected to the first connection layer 120; a second connection layer 140 connected to a bonding position on the surface of the chip 130; and bonding wires 150 respectively connecting the second connection layer 140 to a predetermined position on the copper substrate 110; wherein the first connection layer 120, the second connection layer 140 and the bonding wires 150 are all made of copper.

[0104] Optionally, the area of ​​the first connection layer 120 is larger than the area of ​​the chip 130.

[0105] Optionally, the thickness of the second connecting layer 140 is 10μm to 500μm, or 20μm to 1000μm.

[0106] Optionally, the first connecting layer 120 and the second connecting layer 140 are made of the same material.

[0107] Furthermore, the materials used to fabricate the first connecting layer 120 and the second connecting layer 140 include micron copper particle paste, nano copper particle paste, micro / nano mixed copper particle paste, silver-coated copper micro / nano particle paste, silver / copper mixed paste, sintered copper film, and copper-based adhesive / paste.

[0108] In summary, this application provides a packaging structure and its fabrication method. First, a first interconnect layer is formed on a copper substrate. Then, a chip is mounted on the first interconnect layer. Next, the first interconnect layer and the chip are sintered to achieve interconnection. Then, a second interconnect layer is formed based on the bonding positions on the chip surface, and the second interconnect layer and the chip are sintered. Finally, bonding wires are used to connect the second interconnect layer to predetermined positions on the copper substrate. The first interconnect layer, the second interconnect layer, and the bonding wires are all made of copper. On one hand, because the first interconnect layer, the second interconnect layer, and the bonding wires provided in this application all include copper, compared to the aluminum wire bonding method used in the prior art, the current-carrying capacity of the bonding wires is improved, achieving a reliable connection between the chip and the bonding wires. Furthermore, copper can withstand greater bonding pressure. On the other hand, because the first interconnect layer, the second interconnect layer, and the bonding wires are all made of copper, they have the same coefficient of thermal expansion, thus this packaging structure has higher stability during operation.

[0109] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0110] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for fabricating a packaging structure, characterized in that, The packaging structure manufacturing method comprises: a first connecting layer is arranged based on the copper substrate; a chip is attached based on the first connecting layer; sintering is performed on the first connecting layer and the chip to realize interconnection; a second connecting layer is arranged based on the bonding position on the surface of the chip; sintering is performed on the second connecting layer and the chip; bonding wires are used to connect the second connecting layer and the preset position of the copper substrate respectively; the first connecting layer, the second connecting layer and the bonding wires are all made of copper material; before the step of sintering the second connecting layer and the chip, the method further comprises: a buffer layer is arranged based on the surface of the second connecting layer, so that the buffer layer is arranged on the surface of the second connecting layer, and the buffer layer is made of Teflon tape; when the second connecting layer is copper paste, the buffer layer is arranged on the surface of the second connecting layer; the steps of sintering the first connecting layer and the chip and sintering the second connecting layer and the chip comprise: sintering in an anti-oxidation environment at 200-300℃ and a sintering pressure of 0-30MPa for 1-30min; or sintering in an anti-oxidation environment at 200-300℃ for 1-90min; when the bonding wires are used to connect the second connecting layer and the preset position of the copper substrate respectively, H2, H2 / Ar or H2 / N2 mixed gas is continuously used for protection.

2. The method of claim 1, wherein the step of arranging the second connecting layer based on the bonding position on the surface of the chip comprises: a printing steel mesh with openings is arranged on the surface of the chip, wherein the openings expose the bonding position of the chip; copper paste is coated on the surface of the chip along the printing steel mesh; the printing steel mesh is removed to form the second connecting layer on the bonding position on the surface of the chip.

3. The method of claim 1, wherein the step of arranging the second connecting layer based on the bonding position on the surface of the chip comprises: a copper film is attached based on the bonding position on the surface of the chip to form the second connecting layer.

4. A package structure, characterized by, The packaging structure is manufactured by the method according to any one of claims 1-3, and the packaging structure comprises: a copper substrate; a first connecting layer connected to the copper substrate; a chip connected to the first connecting layer; a second connecting layer connected to the bonding position on the surface of the chip; and bonding wires connected to the second connecting layer and the preset position of the copper substrate respectively; the first connecting layer, the second connecting layer and the bonding wires are all made of copper material.

5. The package structure of claim 4, wherein, The area of the first connecting layer is greater than the area of the chip.

6. The package structure of claim 4, wherein, The thickness of the second connecting layer is 20-1000μm.

7. The package structure of claim 4, wherein, The materials for manufacturing the first connecting layer and the second connecting layer are the same.

8. The package structure of claim 4, wherein, The materials for manufacturing the first connecting layer and the second connecting layer comprise micron copper particle paste, nanometer copper particle paste, micro-nano mixed copper particle paste, silver-coated copper micro-nano particle paste, silver / copper mixed paste, sintered copper film and copper-based adhesive glue / paste.

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