Semiconductor device and manufacturing method thereof, packaging device and electronic device

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, a packaging device and an electronic device. The semiconductor device includes an interposer and a plurality of chips, wherein the second surface of the chip is coupled to the first surface of the interposer through a connection structure; wherein the interposer is used to realize the interconnection of the plurality of chips; the connection structure includes a first dielectric layer formed on the first surface of the interposer and a first conductive pin formed on the first surface of the interposer and exposed from the first dielectric layer, and also includes a second dielectric layer formed on the second surface of the chip and a second conductive pin formed on the second surface of the chip and exposed from the second dielectric layer; and between the first dielectric layer and the second dielectric layer and between the first conductive pin and the second conductive pin, the respective van der Waals force-dependent bonding is realized through an annealing process after the first dielectric layer and the second dielectric layer are pre-bonded. The present disclosure realizes the connection between the chip and the interposer through a new connection structure, and the interconnection density per unit area of ​​the chip is increased.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof, a packaging device, and an electronic apparatus. Background Art

[0002] CoWoS (Chip-on-Wafer-on-Substrate) packaging, i.e. chip-on-wafer-on-substrate packaging, is a packaging method that first connects the chip to the wafer and then connects the wafer connected with the chip to the substrate. This packaging method can package multiple chips together. In this case, the wafer can be used as an interposer to interconnect multiple chips through a built-in redistribution layer (RDL), ultimately achieving the effect of enhancing the interconnectivity between chips. However, since the wafer and the chip are connected through micro-bumps (uBump), the micro-bump is a structure formed by welding (Solder) a pair of copper balls (Cu pillars) attached to the wafer and the chip respectively, and the size is large (above 40um), so the number of micro-bumps set per unit area of ​​the chip is limited, which makes the packaging device using the interposer unable to adapt to the trend of high frequency and high density in the field of electronic design. Summary of the invention

[0003] In view of this, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof, a packaging device and an electronic device, wherein the connection method of the chip and the wafer in the packaging device is different from that in the prior art.

[0004] According to a first aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0005] Intermediary film;

[0006] a plurality of chips, wherein the second surface of the chips is coupled to the first surface of the interposer via a connection structure;

[0007] Wherein, the interposer is used to realize the interconnection of multiple chips;

[0008] The connection structure includes a first dielectric layer formed on a first surface of the interposer and a first conductive pin formed on the first surface of the interposer and exposed from the first dielectric layer, and also includes a second dielectric layer formed on a second surface of the chip and a second conductive pin formed on the second surface of the chip and exposed from the second dielectric layer;

[0009] Furthermore, the first dielectric layer and the second dielectric layer, as well as the first conductive pin and the second conductive pin, are bonded with each other by relying on van der Waals force through an annealing process after the first dielectric layer and the second dielectric layer are pre-bonded.

[0010] Optionally, a longitudinal first signal via is provided in the interposer, and the first signal via includes a first end and a second end;

[0011] The interposer also has a first rewiring layer built in, and the first rewiring layer is used to realize the interconnection of multiple chips;

[0012] The first end is located in the interposer and connected to the first redistribution layer;

[0013] The second end is located at a first position on the first surface of the interposer, and the formation position of the first conductive pin on the first surface of the interposer includes the first position.

[0014] Optionally, a longitudinal second signal via is provided in the interposer, and the second signal via includes a third end and a fourth end;

[0015] A connecting piece is disposed on a side of the intermediate sheet opposite to the first surface of the intermediate sheet, and the third end is used to connect the connecting piece;

[0016] The fourth end is located at a second position on the first surface of the interposer, and the formation position of the first conductive pin on the first surface of the interposer includes the second position.

[0017] Optionally, the third end is located on a surface of the interposer opposite to the first surface of the interposer and is directly connected to the connecting member.

[0018] Optionally, a third longitudinal signal via is provided in the interposer, the third signal via comprises a fifth end and a sixth end, the fifth end is located on a side of the interposer opposite to the first surface of the interposer and connected to the connector, and the sixth end is located in the interposer;

[0019] The interposer also has a built-in second redistribution layer;

[0020] The third end is located in the interposer and is connected to the sixth end through the second redistribution layer.

[0021] Optionally, the first dielectric layer and the second dielectric layer are both made of silicon dioxide.

[0022] Optionally, the first conductive pin and the second conductive pin are both made of copper.

[0023] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, wherein the semiconductor device comprises an interposer and a plurality of chips, wherein the interposer is used to interconnect the plurality of chips, and the manufacturing method comprises:

[0024] forming a first dielectric layer and a first conductive pin on a first surface of the interposer, wherein the first conductive pin is recessed relative to the first dielectric layer;

[0025] forming a second dielectric layer and a second conductive pin on a second surface of the chip, wherein the second conductive pin is recessed relative to the second dielectric layer;

[0026] The first dielectric layer and the second dielectric layer are pre-bonded, and the first dielectric layer and the second dielectric layer, as well as the first conductive pin and the second conductive pin are bonded by annealing to achieve respective Van der Waals force bonding.

[0027] Optionally, a longitudinal target signal via is provided in the interposer, and a target end of the target signal via is used to connect a connector, and the connector is used to connect the interposer and the substrate;

[0028] The manufacturing method further includes: after the first dielectric layer and the second dielectric layer are connected and the first conductive pin and the second conductive pin are connected, thinning the intermediate sheet from a side of the intermediate sheet opposite to the first surface of the intermediate sheet to expose the target end; and connecting the connector to the exposed target end.

[0029] According to a third aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0030] An interposer, wherein a first surface of the interposer is provided with a first conductive pin;

[0031] A chip, wherein a second conductive pin is disposed on a second surface of the chip, the second surface of the chip is coupled to the first surface of the interposer and the second conductive pin is connected to the first conductive pin;

[0032] A connecting member, disposed on a surface of the intermediate sheet opposite to the first surface of the intermediate sheet;

[0033] The interposer is built with a second longitudinal signal via, a second redistribution layer and a third longitudinal signal via;

[0034] The second signal via includes a third end and a fourth end, and the fourth end is located on the first surface of the interposer to connect to the first conductive pin;

[0035] The third signal via comprises a fifth end and a sixth end, wherein the fifth end is located on a side of the interposer opposite to the first surface of the interposer to connect to the connector;

[0036] The third terminal and the sixth terminal are respectively located in the interposer and connected through the second redistribution layer.

[0037] According to a fourth aspect of the present disclosure, there is provided a packaging device, comprising:

[0038] a substrate having a third surface;

[0039] Any semiconductor device described in the first aspect, or the semiconductor device described in the third aspect;

[0040] The semiconductor device includes an interposer whose surface opposite to the first surface of the interposer is coupled to the third surface of the substrate.

[0041] According to a fifth aspect of the present disclosure, there is provided an electronic device, comprising: an external circuit board and any one packaging device described in the fourth aspect, wherein the packaging device is arranged on the external circuit board.

[0042] In an embodiment of the present disclosure, a semiconductor device includes an interposer and a plurality of chips, wherein the second surface of the chip is coupled to the first surface of the interposer via a connection structure, and the interposer is used to realize the interconnection of the plurality of chips, wherein the connection structure includes a first dielectric layer formed on the first surface of the interposer, and a first conductive pin formed on the first surface of the interposer and exposed from the first dielectric layer, and the connection structure also includes a second dielectric layer formed on the second surface of the chip, and a second conductive pin formed on the second surface of the chip and exposed from the second dielectric layer, and the first dielectric layer and the second dielectric layer and the first conductive pin and the second conductive pin are bonded by annealing process after the first dielectric layer and the second dielectric layer are pre-bonded to realize their respective van der Waals force, so that the size of the first conductive pin and the second conductive pin can be much smaller than the existing micro-convex balls, thereby increasing the interconnection density per unit area of ​​the chip, and the packaged device can meet the requirements of high frequency and high density. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0044] Figure 1 It is a schematic diagram of the structure of a packaging device using an embedded multi-chip interconnection bridge technology in the prior art;

[0045] Figure 2 It is a schematic diagram of the structure of a packaged device used in a high-bandwidth memory processor in the prior art;

[0046] Figure 3 It is a schematic diagram of the structure of a packaging device using a chip-on-wafer-on-substrate packaging technology in the prior art;

[0047] Figure 4 is a schematic structural diagram of a semiconductor device provided by the first embodiment of the present disclosure;

[0048] Figure 5 is a schematic structural diagram of another semiconductor device provided by the first embodiment of the present disclosure;

[0049] Figure 6 is a schematic flow chart of a manufacturing method provided in a second embodiment of the present disclosure;

[0050] Figure 7A-7B It is a process schematic diagram of each step included in the manufacturing method provided by the manufacturing embodiment of the present disclosure;

[0051] Figure 8 is a schematic structural diagram of a semiconductor device provided by the third embodiment of the present disclosure;

[0052] Fig. 9 is a schematic structural diagram of a packaging device provided by a fourth embodiment of the present disclosure;

[0053] Fig.10 It is a structural block diagram of an electronic device provided by the fifth embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0055] Semiconductor device according to the first embodiment of the present disclosure

[0056] The design of embedding multiple chips in a packaged device can be roughly divided into three types: 2D packaging, 2.5D packaging and 3D packaging. Among them, 2.5D packaging is an improvement on traditional 2D packaging, which can achieve more sophisticated circuit and space utilization. At the same time, unlike the 3D packaging method of "stacked to the top" in one dimension, 2.5D packaging is more like a "flat version" of Lego blocks, allowing multiple chips to be fixed horizontally on a plane of a fixed size. The multiple chips fixed horizontally can be the same chip or chips of the same or different sizes with different functions manufactured by different processes.

[0057] In 2.5D packaging, in order to enhance the interconnectivity between chips, an "interposer" is introduced. The interposer interconnects multiple chips located on the interposer through a built-in redistribution layer. The interposer can be made of silicon and organic materials, and has a high fine-pitch signal conductor formation capability and silicon through-hole formation capability, thus allowing a more ideal redistribution layer and signal via to be set inside it. The redistribution layer is a metal or polymer dielectric material layer, and the signal conductor made of metal or polymer dielectric material enables the electrical signal in the dielectric sheet to be conducted horizontally. The signal via is a conductive line formed by drilling a hole on the interposer with a laser and then electroplating copper to fill the hole. It runs through the entire interposer to form the shortest conductive path from one side of the interposer to the other side, and its function is to enable the electrical signal in the dielectric sheet to be conducted vertically. The combination of the redistribution layer and the signal via not only enables the interconnection of multiple chips on the interposer, but also enables the chips and the package substrate on both sides of the interposer to be interconnected.

[0058] Since the birth of 2.5D packaging, typical existing packaging technologies include Embedded Multi-Die Interconnect Bridge (EMIB), packaging technology widely used for high-bandwidth memory (HBM) processor integration, and Chip-on-Wafer-on-Substrate (CoWoS).

[0059] Figure 1 The conventional packaged device 100 using the embedded multi-chip interconnection bridge technology is shown. Figure 1 The packaged device 100 includes a chip 101, a chip 102, an intermediate chip 103 and a package substrate 104, wherein the intermediate chip 103 is completely embedded in the package substrate 104; the intermediate chip 103 has a built-in redistribution layer 105, and the intermediate chip 103 and the package substrate 104 have longitudinal signal vias 106, and micro-convex balls 107 are arranged between the chip 101 and the chip 102 and the package substrate 104, so that the micro-convex balls 107→signal vias 106→redistribution layer 105→signal vias 106→micro-convex balls 107 constitute a communication line between the chip 101 and the chip 102 (two such communication lines are shown in the figure); solder balls 108 are also arranged between the chip 101 and the chip 102 and the package substrate 104, so that the chip 101 and the chip 102 are electrically connected to the package substrate 104.

[0060] In this packaging technology, the packaging substrate 104, as the core structure of the chip packaging, plays the role of protecting, fixing, supporting the chip and enhancing the heat dissipation performance of the chip, and can ensure that the chip is not physically damaged; in addition, the packaging substrate 104 is usually composed of multiple layers, each layer is composed of conductive materials and / or insulating materials, so as to be used as a power layer, signal layer, ground layer or insulating layer. In view of the many functions undertaken by the packaging substrate 104, the design of the packaging substrate 104 is preferably not interfered by additional factors, so it is expected that through technical improvements, the packaging substrate 104 does not need to be embedded in the intermediate chip 103.

[0061] Figure 2 FIG. 2 is a schematic diagram of a packaged device 200 widely used in high bandwidth memory processors. Figure 2 The packaged device 200 includes a chip 201, a chip 202, an intermediate sheet 203 and a package substrate 204, wherein the intermediate sheet 203 is partially embedded in the package substrate 204; the intermediate sheet 203 has a built-in redistribution layer 205 and a longitudinal signal via 206, and micro-convex balls 207 are arranged between the chip 201 and the chip 202 and the intermediate sheet 203, so that the micro-convex balls 207→signal via 206→redistribution layer 205→signal via 206→micro-convex balls 207 constitute a communication line between the chip 201 and the chip 202 (two such communication lines are shown in the figure); solder balls 208 are also arranged between the chip 201 and the chip 202 and the package substrate 204, so that the chip 201 and the chip 202 are electrically connected to the package substrate 204.

[0062] In this packaging technology, the packaging substrate 204 bears the Figure 1 The package substrate 104 has many functions similar to those of the package substrate 104 . Although the package substrate 204 does not need to completely accommodate the interposer 203 , it still accommodates a portion of the interposer 203 . Therefore, the design of the package substrate 104 still needs to additionally consider the position of the interposer 203 .

[0063] Figure 3 FIG. 3 is a schematic diagram of a packaged device 300 using a chip-on-wafer-on-substrate packaging technology. Figure 3The packaged device 300 includes a chip 301, a chip 302, an interposer 303 and a package substrate 304, wherein the interposer 303 is located outside the package substrate 304; the interposer 303 has a built-in redistribution layer 305 and a longitudinal first signal via 306, and micro-convex balls 307 are arranged between the chip 301 and the chip 302 and the interposer 303, so that the micro-convex balls 307 → the first signal via 306 → the redistribution layer 305 → the first signal via 306 → the micro-convex balls 307 constitute a communication line between the chip 301 and the chip 302 (two such communication lines are shown in the figure), In order to strengthen the connection between the intermediate sheet 303 and the chip 301 and the chip 302, an organic underfill 310 is set; the intermediate sheet 303 also has a built-in longitudinal second signal via 309, and a solder ball 308 is set between the intermediate sheet 303 and the packaging substrate, so that the micro-convex ball 307→the second signal via 309→the solder ball 308 forms a communication line between the chip 301 / chip 302 and the packaging substrate 304 (four such communication lines are shown in the figure), so that the chip 301 and the chip 302 are each electrically connected to the packaging substrate 304.

[0064] This packaging technology is relatively Figure 1 and Figure 2 The packaging technology used in the packaged device shown has a significant improvement in the position of the intermediate sheet, that is, the intermediate sheet 303 in this packaging technology does not need to be embedded in the packaging substrate 304 at all. However, this packaging technology still uses micro-convex balls, that is, the chip 301 and the chip 302 are connected by micro-convex balls 307 and the intermediate sheet 303 respectively. Taking chip 301 as an example, since the micro-convex ball 307 is a structure formed by welding a pair of copper balls attached to the intermediate sheet 303 and the chip 301 respectively, the size cannot be less than 40um due to process limitations. In this way, the number of micro-convex balls 307 set on a unit area of ​​the chip 301 is limited. When the area of ​​the chip 301 is fixed, the number of channels for communication between the chip 301 and the chip 302 through the micro-convex balls 307 is limited. In other words, the existing packaging technology cannot adapt to the trend of high frequency and high density in the field of electronic design.

[0065] In view of this, the first embodiment of the present disclosure provides a semiconductor device, which includes an interposer and a plurality of chips, wherein the second surface of the chip is coupled to the first surface of the interposer through a connection structure, wherein the interposer is used to realize the interconnection of the plurality of chips. According to the function, the plurality of chips may be chips with the same function or chips with different functions. In the case where the plurality of chips have different functions, for example, they include memory chips, radio frequency chips, processor chips, high-speed communication chips, microelectronic system chips, and the like. The semiconductor device is coupled to a substrate to form a packaged device, and the biggest difference between the packaged device formed and the existing packaged device using 2.5D packaging technology is the connection structure between the chip and the interposer included in the semiconductor device, which is no longer a micro-convex ball, but a structure formed based on van der Waals force.

[0066] Figure 4 FIG. 1 is a semiconductor device provided by the first embodiment of the present disclosure. Since the main improvement of the semiconductor device provided by the embodiment of the present disclosure lies in the connection structure between the chip and the interposer, Figure 4 Only two chips are shown schematically, but it should be understood that two chips or more than two chips can be coupled to the interposer. For multiple chips coupled to the interposer, the interposer is used to realize the connection between any two chips that need to be interconnected. Figure 4 The semiconductor device shown in FIG. 1 is used as an example to illustrate the semiconductor device provided by the embodiment of the present disclosure. In the case where more than two chips are coupled to the interposer, the second dielectric layer and the second conductive pin on the second surface of each chip can refer to Figure 4 Any chip shown.

[0067] Reference Figure 4, the semiconductor device 4X includes a chip 401, a chip 402 and an interposer 403, wherein the interposer 403 has a first redistribution layer 4051 built therein, and the first redistribution layer 4051 is used to realize the interconnection between the chip 401 and the chip 402. The second surfaces of the chip 401 and the chip 402 (i.e., the lower surface of the chip shown in the figure) are coupled to the first surface of the interposer 403 (i.e., the upper surface of the interposer 403 shown in the figure) through a connection structure. The connection structure here includes: a first dielectric layer 409 formed on the first surface of the interposer 403 and a first conductive pin 407 formed on the first surface of the interposer 403 and exposed from the first dielectric layer 409, and a second dielectric layer 410 formed on the second surface of each of the chips 401 and 402 and a second conductive pin 408 formed on the second surface of each of the chips 401 and 402 and exposed from the second dielectric layer 410, wherein the first dielectric layer 409 and the second dielectric layer 410 and the first conductive pin 407 and the second conductive pin 408 are bonded by the van der Waals force after the first dielectric layer 409 and the second dielectric layer 410 are pre-bonded and then annealed.

[0068] Specifically, the materials of the first dielectric layer 409 and the second dielectric layer 410 are insulating materials, such as silicon dioxide. As an inorganic material, silicon dioxide is not only insulating but also has a very low thermal expansion coefficient. In this way, on the basis of the insulation of the first dielectric layer 409 and the second dielectric layer 410, there will be no uneven thickness between the chip 401 / chip 402 and the intermediate sheet 403 due to the thermal expansion of the first dielectric layer 409 and the second dielectric layer 410, and the first conductive pin 407 and the second conductive pin 408 will not be out of contact due to the thermal expansion of the first dielectric layer 409 and the second dielectric layer 410. Figure 3 For the packaged device 300 shown in the figure, the organic filling glue 310 is filled around the micro-bumps 307 between the chip 301 / chip 302 and the intermediate sheet 303. Since the above-mentioned connection structure is used, there is no mismatch problem caused by the coefficient of thermal expansion (CTE) between the chip 401 / chip 402 and the intermediate sheet 403, so the connection between the chip 401 / chip 402 and the intermediate sheet 403 is more reliable.

[0069] The first conductive pin 407 and the second conductive pin 408 may be made of a single metal, such as but not limited to copper or nickel; or may be made of an alloy material with good conductive properties, such as but not limited to SnAg alloy, SnCu alloy, SnCuBi alloy, etc. In practice, copper may be used as the material of the first conductive pin 407 and the second conductive pin 408 for cost and process maturity considerations.

[0070] Based on the semiconductor device 4X described above, it can be understood that the second conductive pin 408 and the first conductive pin 407 are in a one-to-one correspondence, so the position of the second conductive pin 408 is set according to the position of the first conductive pin 407, and the number of the second conductive pin 408 is set according to the number of the first conductive pin 407. Figure 4 and Figure 5 First, the position setting of the first conductive pin 407 is described. Figure 4 and Figure 5 The same filled shapes represent structures labeled with the same number.

[0071] Reference Figure 4 , a longitudinal first signal via 406 is provided in the interposer 403, and the first signal via 406 is used to realize the communication between the chip 401 and the chip 402. Specifically, the second conductive pin 408→the first conductive pin 407→the first signal via 406→the first redistribution layer 4051→the first signal via 406→the first conductive pin 407→the second conductive pin 408 constitute the communication line between the chip 401 and the chip 402 (two such communication lines are shown in the figure). The first signal via 406 includes a first end located in the interposer 403 and connected to the redistribution layer 405 (i.e., the lower end of the first signal via 406 shown in the figure) and a second end located at a first position on the first surface of the interposer 403 (i.e., the upper end of the first signal via 406 shown in the figure), and the formation position of the first conductive pin 407 on the first surface of the interposer 403 includes the first position. That is, at least a part of all the first conductive pins 407 formed on the first surface of the interposer 403 are arranged at the first position. A first conductive pin 407 is disposed at a first position to achieve communication between the chip 401 and the chip 402. Since the first signal via 406 is longitudinal and the first end of the first signal via 406 is connected to the first redistribution layer 4051, the arrangement of at least a portion of the first conductive pin 407 is determined by the end position of the horizontal redistribution layer 405.

[0072] Reference Figure 5In some examples, a longitudinal second signal via 411 is provided in the interposer 403, and the second signal via 411 is used to realize communication between the chip 401 / chip 402 and the substrate coupled to the lower surface of the interposer 403. The second signal via 411 includes a third end (i.e., the lower end shown in the figure) and a fourth end (i.e., the upper end shown in the figure); a connector 412 is provided on the side of the interposer 403 opposite to the first surface of the interposer 403, and the third end is used to connect the connector 412; the fourth end is located at the second position of the first surface, and the formation position of the first conductive pin 407 on the first surface includes the second position. That is, at least a part of all the first conductive pins 407 formed on the first surface of the interposer 403 are arranged at the second position. One first conductive pin 407 is arranged at one second position, thereby realizing communication between the chip 401 / chip 402 and the substrate. Since the second signal via 411 is longitudinal, the arrangement of at least a part of the first conductive pins 407 is determined by the position of the third end.

[0073] In an optional embodiment, the third end is located on the side of the interposer 403 opposite to the first surface of the interposer 403 and is directly connected to the connector 412, so that the second conductive pin 408 → the first conductive pin 407 → the second signal via 411 → the connector 412 constitutes a communication line between the chip 401 / chip 402 and the substrate ( Figure 5 In this embodiment, the position of the third end is determined by the position of the connecting member 412 to which it is connected. One third end is connected to one connecting member 412 , and thus the arrangement of at least a portion of the first conductive pins 407 is directly determined by the position of the connecting member 412 .

[0074] In another optional embodiment, a longitudinal third signal via 413 is provided in the interposer 403, and the third signal via 413 includes a fifth end (i.e., the lower end shown in the figure) and a sixth end (i.e., the upper end shown in the figure), the fifth end is located on the side of the interposer 403 opposite to the first surface of the interposer 403 and connected to the connector 412, and the sixth end is located in the interposer 403; the interposer 403 also has a built-in second redistribution layer 4052; the third end is located in the interposer 403 and is connected to the sixth end through the second redistribution layer 4052. In this way, the second conductive pin 408 → first conductive pin 407 → second signal via 411 → second redistribution layer 4052 → third signal via 413 → connector 412 constitutes a communication line between the chip 401 / chip 402 and the substrate ( Figure 5 Two such communication lines are shown).

[0075] It should be noted that the intermediate film 403 with a built-in redistribution layer can be an integral structure formed by stacking multiple layered structures. Specifically, it can be formed by making a redistribution layer on the surface of a layered structure and then stacking other layered structures. In this way, the redistribution layer can be made at any depth in the intermediate film 403. Figure 5 In order to reduce the number of layered structures required during the formation of the intermediate film 403, the first redistribution layer 4051 and the second redistribution layer 4052 are only made at two different depths in the intermediate film 403, wherein all the first redistribution layers 4051 and a portion of the second redistribution layers 4052 are made in the upper portion of the intermediate film 403, and thus these redistribution layers are also called upper wiring layers; another portion of the second redistribution layers 4052 are made in the lower portion of the intermediate film 403, and thus these redistribution layers are also called lower wiring layers.

[0076] It should be understood that the depths of the first redistribution layer 4051 and the second redistribution layer 4052 in the interposer 403 are not limited in the present embodiment, as long as all the wiring layers in the interposer 403 and the signal vias connected to the wiring layers do not affect each other in position. In addition, the depths of the second signal via 411 and the third signal via 413 do not necessarily have a constant size relationship, as shown in FIG. Figure 5 The depth of the second signal via 411 may be greater than or less than the third signal via 413 . In other cases, the depth of the second signal via 411 may be equal to the third signal via 413 .

[0077] Reference Figure 5 When the second signal via 411 is combined with the third signal via 413 to realize the interconnection between the chip and the substrate on both surfaces of the interposer 403, due to the existence of the second redistribution wiring 4052, the third signal via 413 can be located at any position around the second signal via 411, so that the setting of the above-mentioned second position is not strictly limited by the position of the connector 412.

[0078] In this embodiment, since the third signal via 413 is longitudinal, the position of the sixth end is determined by the position of the connector 412; and the sixth end is connected to the third end through the second redistribution layer 4052, and the position of the third end is determined by the position of one end of the second redistribution layer 4052 connected to the third end. Therefore, the third end does not need to be directly connected to the connector 412 longitudinally, and the position setting of the third end is more flexible, thereby making the second position more flexible, that is, the position setting of the first conductive pin 407 can be more flexible.

[0079] The above-mentioned connector 412 is used to connect the interposer 403 and the substrate. In some examples, the interposer 403 can be connected to the upper surface of the substrate by flip chip on board. Flip chip on board is to make various micro "solder bumps" at corresponding points on the periphery of the interposer 403 itself, and the micro "solder bumps" are connected to the corresponding soldering points prepared in advance on the upper surface of the substrate, and then the soldering area on the interposer 403 is connected to the soldering area on the substrate by wire bonding process. In the case where there are "solder bumps" everywhere on the entire surface of the interposer 403, flip chip on board is specifically called C4 method (Controlled Collapsed Chip Connection), and in this case, the connector 412 is a C4 solder ball (C4 bump). The connector 412 in the embodiment of the present disclosure is an electronic connection element with a broader meaning, and its form includes but is not limited to a spherical shape, and it can not only be a connector formed by flip chip on board, so the term "connector" is defined according to its function.

[0080] It should be noted that the first signal via 406 is used to form a communication line between the chip 401 and the chip 402, so the provision of the first signal via 406 is necessary, so the above-mentioned first position must exist. The second signal via 411 and the third signal via 413 are both used to form a communication line between the chip 401 / chip 402 and the substrate, and the chip 401 / chip 402 does not have to communicate with the substrate through the signal via (for example, when a part of the chip 401 / chip 402 is located outside the intermediate sheet 403, the chip 401 / chip 402 can be directly connected to the substrate through the solder ball), so the above-mentioned second position does not necessarily exist. Moreover, even if the second position exists, the chip 401 / chip 402 can be interconnected with the substrate through any one or both of the two optional embodiments mentioned above. Therefore, the setting position of the first conductive pin 407 is not limited to Figure 4 and Figure 5 The situation shown.

[0081] Based on the above description of setting the position of the first conductive pin 407, since the first conductive pin 407 is set at the first position and the second position on the first surface of the intermediate piece 403, and one first conductive pin 407 is set at one first position and one first conductive pin 407 is set at one second position, the number of the first conductive pins 407 is determined by the total number of the first position and the second position on the first surface.

[0082] In any of the semiconductor devices 4X provided in the embodiments of the present disclosure, the first dielectric layer 409 and the second dielectric layer 410, as well as the first conductive pin 407 and the second conductive pin 408, are bonded by the van der Waals force after the first dielectric layer 409 and the second dielectric layer 410 are pre-bonded through an annealing process. It should be understood that, since the first dielectric layer 409 and the second dielectric layer 410 are pre-bonded first, and then the first dielectric layer 409 and the second dielectric layer 410, as well as the first conductive pin 407 and the second conductive pin 408, are bonded by the van der Waals force, and the thermal expansion coefficient of the material of the first conductive pin 407 is greater than that of the first dielectric layer 409, the first conductive pin 407 is recessed relative to the first dielectric layer 409 before the return process is performed. Similarly, the second conductive pin 408 is recessed relative to the second dielectric layer 410 before the return process is performed. An exemplary process is: firstly, in the chemical mechanical polishing process of the pin, the first conductive pin 407 is recessed relative to the first dielectric layer 409 and the second conductive pin 408 is recessed relative to the second dielectric layer 410, then the first dielectric layer 409 and the second dielectric layer 410 are pre-bonded at ambient temperature (i.e., the first dielectric layer 409 and the second dielectric layer 410 are in contact with each other), and then in the annealing process, the first conductive pin 407 and the second conductive pin 408 are bonded by diffusion of the pin material, and the first dielectric layer 409 and the second dielectric layer 410 are also more tightly bonded during the annealing process. Since the van der Waals force is a force that exists between molecules and brings molecules together, the first dielectric layer 409 and the second dielectric layer 410 can be made very thin, and the first conductive pin 407 and the second conductive pin 408 can also be made very small.

[0083] Based on the existing process, the size of the first conductive pin 407 and the second conductive pin 408 can be less than 10um. Compared with the lower limit size of 40um of the micro-convex ball, the number of conductive pins allowed to be produced per unit area of ​​the chip is significantly increased, so that the interconnection density between chips is increased, and the channels between chips are more dense (also known as increased bandwidth); and because the first conductive pin 407 and the second conductive pin 408 are part of the interconnection line between chips, the smaller size of the first conductive pin 407 and the second conductive pin 408 makes the interconnection line between chips shorter, so that the signal transmission between chips is faster.

[0084] Based on the existing process, the thickness of the first dielectric layer 409 and the second dielectric layer 410 can be less than 10um, which improves the performance of the semiconductor device 4X in many aspects. On the one hand, the interposer 403 does not need to be set to a large thickness to bear the weight of the first dielectric layer 409, the second dielectric layer 410, the first conductive pin 407 and the second conductive pin 408; and because the first surface of the interposer 403 does not need to be welded with micro-bumps, it is also free from stress damage, so the interposer 403 can be set to a thickness of less than 30um (because the surface of the interposer 403 opposite to the first surface is usually connected to the upper surface of the substrate by reverse welding, it has been verified that the thickness of the interposer 403 cannot be much less than 30um). Compared with the thickness of the interposer 303 of about 100um in the CoWoS packaging process, the thickness of the interposer 403 of less than 30um is greatly improved, so that the depth of the signal vias set in the interposer 403 is reduced, so that the signal can be transmitted faster between the chips and the substrate on both surfaces of the interposer 403; and the electrical performance loss caused by the signal vias is reduced, and the signal crosstalk caused by the signal vias is also reduced, which also helps to improve the integrity of the signal transmitted by the semiconductor device 4X. On the other hand, the interposer 403 is allowed to be set to a thickness of less than 30um, and the thickness of the first dielectric layer 409 and the second dielectric layer 410 can be less than 10um respectively, so the thickness from the second surface to the surface of the interposer 403 relative to the first surface is less than 50um. Compared with the thickness of about 100um of the intermediate sheet 303 and the thickness of about 50um of the organic filler 310 in the CoWoS packaging process, the second surface to the surface of the intermediate sheet 403 relative to the first surface has the advantage of obvious shortening (150um shortened to 50um), which not only makes the semiconductor device 4X thinner but also prevents the connector 412 from being deformed due to the heavy load, that is, the connection reliability of the connector 412 is also improved.

[0085] Method for manufacturing a semiconductor device according to a second embodiment of the present disclosure

[0086] Figure 6 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device includes an interposer and a plurality of chips, and the interposer is used to interconnect the plurality of chips. Figure 6 , the manufacturing method comprises:

[0087] Step S110 , forming a first dielectric layer and a first conductive pin on a first surface of the interposer, wherein the first conductive pin is recessed relative to the first dielectric layer.

[0088] Step S120 , forming a second dielectric layer and a second conductive pin on the second surface of the chip, wherein the second conductive pin is recessed relative to the second dielectric layer.

[0089] Step S130 , pre-bonding the first dielectric layer and the second dielectric layer, and achieving van der Waals force-dependent bonding between the first dielectric layer and the second dielectric layer, and between the first conductive pin and the second conductive pin through an annealing process.

[0090] The first dielectric layer can be formed on the first surface by chemical vapor deposition, and then the first conductive pin is formed in the first dielectric layer by etching and electroplating according to the position setting requirements of the first conductive pin. Similarly, the second dielectric layer can be formed on the second surface by chemical vapor deposition, and then the second conductive pin is formed in the second dielectric layer by etching and electroplating according to the position setting of the first conductive pin. The position setting of the first conductive pin can refer to the relevant description above, which will not be repeated here. The annealing process belongs to the prior art and will not be described in detail here.

[0091] In the embodiment of the present disclosure, the first dielectric layer and the second dielectric layer and the first conductive pin and the second conductive pin are bonded together by an annealing process, respectively, and each of these is dependent on the van der Waals force. This allows the size of the first conductive pin and the second conductive pin to be smaller, and the thickness of the first dielectric layer and the second dielectric layer to be smaller, thereby improving the performance of the semiconductor device in many aspects.

[0092] 7A-7B are process schematic diagrams of the steps included in the manufacturing method provided in this embodiment.

[0093] Reference Fig. 7A , the above step S110 forms the first dielectric layer 409 and the first conductive pin 407 on the first surface of the interposer 403 and some structures required to be set in the dielectric sheet 403 (such as the first signal via 405 and the redistribution layer 405 shown in the figure), thereby manufacturing module X3. The above step S120 forms the second dielectric layer 410 and the second conductive pin 408 on the second surface of the chip 401 and the chip 402, respectively, thereby manufacturing module X1 and module X2. The above step S130 connects the first dielectric layer 409 and the second dielectric layer 410 and connects the first conductive pin 407 and the second conductive pin 408, thereby manufacturing module X4. It should be noted that in the module X4 formed by the modules X1, X2 and X3, the second dielectric layer 410 between the chip 401 and the chip 402 is uninterrupted. This is caused by the annealing process. That is, during the annealing process, the second dielectric layer 410 of the module X1 and the second dielectric layer 410 of the module X2 expand and thus bond between the chip 401 and the chip 402. Figure 6 and Fig. 7A It can be seen that the manufacturing method provided in the embodiment of the present disclosure allows multiple initial modules (ie, module X1, module X2 and module X3) to be manufactured simultaneously, which is beneficial to improving the manufacturing efficiency.

[0094] Reference Figure 7B After manufacturing module X4, the following steps are performed successively: using molding material 415 to mold chip 401 and chip 402 to manufacture module X5 → thinning molding material 415 on chip 401 and chip 402 to expose the upper surfaces of chip 401 and chip 402 respectively to manufacture module X6 → thinning interposer 403 from the side of interposer 403 opposite to the first surface of interposer 403 to expose the target end so as to facilitate connecting connector 412 to the exposed target end to manufacture module X7. The target end is the target signal via (e.g. Figure 5 The second signal via 412 or the third signal via 413 shown in the figure is used to connect one end of the connector 412, and the connector 412 is used to connect the intermediate sheet 403 and the substrate in the above embodiment. Here, the intermediate sheet 403 is thinned after the structure of the first surface of the intermediate sheet 403 is completed, so that the possibility of damage to the intermediate sheet 403 due to the structure of the first surface is further reduced. Fig. 7A and Figure 7B It can be seen that although the above-mentioned semiconductor device 4X adopts a new connection structure to achieve respective connections between the first dielectric layer 409 and the second dielectric layer 410 and between the first conductive pin 407 and the second conductive pin 408, the manufacturing process of the semiconductor device 4X is compatible with existing plastic packaging and thinning processes.

[0095] Some implementation details of the above method embodiment have been described in detail in the previous device embodiment section, and you can refer to the previous device embodiment section, so they will not be repeated here.

[0096] Semiconductor device according to the third embodiment of the present disclosure

[0097] Figure 8 FIG. 2 is a semiconductor device provided by the third embodiment. Figure 8The semiconductor device 800 includes: an interposer 801, a first surface of the interposer 801 (i.e., the upper surface of the interposer 801 shown in the figure) is provided with a first conductive pin 802; a chip 803, a second surface of the chip 803 (i.e., the lower surface of the chip 803 shown in the figure) is provided with a second conductive pin 804, the second surface of the chip 803 is coupled to the first surface of the interposer 801 and the second conductive pin 804 is connected to the first conductive pin 802; a connector 805, which is provided on the side of the interposer 801 opposite to the first surface of the interposer 801 and is used to connect to the substrate. Among them, the interposer 801 is built with a longitudinal second signal via 806, a second redistribution layer 807 and a longitudinal third signal via 808; the second signal via 806 includes a third end (i.e., the lower end of the second signal via 806 shown in the figure) and a fourth end (i.e., the upper end of the second signal via 806 shown in the figure), and the fourth end is located on the first surface of the interposer 801 to connect to the first conductive pin 802; the third signal via 808 includes a fifth end (i.e., the lower end of the third signal via 808 shown in the figure) and a sixth end (i.e., the upper end of the third signal via 808 shown in the figure), and the fifth end is located on a side of the interposer 801 opposite to the first surface of the interposer 801 to connect to the connector 805; the third end and the sixth end are respectively located in the interposer 801 and are connected through the second redistribution layer 807.

[0098] It should be understood that in the semiconductor device 800 provided in this embodiment, the second conductive pin 804 and the first conductive pin 802 can be connected in the manner described in the first embodiment. Further, the semiconductor device 800 provided in this embodiment can also include other structures, such as the first dielectric layer 808 formed on the first surface of the interposer 801 and the second dielectric layer 809 formed on the second surface of the chip 803 in the first embodiment, and the first dielectric layer 808 and the second dielectric layer 809 can be connected in the manner described in the first embodiment. The embodiments of the present disclosure do not limit whether the semiconductor device 800 is provided with other structures, which other structures are provided, and how to provide other structures.

[0099] Some details of the semiconductor device 800 have been described in detail in the first embodiment above, and reference may be made to the parts of the previous device embodiments, so they will not be repeated here.

[0100] The semiconductor device 800 provided in the embodiment of the present disclosure sets a second redistribution layer 807 so that the positions of the interconnected first conductive pins 802 and connectors 805 do not have to be restricted to the same vertical line, which is conducive to the flexible setting of the positions of the first conductive pins 802 and the connectors 805.

[0101] The packaged device according to the fourth embodiment of the present disclosure

[0102] Fig. 9 FIG. 4 is a packaged device provided by the fourth embodiment. Fig. 9 The packaged device 900 includes a substrate 901 and a semiconductor device 902, wherein the substrate 901 is a package substrate or an intermediate substrate, and the substrate 901 has a third surface; the semiconductor device 902 is any semiconductor device 4X described in the first embodiment or any semiconductor device 800 described in the third embodiment, and the semiconductor device 902 includes an intermediate sheet having a side opposite to the first surface of the intermediate sheet coupled to the third surface of the substrate 901 (specifically, it can be through Fig. 9 Since any semiconductor device 4X described in the first embodiment is improved in thickness, reliability, signal transmission rate and integrity compared with the prior art, any semiconductor device 800 described in the third embodiment makes the arrangement positions of the first conductive pin 802 and the connector 805 more flexible, so many performances of the packaged device 900 are improved accordingly.

[0103] Electronic device according to the fifth embodiment of the present disclosure

[0104] Fig.10 1 is a structural block diagram of an electronic device provided by another embodiment of the present disclosure. As shown in the figure, the electronic device 10 provides a motherboard 1000, and various components are arranged on the motherboard 1000. The motherboard 1000 is used as an external circuit board of the above-mentioned packaged device 900. The motherboard 1000 is, for example, a printed circuit board. The motherboard 1000 carries various components, including but not limited to a processor 1002, a graphics processor 1003, a dynamic random access memory 1004, a static random access memory 1010, a flash memory 1006, a GPS chip 1008 and even a graphics card 1005, a Bluetooth chip 1007, a video codec 1009, etc. These components are coupled to the motherboard 1000 by physical and electrical means. The motherboard 1000 provides communication functions between various components.

[0105] Among the components carried on the motherboard 1000, some need to integrate multiple chips. For the components that need to integrate multiple chips, at least some of them are packaged into a relatively light and thin packaged device by the packaging method provided in the above embodiment. In a further embodiment, for example, the functions of some components can be integrated in the processor, for example, the dynamic random access memory 1004, the static random access memory 1010 can be packaged into a relatively light and thin packaged device with the processor 1002 by the packaging method provided in the above embodiment and used as the processor 1002 integrated with the dynamic random access memory 1004 and the static random access memory 1010 of this embodiment. The packaged device packaged by the packaging method provided in the above embodiment performs well in many performances, so many performances of the electronic device 10 are also significantly improved compared with the prior art.

[0106] The processor comes from a traditional computer system, and it is a processor that plays a role of overall control and scheduling. The processor is very effective in logic control, but often lacks in specialization, so the processor is sometimes integrated with various special acceleration units, for example, an acceleration unit dedicated to neural network model calculation, a graphics processor with higher efficiency in graphics processing, etc. In this embodiment, the processor 1002 and the graphics processor 1003 are integrated into the same electronic device 10 through the motherboard 1000.

[0107] The communication chip implements wireless communication to facilitate the transmission of data to and from the electronic device 10. The term "wireless" does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain wires. The communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. Since there are many different communication protocols, independent communication chips can be constructed based on each communication protocol. For example, the motherboard 1000 in the figure is provided with a GPS chip 1008 and a Bluetooth chip 1007. In addition, the board 1000 is also provided with some chips dedicated to longer-distance wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc. In addition, other functions, such as a compass, various component drivers, etc., can also form various components and be integrated into the electronic device 10 through the motherboard 1000.

[0108] In addition, the electronic device also includes some components that are not integrated into the electronic device 10 through the motherboard 1000, such as a sound card 1011, a keyboard 1012, a mouse 1013 and a network card 1014. These components provide input and output functions for the electronic device 10.

[0109] The commercial value of the disclosed embodiments

[0110] In the semiconductor device provided by the embodiment of the present disclosure, the interposer and the multiple chips laterally fixed on the first surface of the interposer are no longer connected by micro-convex balls, but are connected by a new connection structure. The conductive pins between the chip and the interposer can be set very small and the position is flexible, and the connection structure between the chip and the interposer can be set very thin as a whole, and the allowable thickness of the interposer can also be greatly reduced relative to the prior art. This improvement helps to reduce the product thickness of 2.5D packaged devices, which is in line with the trend of thinning, miniaturization and flexibility of products, and the interconnection density between chips can be increased, the rate and integrity of the signal transmitted by the semiconductor device can be improved, and the reliability of the physical connection between different parts in the semiconductor device can be improved. Therefore, the semiconductor device provided by the embodiment of the present disclosure and the packaged device and electronic device including the semiconductor device provided by the embodiment of the present disclosure have good market prospects, and thus generate high economic value and commercial value.

[0111] It should be understood that the same or similar parts between the various embodiments in this specification can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0112] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0113] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0114] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. A semiconductor device, comprising: Intermediary film; a plurality of chips, wherein the second surface of the chips is coupled to the first surface of the interposer via a connection structure; Wherein, the interposer is used to realize the interconnection of multiple chips; The connection structure includes a first dielectric layer formed on a first surface of the interposer and a first conductive pin formed on the first surface of the interposer and exposed from the first dielectric layer, and also includes a second dielectric layer formed on a second surface of the chip and a second conductive pin formed on the second surface of the chip and exposed from the second dielectric layer; Furthermore, the first dielectric layer and the second dielectric layer, as well as the first conductive pin and the second conductive pin, are bonded by the van der Waals force respectively through an annealing process after the first dielectric layer and the second dielectric layer are pre-bonded; The first dielectric layer and the second dielectric layer are pre-bonded to contact each other, and the first conductive pin and the second conductive pin are combined by diffusion of the pin material during the annealing process.

2. The semiconductor device according to claim 1, wherein A longitudinal first signal via is provided in the interposer, and the first signal via includes a first end and a second end; The interposer also has a first rewiring layer built in, and the first rewiring layer is used to realize the interconnection of multiple chips; The first end is located in the interposer and connected to the first redistribution layer; The second end is located at a first position on the first surface of the interposer, and the formation position of the first conductive pin on the first surface of the interposer includes the first position.

3. The semiconductor device according to claim 1, wherein A longitudinal second signal via is provided in the interposer, and the second signal via includes a third end and a fourth end; A connecting piece is disposed on a side of the intermediate sheet opposite to the first surface of the intermediate sheet, and the third end is used to connect the connecting piece; The fourth end is located at a second position on the first surface of the interposer, and the formation position of the first conductive pin on the first surface of the interposer includes the second position.

4. The semiconductor device according to claim 3, wherein: The third end is located on a surface of the interposer opposite to the first surface of the interposer and is directly connected to the connecting member.

5. The semiconductor device according to claim 3, wherein: A third longitudinal signal via is provided in the interposer, the third signal via comprises a fifth end and a sixth end, the fifth end is located on a side of the interposer opposite to the first surface of the interposer and connected to the connector, and the sixth end is located in the interposer; The interposer also has a built-in second redistribution layer; The third end is located in the interposer and is connected to the sixth end through the second redistribution layer.

6. The semiconductor device according to claim 1, wherein The materials of the first dielectric layer and the second dielectric layer are both silicon dioxide.

7. The semiconductor device according to claim 1, wherein The first conductive pin and the second conductive pin are both made of copper.

8. A method for manufacturing a semiconductor device, the semiconductor device comprising an interposer and a plurality of chips, the interposer being used to interconnect the plurality of chips, the manufacturing method comprising: forming a first dielectric layer and a first conductive pin on a first surface of the interposer, wherein the first conductive pin is recessed relative to the first dielectric layer; forming a second dielectric layer and a second conductive pin on a second surface of the chip, wherein the second conductive pin is recessed relative to the second dielectric layer; Pre-bonding the first dielectric layer and the second dielectric layer, and achieving Van der Waals force-dependent bonding between the first dielectric layer and the second dielectric layer, and between the first conductive pin and the second conductive pin through an annealing process; The first dielectric layer and the second dielectric layer are pre-bonded to contact each other, and the first conductive pin and the second conductive pin are combined by diffusion of the pin material during the annealing process.

9. The manufacturing method according to claim 8, wherein: A longitudinal target signal via is provided in the interposer, and a target end of the target signal via is used to connect a connector, and the connector is used to connect the interposer and the substrate; The manufacturing method further includes: after the first dielectric layer and the second dielectric layer are connected and the first conductive pin and the second conductive pin are connected, thinning the intermediate sheet from a side of the intermediate sheet opposite to the first surface of the intermediate sheet to expose the target end; and connecting the connector to the exposed target end.

10. A semiconductor device comprising: An interposer, wherein a first surface of the interposer is provided with a first conductive pin; A chip, wherein a second conductive pin is disposed on a second surface of the chip, the second surface of the chip is coupled to the first surface of the interposer and the second conductive pin is connected to the first conductive pin; A connecting member, disposed on a surface of the intermediate sheet opposite to the first surface of the intermediate sheet; The interposer is built with a second longitudinal signal via, a second redistribution layer and a third longitudinal signal via; The second signal via includes a third end and a fourth end, and the fourth end is located on the first surface of the interposer to connect to the first conductive pin; The third signal via comprises a fifth end and a sixth end, wherein the fifth end is located on a side of the interposer opposite to the first surface of the interposer to connect to the connector; The third terminal and the sixth terminal are each located in the interposer and connected through the second redistribution layer; After the pre-bonding process, the first conductive pin and the second conductive pin are bonded together by the diffusion of the pin material during the annealing process, thereby achieving the respective Van der Waals force-dependent bonding.

11. A packaging device, comprising: a substrate having a third surface; The semiconductor device according to any one of claims 1 to 7, or the semiconductor device according to claim 10; The semiconductor device includes an interposer whose surface opposite to the first surface of the interposer is coupled to the third surface of the substrate.

12. An electronic device comprising: An external circuit board and the packaged device as claimed in claim 11, wherein the packaged device is disposed on the external circuit board.

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