Chip stacking packaging structure adopting flexible RDL and packaging method thereof

Abstract

The invention relates to the technical field of chip packaging, in particular to a chip stacking packaging structure adopting flexible RDL and a packaging method. Comprising one or more chip sets, each chip set comprises a flexible RDL, a first chip, a second chip and first bumps, dielectric layers and first metal layers are arranged in the flexible RDL, the dielectric layers are provided with oppositely arranged side faces, the first metal layers are located on the oppositely arranged side faces, and the oppositely arranged first metal layers are connected with the first chip and the second chip through the first bumps respectively. The surface, connected with the outside, of the dielectric layer is provided with a second metal layer, and the dielectric layer is connected with other chip sets or second salient points through the second metal layer. Compared with the prior art, the cost is low, the interconnection density is high, the productivity is greatly improved, and the total thickness after final bending and stacking is greatly reduced. And the bending and stacking adopt a hot pressing mode, so that the molding compound is cured and adhered again, the glue film adhesion between the chips is replaced, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip stacking packaging structure and a packaging method using a flexible RDL. Background Art

[0002] At present, in the packaging field, especially in the field of memory chip packaging, stacking is generally considered to expand the storage capacity of a single package. Fig. 9 As shown in FIG, multiple chips are stacked together in sequence and then wire bonded to complete the electrical connection, but the interconnection density is limited by the wire bonding process. Fig.10 As shown in FIG. 1 , the HBM packaging module is mainly structured by stacking chips on stacked chips and interconnecting the stacked chips through TSV. However, its disadvantage is that the process cost of using TSV and Si interposer is very high. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the present invention provides a chip stacking packaging structure and a packaging method using a flexible RDL.

[0004] To achieve the above-mentioned purpose, a chip stacking packaging structure using a flexible RDL is designed, including one or more chipsets, wherein the chipsets include a flexible RDL, chip one, chip two, and bump one. A dielectric layer and a metal layer one are provided in the flexible RDL, the dielectric layer is provided with oppositely arranged side surfaces, the metal layer one is located on the oppositely arranged side surfaces, and the oppositely arranged metal layers one are respectively connected to chip one and chip two through bump one, and a metal layer two is provided on the surface of the dielectric layer connected to the outside world, which is connected to other chipsets or bump two through the metal layer two.

[0005] The chip 1, the chip 2 and the outer sides are provided with a plastic sealing layer, and the plastic sealing layer wraps the chip 1, the chip 2 and the bump 1.

[0006] When the dielectric layer is connected to other chip groups through the second metal layer, the dielectric layers of adjacent chip groups are connected.

[0007] In a single chipset, the flexible RD is C-shaped; after several chipsets are stacked, the flexible RDL is S-shaped.

[0008] The first and second bumps are solder balls.

[0009] To achieve the above purpose, a chip stacking packaging method using flexible RDL is designed, comprising the following steps: S1, connecting the flexible RDL on the carrier through temporary bonding glue, and the flexible RDL is provided with a dielectric layer and a metal layer; S2, mounting a plurality of chips 1 on one side surface of the flexible RDL by flip-chip method, and attaching a soluble adhesive film between adjacent chips 1; S3, plastic encapsulation, so that the plastic encapsulation layer fills the gap between the chip 1, the bump 1 and the flexible RDL and the adhesive film, and wraps the chip 1 and the bump 1; S4, debonding, removing temporary bonding glue and carrier film; S5, repeating step S2 to step S3 to form a plurality of chips 2 on the other side surface of the flexible RDL; S6, thinning the plastic sealing layer on both sides to expose the soluble adhesive film; S7, removing the soluble adhesive film to obtain a temporary encapsulation body; S8, bending and hot pressing the temporary package obtained in step S7 to obtain a multi-layer stacked package.

[0010] In the step S2, the soluble adhesive film is a hydrosol.

[0011] In the step S3, plastic sealing is performed by using a MUF process.

[0012] The method further includes step S9 of electrically connecting the second metal layer of the outermost flexible RDL to the second bump.

[0013] Compared with the prior art, the present invention has the following beneficial effects: 1. Low cost: No need to form through silicon vias (TSV) in the chip, which greatly reduces the overall production cost.

[0014] 2. High interconnection density: RDL replaces traditional wire bonding.

[0015] 3. After the chip is flip-chip mounted, the MUF process is used to replace the traditional Underfill, which greatly improves the production capacity for small chip FC.

[0016] 4. Thinning can be performed after plastic encapsulation, and the chip can be further thinned, and the total thickness after bending and stacking is greatly reduced.

[0017] 5. The bending and stacking adopts the hot pressing method to make the plastic encapsulation material solidify and adhere again, replacing the film adhesion between chips, thus reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure of a single chipset of the present invention.

[0020] Figure 3 It is a schematic diagram of step S1 of the present invention.

[0021] Figure 4 It is a schematic diagram of step S2 of the present invention.

[0022] Figure 5 It is a schematic diagram of step S3 of the present invention.

[0023] Figure 6 It is a schematic diagram of step S4 of the present invention.

[0024] Figure 7 It is a schematic diagram of step S5 of the present invention.

[0025] Figure 8 It is a schematic diagram of steps S6 and S7 of the present invention.

[0026] Fig. 9 Schematic diagram of chip stacking in the prior art Figure 1 .

[0027] Fig.10 Schematic diagram of chip stacking in the prior art Figure 2 . DETAILED DESCRIPTION

[0028] The present invention will be further described below with reference to the accompanying drawings.

[0029] like Figure 1 to Figure 2 As shown, it includes one or more chipsets, and the chipset 1 includes a flexible RDL2, a chip 3-1, a chip 3-2, and a bump 4-1. A dielectric layer 2-3 and a metal layer 2-1 are provided in the flexible RDL2. The dielectric layer 2-3 is provided with relatively arranged side surfaces. The metal layer 2-1 is located on the relatively arranged side surfaces, and the relatively arranged metal layers 2-1 are respectively connected to the chip 3-1 and the chip 3-2 through the bump 4-1. The surface of the dielectric layer 2-3 connected to the outside world is provided with a metal layer 2-2, and is connected to other chipsets 1 or bumps 4-2 through the metal layer 2-2.

[0030] A plastic sealing layer 5 is arranged on the outer sides of the chip 1 3 - 1 and the chip 2 3 - 2 . The plastic sealing layer wraps the chip 1 3 - 1 , the chip 2 3 - 2 and the bump 1 4 - 1 to play a protective role.

[0031] When the dielectric layer 2 - 3 is connected to other chipsets 1 through the metal layer 2 - 2 , the dielectric layers 2 - 3 of adjacent chipsets 1 are connected.

[0032] In the single chipset 1 of this embodiment, the flexible RDL 2 is C-shaped. The C-shaped flexible RDL has two side surfaces arranged opposite to each other.

[0033] After a number of chipsets 1 are stacked, the flexible RDL 2 is in an S shape.

[0034] In this embodiment, solder balls are used as the first bump 4-1 and the second bump 4-2.

[0035] like Figures 3 to 8 As shown, the chip stacking packaging method using the flexible RDL comprises the following steps: S1, connecting the flexible RDL2 on the carrier 7 through the temporary bonding glue 6, and the flexible RDL2 is provided with a dielectric layer 2-3 and a metal layer 2-1; S2, mounting a plurality of chips 3-1 on one side surface of the flexible RDL 2 by flip-chip method, and attaching a soluble adhesive film 8 between adjacent chips 3-1; S3, plastic sealing, so that the plastic sealing layer 5 fills the gap between the chip 3-1, the bump 4-1 and the flexible RDL 2 and the adhesive film 8, and wraps the chip 3-1 and the bump 4-1; S4, debonding, removing the temporary bonding glue 6 and the carrier film 7; S5, repeating step S2 to step S3 to form a plurality of chips 3-2 on the other side surface of the flexible RDL2; S6, the plastic sealing layer 5 on both sides is thinned to expose the soluble adhesive film 8; the plastic sealing layer on the surface of the chip away from the bump is also removed, and the plastic sealing layer on the chip, the bump and other positions is retained.

[0036] S7, removing the soluble adhesive film 8 to obtain a temporary encapsulation body; S8, bending and hot pressing the temporary package obtained in step S7 to obtain a multi-layer stacked package; the bent dielectric layer presents an S shape, such as Figure 1 shown.

[0037] S9, electrically connecting the metal layer 2-2 of the outermost flexible RDL2 to the bump 4-2.

[0038] In step S2, the soluble adhesive film 8 is made of hydrosol. In step S7, the hydrosol is removed by washing with water.

[0039] In step S3, the MUF process is used for plastic encapsulation to fill the gaps between the chip, bumps, flexible RDL, and adhesive film, which helps to solidify tightly.

[0040] The present invention does not need to form through silicon vias (TSV) in the chip, which greatly reduces the overall production cost. Flexible RDL is used to replace traditional wire bonding, and the interconnection density is high. After the chip is flip-chip mounted, the MUF process is used to replace the traditional Underfill, which greatly improves the production capacity for small chips FC. Thinning can be performed after plastic encapsulation, and the chip can be further thinned, and the total thickness after bending and stacking is greatly reduced. The bending and stacking adopts hot pressing to make the plastic encapsulation material solidify and adhere again, replacing the use of film adhesion between chips, reducing production costs.

Claims

1. A chip stacking packaging structure using a flexible RDL, characterized in that: The invention comprises one or more chipsets, wherein the chipset (1) comprises a flexible RDL (2), a chip one (3-1), a chip two (3-2), and a bump one (4-1). A dielectric layer (2-3) and a metal layer one (2-1) are provided in the flexible RDL (2). The dielectric layer (2-3) is provided with oppositely arranged side surfaces. The metal layer one (2-1) is located on the oppositely arranged side surfaces. The oppositely arranged metal layers one (2-1) are respectively connected to the chip one (3-1) and the chip two (3-2) through the bump one (4-1). A metal layer two (2-2) is provided on the surface of the dielectric layer (2-3) connected to the outside world, and the dielectric layer is connected to other chipsets (1) or the bump two (4-2) through the metal layer two (2-2).

2. The chip stacking packaging structure using flexible RDL according to claim 1, characterized in that: The chip 1 (3-1) and the chip 2 (3-2) are provided with a plastic sealing layer (5) on the outside, and the plastic sealing layer wraps the chip 1 (3-1), the chip 2 (3-2) and the bump 1 (4-1).

3. The chip stacking packaging structure using flexible RDL according to claim 1, characterized in that: When the dielectric layer (2-3) is connected to other chip groups (1) via the second metal layer (2-2), the dielectric layers (2-3) of adjacent chip groups (1) are connected.

4. The chip stacking packaging structure using flexible RDL according to claim 1, characterized in that: In a single chipset (1), the flexible RDL (2) is C-shaped; after a plurality of chipsets (1) are stacked, the flexible RDL (2) is S-shaped.

5. The chip stacking packaging structure using flexible RDL according to claim 1, characterized in that: The bump 1 (4-1) and the bump 2 (4-2) are solder balls.

6. A chip stacking packaging method using flexible RDL, characterized in that: The steps include: S1, connecting a flexible RDL (2) on a carrier (7) by means of a temporary bonding adhesive (6), wherein a dielectric layer (2-3) and a metal layer 1 (2-1) are provided in the flexible RDL (2); S2, mounting a plurality of chips 1 (3-1) on one side surface of the flexible RDL (2) by flip-chip method, and attaching a soluble adhesive film (8) between adjacent chips 1 (3-1); S3, plastic encapsulation, so that the plastic encapsulation layer (5) fills the gaps between the chip 1 (3-1), the bump 1 (4-1) and the flexible RDL (2), and the adhesive film (8), and wraps the chip 1 (3-1) and the bump 1 (4-1); S4, debonding, removing the temporary bonding glue (6) and the carrier (7); S5, repeating steps S2 to S3 to form a plurality of chips 2 (3-2) on the other side surface of the flexible RDL (2); S6, thinning the plastic sealing layer (5) on both sides of the surface to expose the soluble adhesive film (8); S7, removing the soluble adhesive film (8) to obtain a temporary encapsulation body; S8, bending and hot pressing the temporary package obtained in step S7 to obtain a multi-layer stacked package.

7. The chip stacking packaging method using flexible RDL according to claim 6, characterized in that: In the step S2, the soluble adhesive film (8) is a hydrosol.

8. The chip stacking packaging method using flexible RDL according to claim 6, characterized in that: In the step S3, plastic sealing is performed by using a MUF process.

9. The chip stacking packaging method using flexible RDL according to claim 6, characterized in that: The method further includes step S9 of electrically connecting the metal layer 2 (2-2) of the outermost flexible RDL (2) to the bump 2 (4-2).

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