Quantum well field effect transistor and method for manufacturing the same

Abstract

A quantum well field effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer include undoped aluminum indium antimonide. The quantum well layer includes indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. The gate contact is on the dielectric layer, and the dielectric layer is on the spacer layer. By setting the barrier layer and the spacer layer as undoped layers, the performance of the QWFET can be improved.

Description

Technical Field

[0001] The present disclosure relates to quantum well field effect transistors (QWFETs) and methods of making the same. Background Art

[0002] Quantum well field effect transistors (QWFETs) have been studied for low voltage, high performance applications. In particular, QWFETs having quantum wells containing indium antimonide have been studied due to the high carrier mobility of indium antimonide. Figure 1 A conventional QWFET 10 including an indium antimonide quantum well is shown. The conventional QWFET 10 includes an aluminum indium antimonide (In x Al 1-x Sb) barrier layer 12, an indium antimonide quantum well layer 14 on the barrier layer 12, and an aluminum indium antimonide (InSb) on the quantum well layer 14. x Al 1-x The barrier layer 12 includes a first gate electrode 14 and a second gate electrode 20. The first gate electrode 14 includes a first gate electrode 22 and a second gate electrode 24. The first gate electrode 14 includes a first gate electrode 22 and a second gate electrode 24. The first gate electrode 14 includes a first gate electrode 22 and a second gate electrode 24. The first gate electrode 14 includes a first gate electrode 22 and a second gate electrode 24. The first gate electrode 14 includes a first gate electrode 22 and a second gate electrode 24.

[0003] The barrier layer 12 and the spacer layer 16 are remotely doped to form a first delta-doped layer 26A adjacent to the bottom side of the quantum well layer 14 and a second delta-doped layer 26B adjacent to the top side of the quantum well layer 14. Thus, the quantum well layer 14 is sandwiched between the first delta-doped layer 26A and the second delta-doped layer 26B. The delta-doped layer 26 is doped to provide excess electrons (e.g., using silicon as a dopant), which are pulled into the quantum wells formed by the quantum well layer 14. Thus, the quantum well layer 14 forms a conductive channel between the source contact 18 and the drain contact 20 during steady-state conditions (i.e., zero gate bias), and the conventional QWFET 10 is a depletion mode device.

[0004] In operation, the conventional QWFET 10 is in an on state so that when a zero bias or a positive bias is applied to the gate contact 24, conduction exists between the drain contact 20 and the source contact 18. As discussed above, this is because the electrons added by the delta doping layer 26 are pulled into the quantum well formed by the quantum well layer 14 so that the quantum well layer 14 forms a conductive channel. Therefore, the conventional QWFET 10 can be referred to as a depletion mode device. In order to turn off the conventional QWFET 10 so that conduction between the drain contact 20 and the source contact 18 is limited, a negative bias voltage below the device threshold voltage is applied to the gate contact 24. The negative bias creates an electric field that pushes electrons away from the quantum well layer 14, and thus limits conduction between the drain contact 20 and the source contact 18.

[0005] Although functional, the performance of conventional QWFET 10 may be unstable over time. For example, the conductivity of conventional QWFET 10 may drift or even suddenly jump over time. Therefore, a QWFET 10 device with stable performance is needed. Summary of the invention

[0006] In an exemplary embodiment, a quantum well field effect transistor (QWFET) includes a barrier layer, a quantum well layer, and a spacer layer. The quantum well layer is on the barrier layer. The barrier layer and the spacer layer include undoped aluminum indium antimonide. The quantum well layer includes indium antimonide. The spacer layer is on the quantum well layer. The quantum well layer and the spacer layer are between a source contact and a drain contact. The gate contact is on the dielectric layer, and the dielectric layer is on the spacer layer. By setting the barrier layer and the spacer layer as undoped layers, the performance of the QWFET can be improved.

[0007] In an exemplary embodiment, a method for manufacturing a QWFET includes: providing a barrier layer, providing a quantum well layer on the barrier layer, providing a spacer layer on the quantum well layer, providing a source contact and a drain contact, and providing a dielectric layer and a gate contact. The barrier layer and the spacer layer include undoped aluminum indium antimonide. The quantum well layer includes indium antimonide. The source contact and the drain contact are provided so that the quantum well layer and the spacer layer are between the source contact and the drain contact. The dielectric layer is provided on the spacer layer, and the gate contact is provided on the dielectric layer. By providing the barrier layer and the spacer layer as undoped layers, the performance of the QWFET device provided by the method can be improved.

[0008] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0010] Figure 1 A conventional quantum well field effect transistor (QWFET) is illustrated.

[0011] Figure 2 A QWFET according to one embodiment of the present disclosure is illustrated.

[0012] Figure 3 is a flow chart illustrating a method for fabricating a QWFET according to one embodiment of the present disclosure.

[0013] 4A to 4F The diagram shows an embodiment according to the present disclosure. Figure 3 Method for fabricating QWFETs. DETAILED DESCRIPTION

[0014] The embodiments set forth below represent information necessary for enabling those skilled in the art to practice these embodiments and to illustrate the best mode for practicing these embodiments. After reading the following description according to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize the application of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0015] It should be understood that, although the terms first, second, etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "extending to" another element "on", it can be directly on or directly extending to another element or there may also be an intermediate element. In contrast, when an element is referred to as being "directly on" or "extending directly to" another element "on", there are no intermediate elements. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "above" or extending "above" another element, it can be directly "above" or extending "above" another element or there may also be an intermediate element. In contrast, when an element is referred to as being "directly on" or "directly on" another element "extending", there are no intermediate elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element or there may be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0017] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0018] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to also include plural forms. It will be further understood that when used in this article, the terms "include" and / or "comprise" specify the existence of stated features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and related technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0020] As discussed above, conventional quantum well field effect transistors (QWFETs) experience inconsistent performance over time, and in particular, experience conductivity drift and jumps over time. The inventors of the present subject matter have discovered that the inconsistency in performance is caused by disorder generated in the semiconductor structure of the conventional QWFET, and further discovered that the disordered structure is caused by the delta-doped layer due to the presence of excess electrons therein.

[0021] To address the defects of conventional QWFETs, Figure 2 A QWFET 28 is shown according to one embodiment of the present disclosure. The QWFET 28 includes a barrier layer 30, a quantum well layer 32 on the barrier layer 30, and a spacer layer 34 on the quantum well layer 32. A source contact 36 and a drain contact 38 are adjacent to the quantum well layer 32 and the spacer layer 34 on the barrier layer 30, such that the source contact 36 and the drain contact 38 are in contact with the quantum well layer 32 and the spacer layer 34, and the quantum well layer 32 and the spacer layer 34 are between the source contact 36 and the drain contact 38. A dielectric layer 40 is on the spacer layer 34. A gate contact 42 is on the dielectric layer 40.

[0022] It is noteworthy that in QWFET 28, both barrier layer 30 and spacer layer 34 are undoped. In other words, QWFET 28 does not include any delta-doped layers, so that the doping profiles of the entirety of spacer layer 34 and the entirety of barrier layer 30 are flat. There is only doping inherent to the materials of barrier layer 30 and spacer layer 34.

[0023] In one embodiment, the barrier layer 30 and the spacer layer 34 include aluminum indium antimonide (In x Al 1-x Sb - more specifically, In with 8-12% Al x Al 1-x Sb). As discussed above, no dopant is introduced into the aluminum indium antimonide, so that in at least one embodiment, the barrier layer 30 and the spacer layer 34 consist only of undoped aluminum indium antimonide. As discussed herein, "undoped" means that it is not intentionally or unintentionally doped with additional dopants (such as silicon), and therefore the barrier layer 30 and the spacer layer 34 only include the inherent doping concentration of the aluminum indium antimonide. The quantum well layer 32 may include indium antimonide. The source contact 36 and the drain contact 38 may include any suitable metal for making ohmic contacts, and in particular may include titanium gold, niobium titanium nitride, etc. The dielectric layer 40 may include any suitable oxide, such as aluminum oxide. The gate contact 42 may include any suitable metal for making a gate contact, such as titanium gold.

[0024] In various embodiments, the thickness of barrier layer 30 may be between 10 nm and 4 μm. The thickness of quantum well layer 32 may be between 10 nm and 30 nm. The thickness of spacer layer 34 may be between 10 nm and 50 nm. The distance between source contact 36 and drain contact 38 may be between 100 nm and 10 μm, which define the channel of the device. The thickness of dielectric layer 40 may be between 10 nm and 40 nm.

[0025] In operation, the QWFET 28 is off so that there is no conduction or minimal conduction between the drain contact 38 and the source contact 36 when a zero bias or negative bias is applied to the gate contact 42. This is because there is no delta doping layer, so there are not enough electrons trapped in the quantum wells created by the quantum well layer 32 to set up a conductive channel. The QWFET 28 can therefore be referred to as an enhancement mode device, which is in contrast to the conventional QWFET discussed above. In order to turn on the QWFET 28 so that there is conduction between the drain contact 38 and the source contact 36, a positive bias voltage above the threshold voltage of the device is applied to the gate contact 42. The positive bias voltage creates an electric field that pulls the electric field of the electrons into the quantum well layer 32 and thus sets up a conductive channel between the drain contact 38 and the source contact 36. The electrons can originate from the source contact 36 and drain contact 38 regions.

[0026] It is noteworthy that the performance of QWFET 28 is very stable over time. The conductivity of QWFET 28 has minimal drift over time and does not jump. As discussed above, this is due to the removal of the delta doping layers required for conventional QWFETs, as these layers would create disorder in the semiconductor structure of conventional QWFETs. Therefore, QWFET 28 provides better performance than its conventional counterparts.

[0027] Figure 3 is a flow chart illustrating a method for fabricating QWFET 28 according to one embodiment of the present disclosure. FIG. 4A to FIG. 4F The method steps and Figure 3 , and thus in the following Figure 3 Discuss together. Setting barrier layer 30 (frame 100 and Figure 4A The barrier layer 30 may be provided by any suitable process, such as by an epitaxial process. The quantum well layer 32 is provided on the barrier layer 30 (blocks 102 and Figure 4B ). Similarly, the quantum well layer 32 can be provided by any suitable process, such as by an epitaxial process. The spacer layer 34 is provided on the quantum well layer 32 (blocks 104 and Figure 4C ). Likewise, the spacer layer 32 may be provided by any suitable process, for example, by an epitaxial process.

[0028] Setting source contact 36 and drain contact 38 (blocks 106 and Figure 4D ). The source contact 36 and the drain contact 38 may be provided by any suitable process, such as a deposition process. One or more trenches for the source contact 36 and the drain contact 38 may be provided before the metal for the source contact 36 and the drain contact 38 is deposited. The dielectric layer 40 is provided on the spacer layer 34 (blocks 108 and Figure 4E The dielectric layer 40 may be deposited by any suitable process, such as a deposition process such as atomic layer deposition. The gate contact 42 is disposed on the dielectric layer 40 (blocks 110 and Figure 4F ). The gate contact 42 may be provided by any suitable process, such as a deposition process. Those skilled in the art will readily appreciate that there may be many different processes to provide each of the barrier layer 30, quantum well layer 32, spacer layer 34, source contact 36, drain contact 38, dielectric layer 40, and gate contact 42, all of which are contemplated herein.

[0029] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A quantum well field effect transistor (QWFET), comprising: a source contact, a drain contact, and a gate contact; a barrier layer comprising aluminum indium antimonide, wherein the barrier layer is undoped; a quantum well layer on the barrier layer, wherein the quantum well layer is between the source contact and the drain contact, and the quantum well layer comprises indium antimonide; a spacer layer directly on the quantum well layer, wherein the spacer layer is between the source contact and the drain contact, the spacer layer comprises aluminum indium antimonide, the spacer layer is undoped, and there is no delta-doped layer directly adjacent to the spacer layer; as well as A dielectric layer is directly on the spacer layer, wherein the gate contact is on the dielectric layer opposite the spacer layer.

2. The QWFET of claim 1, wherein the quantum well layer is directly on the barrier layer, and the spacer layer is directly on the quantum well layer.

3. The QWFET of claim 2, wherein the barrier layer and the spacer layer are composed of aluminum indium antimonide.

4. The QWFET of claim 3, wherein the QWFET is an enhancement mode device.

5. The QWFET of claim 2, wherein the QWFET is an enhancement mode device.

6. The QWFET of claim 1 wherein the barrier layer and the spacer layer are comprised of aluminum indium antimonide.

7. The QWFET of claim 6, wherein the QWFET is an enhancement mode device.

8. The QWFET of claim 1, wherein the QWFET is an enhancement mode device.

9. A method for manufacturing a quantum well field effect transistor (QWFET), comprising: providing a barrier layer, wherein the barrier layer comprises aluminum indium antimonide and the barrier layer is undoped; Disposing a quantum well layer on the barrier layer, wherein the quantum well layer comprises indium antimonide; Disposing a spacer layer directly on the quantum well layer, wherein the spacer layer comprises aluminum indium antimonide and is undoped; arranging source and drain contacts such that the quantum well layer and the spacer layer are between the source and drain contacts, wherein there is no delta doped layer directly adjacent to the spacer layer; Disposing a dielectric layer directly on the spacer layer; as well as A gate contact is disposed on the dielectric layer.

10. The method of claim 9, wherein the quantum well layer is disposed directly on the barrier layer, and the spacer layer is disposed directly on the quantum well layer.

11. The method of claim 10, wherein the barrier layer and the spacer layer are composed of aluminum indium antimonide.

12. The method of claim 11, wherein the QWFET is an enhancement mode device.

13. The method of claim 10, wherein the QWFET is an enhancement mode device.

14. The method of claim 9, wherein the barrier layer and the spacer layer are composed of aluminum indium antimonide.

15. The method of claim 14, wherein the QWFET is an enhancement mode device.

16. The method of claim 9, wherein the QWFET is an enhancement mode device.

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