DC-DC converter circuit

Abstract

A DC-to-DC converter circuit is provided. The DC-DC converter circuit is capable of generating a DC output voltage within a defined voltage range based on an input voltage. The DC-DC converter circuit may include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multilayer ceramic capacitor (MLCC). Notably, due to inherent DC bias instability, the MLCC may produce a variable capacitance within the defined voltage range, thereby endangering the stability of the DC-DC converter circuit. Therefore, a control circuit is configured to determine a configurable transconductance based on a feedback of the output voltage and accordingly control the compensator circuit to operate. Thus, it is possible to mitigate the impact of MLCC capacitance variation, thereby contributing to maintaining the stability of the DC-DC converter circuit.

Description

Technical Field

[0001] The technology of the present disclosure generally relates to a direct current (DC) - to - DC (DC - DC) converter circuit. Background Art

[0002] Mobile communication devices have become increasingly common in current society. The popularity of these mobile communication devices is partly driven by the many functions now realized on such devices. The improvement in processing power in such devices means that mobile communication devices have evolved from pure communication tools to complex mobile multimedia centers capable of enhancing the user experience.

[0003] Mobile communication devices are typically powered by a battery configured to supply a battery direct current (DC) voltage. Notably, a mobile communication device may include lower or higher voltage components and / or circuits configured to operate at a DC voltage lower or higher than the battery DC voltage. Accordingly, a mobile communication device may include a DC - DC converter circuit (e.g., a buck, boost, buck - boost regulator) for converting the battery DC voltage into a lower or higher DC voltage.

[0004] DC - DC converter circuits typically include an inductor - capacitor (LC) filter circuit configured to regulate a lower DC voltage within a selected bandwidth. Multilayer ceramic capacitors (MLCCs) are generally the capacitor of choice for LC filter circuits due to many attractive features such as low equivalent series resistance (ESR), good capacitance - to - volume ratio, relatively low leakage, non - polarity, and low cost of MLCCs. However, compared to other types of capacitors, MLCCs may also have drawbacks such as lower capacitance per volume and DC bias instability. In this regard, it may be desirable to employ MLCCs in a DC - DC converter circuit to take advantage of the attractive features while mitigating the side effects of MLCCs. Summary of the Invention

[0005] Aspects disclosed in the detailed implementation include a direct current to direct current (DC-DC) converter that can generate a DC output voltage within a defined voltage range (e.g., 3V - 24V) based on an input voltage. The DC-DC converter circuit may include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multilayer ceramic capacitor (MLCC). Notably, due to inherent DC bias instability, the MLCC may produce a variable capacitance within the defined voltage range, thereby endangering the stability of the DC-DC converter circuit. Therefore, a control circuit is provided to help maintain the stability of the DC-DC converter circuit. Specifically, the control circuit is configured to determine a configurable transconductance based on the feedback of the output voltage and control the operation of the compensator circuit based on the determined configurable transconductance. Thus, it is possible to mitigate the impact of MLCC capacitance variation, thereby helping to maintain the stability of the DC-DC converter circuit.

[0006] In one aspect, a DC-DC converter circuit is provided. The DC-DC converter circuit includes a modulator circuit configured to generate a pulse train based on an input waveform and a control voltage. The DC-DC converter circuit further includes an output filter circuit coupled to the modulator circuit and configured to generate an output voltage within a defined voltage range based on the input voltage and the pulse train. The DC-DC converter circuit further includes a compensator circuit having a configurable transconductance and configured to generate a control voltage and provide the control voltage to the modulator circuit. The DC-DC converter circuit further includes a control circuit coupled to the output filter circuit and the compensator circuit. The control circuit is configured to receive feedback of the output voltage from the output filter circuit. The control circuit is further configured to determine the configurable transconductance based on the feedback of the output voltage. The control circuit is further configured to configure the compensator circuit based on the determined configurable transconductance to generate the control voltage.

[0007] In another aspect, a DC-DC converter circuit is provided. The DC-DC converter circuit includes a modulator circuit configured to generate a pulse train based on an input waveform and a control voltage. The DC-DC converter circuit further includes an output filter circuit including an inductor-capacitor (LC) filter circuit formed based on an inductor and an MLCC. The output filter circuit is configured to generate an output voltage within a defined voltage range based on an input voltage and the pulse train. The DC-DC converter circuit further includes a compensator circuit having a configurable transconductance and configured to generate the control voltage and provide the control voltage to the modulator circuit. The DC-DC converter circuit further includes a control circuit coupled to the output filter circuit and the compensator circuit. The control circuit is configured to receive a feedback of the output voltage from the output filter circuit. The control circuit is further configured to determine the configurable transconductance based on the feedback of the output voltage. The control circuit is further configured to configure the compensator circuit to generate the control voltage based on the determined configurable transconductance.

[0008] Those skilled in the art will appreciate the scope of the present disclosure and recognize additional aspects thereof after reading the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings incorporated in and forming a part of this specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] FIG. 1A is a schematic diagram providing an exemplary illustration of a pair of complex conjugate poles plotted in the s-plane;

[0011] FIG. 1B is a schematic diagram providing an exemplary illustration of a real pole and a real zero plotted in the s-plane as in FIG. 1A;

[0012] FIG. 2A is a schematic diagram of a conventional direct current to direct current (DC-DC) converter circuit configured to generate an output voltage based on an input voltage;

[0013] FIG. 2B is a schematic diagram providing an exemplary illustration of an output filter circuit in the conventional DC-DC converter circuit of FIG. 2A;

[0014] FIG. 2C is a schematic diagram providing an exemplary illustration of the capacitance variation of a multilayer ceramic capacitor (MLCC) with respect to a bias voltage;

[0015] Figure 3A is a schematic diagram of an exemplary DC-DC converter circuit, such as a buck regulator circuit, configured to overcome instability issues associated with the conventional DC-DC converter circuit of FIG. 2A according to an embodiment of the present disclosure;

[0016] Figure 3B is provided in connection withFigure 3A Exemplary diagrams of input waveforms, control voltages, and pulses associated with a modulator circuit in a DC-DC converter circuit; and

[0017] Figure 3C provides Figure 3A configured to generate in a DC-DC converter circuit Figure 3B Schematic diagram of an exemplary VRAMP generation circuit for the input waveform in DETAILED DESCRIPTION

[0018] The embodiments set forth below represent the necessary information enabling those skilled in the art to practice the embodiments and show the best mode of practicing the embodiments. After reading the following description with reference to the drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0019] It should be understood that although terms such as first and second may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0020] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on the other element or directly extend onto the other element, or there may also be intermediate elements. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intermediate elements. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "above" or "extending above" another element, it can be directly above the other element or directly extend above the other element, or there may also be intermediate elements. In contrast, when an element is referred to as being "directly above" or "directly extending above" another element, there are no intermediate elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0021] In this document, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used to describe the relationship of one element, layer or region shown in the figure to another element, layer or region. It should be understood that these terms and those discussed above are intended to cover different orientations of the device in addition to the orientations depicted in the drawings.

[0022] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that when used herein, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Aspects disclosed in the detailed description include a direct current to direct current (DC-DC) converter circuit. The DC-DC converter circuit is capable of generating a DC output voltage within a defined voltage range (e.g., 3V - 24V) based on an input voltage. The DC-DC converter circuit may include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multilayer ceramic capacitor (MLCC). Notably, due to inherent DC bias instability, the MLCC may produce a variable capacitance within the defined voltage range, thus endangering the stability of the DC-DC converter circuit. Therefore, a control circuit is provided to help maintain the stability of the DC-DC converter circuit. Specifically, the control circuit is configured to determine a configurable transconductance based on feedback of the output voltage, and control the compensator circuit to operate based on the determined configurable transconductance. Thus, it is possible to mitigate the impact of MLCC capacitance variation, thereby helping to maintain the stability of the DC-DC converter circuit.

[0025] Before discussing the DC-DC converter circuit of the present disclosure, a brief overview of transfer functions is first provided with reference to FIGS. 1A and 1B to help define high-order transfer functions (e.g., second-order complex pole transfer functions) and first-order real pole / real zero transfer functions. Next, an overview of existing DC-DC converter circuits is provided with reference to FIGS. 2A-2C to help establish the operating context of the DC-DC converter circuit of the present disclosure. The discussion of specific exemplary aspects of the DC-DC converter circuit of the present disclosure begins below with reference to FIG. 3.

[0026] The transfer function of a system, which is typically denoted as H(s), can be represented by the following equation (Equation 1).

[0027]

[0028] In the above equation (Equation 1), N(s) and D(s) are simple polynomials that respectively define the zeros and poles of the transfer function H(s). More specifically, the zeros are the roots of the polynomial N(s) and can be determined by solving the equation N(s) = 0. In this regard, the order of the polynomial N(s) determines the number of zeros of the transfer function H(s). The zeros correspond to zero outputs of the transfer function H(s). When the polynomial N(s) represents a constant value, the polynomial N(s) is a zero-order polynomial, and when the polynomial N(s) is equal to 1 + b0s, the polynomial is a first-order polynomial.

[0029] In contrast, the poles are the roots of the polynomial D(s) and can be determined by solving the equation D(s) = 0. In this regard, the order of the polynomial D(s) determines the number of poles of the transfer function H(s). The poles correspond to infinite outputs of the transfer function H(s). When the polynomial D(s) represents a constant value, the polynomial D(s) is a zero-order polynomial, and when the polynomial is equal to 1 + a0s, the polynomial is a first-order polynomial. When the polynomial D(s) is equal to 1 + a0s + a1s 2 then, the polynomial D(s) becomes a second-order polynomial, and when the polynomial D(s) is equal to 1 + a0s + a1s 2 + a2s 3 then, the polynomial becomes a third-order polynomial, and so on. In this regard, when the polynomial D(s) is not a zero-order or first-order polynomial, the polynomial D(s) is a high-order polynomial. Thus, when the polynomial D(s) is a high-order polynomial, the transfer function H(s) becomes a high-order transfer function H(s). More specifically, when the polynomial D(s) is a second-order polynomial, the transfer function H(s) is hereinafter referred to as a second-order complex pole transfer function, and when the polynomial D(s) is a third-order polynomial, the transfer function H(s) is hereinafter referred to as a complex pole / real pole transfer function.

[0030] In one example, N(s) can be a zero-order polynomial and D(s) can be a second-order polynomial. Thus, the transfer function H(s) becomes a second-order transfer function with two poles. When the two poles are complex conjugate poles (e.g., damping factor < 1), the transfer function H(s) is hereinafter referred to as a second-order complex pole transfer function. In contrast, when the two poles are real poles (e.g., damping factor > 1), the transfer function H(s) is hereinafter referred to as a second-order real pole transfer function.

[0031] FIG. 1A is a graphical diagram providing an exemplary illustration of a pair of complex conjugate poles 10, 12 plotted in an s-plane 14. The s-plane 14 is a complex plane for plotting the Pierre-Simon Laplace (Laplace) transform. The s-plane 14 includes a real axis 16 and an imaginary axis 18 perpendicular to the real axis 16. The complex conjugate poles 10, 12, as plotted in the s-plane 14, have real parts 20 that are equal in magnitude and the same in sign. The complex conjugate poles 10, 12 have imaginary parts 22, 24, respectively. The imaginary parts 22, 24 are equal in magnitude but opposite in sign.

[0032] In another example, both N(s) and D(s) are first-order polynomials. Thus, the transfer function H(s) becomes a first-order transfer function with one pole and one zero. FIG. 1B is a graphical diagram providing an exemplary illustration of a real pole 26 and a real zero 28 plotted in the s-plane 14 as in FIG. 1A.

[0033] The real pole 26 and the real zero 28 are both located on the real axis 16. Although the real pole 26 as shown is farther from the imaginary axis 18 than the real zero 28, it is also possible that the real pole 26 is closer to the imaginary axis 18 than the real zero 28. In the case where both the real pole 26 and the real zero 28 are located on the real axis 16, the transfer function H(s) is hereinafter referred to as a first-order real pole / real zero transfer function.

[0034] In another example, N(s) can be a first-order polynomial with real poles / real zeros and D(S) can be a third-order polynomial with two complex poles and one real pole. In this regard, the transfer function H(s) can be referred to as a "second-order complex pole in series with a first-order real pole / real zero" transfer function.

[0035] FIG. 2A is configured to generate an output voltage V based on an input voltage V IN OUT ​Schematic diagram of an existing DC-DC converter circuit 30. The existing DC-DC converter circuit 30 includes a modulator circuit 32, an output filter circuit 34, and a compensator circuit 36. The output filter circuit 34 is coupled in series to the modulator circuit 32. The compensator circuit 36 is coupled between the modulator circuit 32 and the output filter circuit 34 to form a closed loop. The modulator circuit 32 is configured to generate a voltage having a voltage between zero voltage (0V) and the input voltage V IN At this point, the pulse train 38 is between 0V and the input voltage V according to the duty cycle. IN The duty cycle is equal to the pulse train 38 maintaining the input voltage V during the defined period. IN The total time under the condition is divided by the duration of the defined period. In this regard, the corresponding pulse width of each pulse in the pulse train 38 increases when the duty cycle increases and decreases when the duty cycle decreases.

[0036] The output filter circuit 34 is configured to generate an output voltage V OUT The compensator circuit 36 is configured to receive the output voltage V OUT The feedback and reference voltage V REF , the reference voltage represents the output voltage V OUT The compensator circuit 36 compares the output voltage V OUT The feedback and reference voltage V REF To determine the output voltage V OUT The feedback and reference voltage V REF Is there a voltage error between V ERR (V ERR =V OUT -V REF ). If the voltage error V ERR is not equal to zero, the compensator circuit 36 can control the voltage V CTRL is provided to the modulator circuit 32. In a non-limiting example, the control voltage V CTRL The duty cycle of the pulse train 38 can be changed, and thus the output voltage V OUT changes so that the output voltage V OUT With reference voltage V REF equal.

[0037] The output filter circuit 34 is configured to perform an averaging function to convert the pulse train 38 into an output voltage V OUT FIG. 2B is a schematic diagram providing an exemplary illustration of the output filter circuit 34 in the prior art DC-DC converter circuit 30 of FIG. 2A . Common elements between FIG. 2A and FIG. 2B are shown with common element numbers and will not be described repeatedly herein.

[0038] The output filter circuit 34 may include a driver stage circuit 40 (denoted as "driver"), a power stage switching circuit 42, and an LC filter circuit 44. The power stage switching circuit 42 includes a high-side switch HSW and a low-side switch LSW coupled in series between a node 46 configured to receive an input voltage V IN and ground GND. The driver stage circuit 40 is configured to receive a pulse train 38 and control the power stage switching circuit 42 based on the duty cycle of the pulse train 38 to couple the input voltage V IN to the LC filter circuit 44 or decouple the input voltage V IN from the LC filter circuit 44. In this regard, the duty cycle of the pulse train 38 causes the power stage switching circuit 42 to operate based on a switching frequency F sw .

[0039] The LC filter circuit 44 includes an inductor 48 having an inductance L0 and an MLCC 50 having a capacitance C0. It is noted that the MLCC 50 may have an inherent equivalent series resistance R ESR . The LC filter circuit 44 may be coupled to a load circuit represented by a load resistor R LOAD (e.g., a circuit that receives an output voltage V OUT ).

[0040] When the driver stage circuit 40 drives the power stage switching circuit 42 to close HSW and open LSW, the inductor 48 is coupled to the node 46 to receive a bias voltage V IN that may be slightly lower than the input voltage V SW (V SW = V IN minus the voltage drop across HSW). Thus, the bias voltage V SW causes current to flow from the node 46 through the inductor 48 to charge the MLCC 50 to the output voltage V OUT . In contrast, when the driver stage circuit 40 drives the power stage switching circuit 42 to open HSW and close LSW, the inductor 48 is coupled to ground GND. Thus, the MLCC 50 discharges, and current will flow from the MLCC 50 through the inductor 48 to ground GND. As a result, the LC filter circuit 44 resonates at a resonant frequency f0, as shown in the following equation (Equation 2).

[0041]

[0042] In this regard, the LC filter circuit 44 represents a two-pole transfer function and acts as a low-pass filter in the frequency domain to transfer the output voltage V OUT . As previously mentioned, one of the disadvantages of the MLCC 50 is DC bias instability, which means that when the bias voltage V SWWhen it changes, the capacitance C0 of the capacitor C0 may change. FIG. 2C is a diagrammatic view of an exemplary illustration providing the capacitance change of the MLCC 50 in FIG. 2B as a function of the bias voltage V SW and varying. As shown in FIG. 2C, when the bias voltage V SW increases, the capacitance C0 of the MLCC 50 decreases. In contrast, when the bias voltage V SW increases, the capacitance C0 of the MLCC 50 increases.

[0043] According to the above equation (Equation 2), when the capacitance C0 of the MLCC 50 changes, the resonant frequency f0 may be affected. As a result, the double poles of the LC filter circuit 44 may shift to the right toward the imaginary axis 18 in FIGS. 1A and 1B or even cross the imaginary axis, thereby risking destabilizing the existing DC-DC converter circuit 30. Although it is possible to replace the MLCC 50 with another type of capacitor having less DC bias instability, disadvantageously, this would mean sacrificing many attractive features of the MLCC 50. Therefore, it may be necessary to employ the MLCC 50 in the LC filter circuit 44 while mitigating the effects of the DC bias instability caused by the MLCC 50.

[0044] At this point, Figure 3AFIG. 5 is a schematic diagram of an exemplary DC - DC converter circuit 52 configured according to an embodiment of the present disclosure to overcome the instability problems in the existing DC - DC converter circuit 30 of FIG. 2A as discussed above. In the examples discussed below, the DC - DC converter circuit 52 may be a buck regulator circuit. It is noted that the DC - DC converter circuit 52 may also be a DC - DC boost regulator circuit or a DC - DC buck - boost circuit. It should also be understood that the operating principles discussed below may also be applied to other types of DC - DC converters. The DC - DC converter circuit 52 may be similar to the existing DC - DC converter circuit 30 in that the DC - DC converter circuit 52 also includes a modulator circuit 54, an output filter circuit 56, and a compensator circuit 58. And, the output filter circuit 56 includes an LC filter circuit 60 formed by an inductor 62 having an inductance L0 and an MLCC 64 having a capacitance C0. However, the DC - DC converter circuit 52 is different from the existing DC - DC converter circuit 30 in that the DC - DC converter circuit 52 further includes a control circuit 66. As discussed in detail below, the control circuit 66 may be configured to control the compensator circuit 58 to help mitigate the instability problems in the existing DC - DC converter circuit 30 as discussed above in FIGS. 2A - 2C. By including the control circuit 66 in the DC - DC converter circuit 52 to mitigate the instability problems, it is possible to realize many attractive features of the MLCC 64, thereby helping to reduce the cost and footprint of the DC - DC converter circuit 52.

[0045] The modulator circuit 54 includes a voltage comparator 68 configured to generate a pulse train 70 based on an input waveform V ramp and a control voltage V CTRL . As Figure 3B shown, the control voltage VCTRL may cause the duty cycle of the pulse train 70 to vary.

[0046] In this regard, Figure 3B FIG. 6 is a graphical diagram providing an exemplary illustration of the input waveform V ramp , the control voltage V CTRL , and the pulse train 70. As Figure 3B shown, when the control voltage V CTRL increases from V1 to V2, the pulse train 70 changes from a narrower pulse width W1 to a wider pulse width W2. Thus, the pulse train 70 will transition from a lower duty cycle to a higher duty cycle.

[0047] Referring to Figure 3A , the modulator circuit 54 may include a VRAMP generation circuit 72 configured to generate the input waveform V ramp . Figure 3C FIG. 7 is provided Figure 3Aconfigured to generate an input waveform V in the DC-DC converter circuit 52 ramp Schematic diagram of an exemplary illustration of the VRAMP generation circuit 72.

[0048] In a non-limiting example, the VRAMP generation circuit 72 includes a RAMPGEN circuit 74, a resistor R base and a capacitor C ramp . As will be discussed later, the resistor R base and the capacitor C ramp are among many parameters that define the transfer function H(s) of the DC-DC converter circuit 52.

[0049] Return reference Figure 3A , the output filter circuit 56 includes a power stage switch circuit 76 and a driver stage circuit 78 (denoted as “driver”). The output filter circuit 56 is configured to generate an output voltage V within a defined voltage range (e.g., ≥3V and ≤24V) based on the input voltage V IN and the pulse train 70. OUT The power stage switch circuit 76 and the driver stage circuit 78 are functionally equivalent to the driver stage circuit 40 and the power stage switch circuit 42 in the existing DC-DC converter circuit 30, respectively.

[0050] The output filter circuit 56 can be coupled to a voltage divider 80 configured to generate a feedback (hereinafter referred to as “V OUT ”) of the output voltage V OUT-FB . The voltage divider 80 may include a top resistor R OUT configured to divide the output voltage V OUT-FB to generate V OUT-FB (V OUT =V bot *R top / (R bot +R top )) and a bottom resistor R bot .

[0051] The compensator circuit 58 includes an error amplifier 82 (denoted as “EA”) and a circuit 84. The error amplifier 82 is configured to receive a reference voltage V REF and V OUT-FB , and the reference voltage may represent a scaled target of the output voltage V OUT . In a non-limiting example, the error amplifier 82 is a transconductance amplifier with a configurable transconductance G m . In this regard, the error amplifier 82 generates a control current I REF and V OUT-FB based on the reference voltages V CTRL (I CTRL =Gm *(V OUT -FB-V REF ))。

[0052] The circuit 84 may include a resistor R coupled in parallel to the capacitor C comp2 。 oea The circuit 84 may also include another resistor R coupled in series to another capacitor C comp 。 comp The circuit 84 may be configured to generate a control voltage V CTRL based on a control current I CTRL and provide the control voltage V CTRL to the voltage comparator 68. As discussed earlier, the control voltage V CTRL may change the duty cycle of the pulse train 70 and thus change the output voltage V OUT 。

[0053] In a non-limiting example, the transfer function H(S) of the DC-DC converter circuit 52 can be expressed by the equation (Equation 3).

[0054]

[0055] By solving the equation (Equation 3) to be equal to one (1) at the cut-off frequency F C , it is possible to express the cut-off frequency F C with the following equation (Equation 4).

[0056]

[0057] According to the above equation (Equation 4), the cut-off frequency F C is inversely proportional to the capacitance C0 of the MLCC 64. Therefore, if the capacitance C0 changes due to the inherent DC bias instability of the MLCC 64, the cut-off frequency FC may change accordingly, making the DC-DC converter circuit 52 unstable. Therefore, in order to maintain the stability of the DC-DC converter circuit 52, it may be necessary to keep the cut-off frequency F C relatively stable regardless of how the capacitance C0 of the MLCC 64 changes.

[0058] Fortunately, the equation (Equation 4) reveals that it is possible to turn multiple knobs to help restore the stability of the cut-off frequency F C . For example, when the capacitance C0 decreases due to an increase in the bias voltage, it is possible to increase the resistor R comp , the resistor R ramp and / or the capacitor C ramp to help maintain the stability of the cut-off frequency F C . However, in order to reduce complexity, cost, and / or footprint, it may be necessary to keep the resistor Rcomp , resistor R ramp and capacitor C ramp are fixed in the DC - DC converter circuit 52.

[0059] At this point, in a preferred embodiment, the control circuit 66 is configured to adjust the configurable transconductance G of the error amplifier 82 m to help maintain a relatively stable cut - off frequency F in the face of changes in the capacitance C0 of the MLCC 64 C Specifically, the control circuit 66 can decrease the configurable transconductance G when the capacitance C0 of the MLCC 64 increases m . In contrast, the control circuit 66 can increase the configurable transconductance G when the capacitance C0 of the MLCC 64 decreases m .

[0060] In a non - limiting example, the control circuit 66 can include a look - up table (LUT), as shown below, configured to associate a plurality of configurable transconductances with a plurality of predefined ranges of the output voltage V OUT .

[0061] Configurable transconductance LUT

[0062] Binary word <![CDATA[V OUT range]]> Transconductance 00 <![CDATA[3V ≤ V OUT <8V]]> <![CDATA[1.00G m > 01 <![CDATA[8V≤V OUT <11.2V]]> <![CDATA[0.75G m > 10 <![CDATA[11.2V≤V OUT <16V]]> <![CDATA[0.50G m > 11 <![CDATA[16V ≤ V OUT ≤ 24V]]> <![CDATA[0.25G m >

[0063] The control circuit 66 can receive a binary word representing a predefined range of the output voltage V OUT . For example, the binary word "00" represents a range of the output voltage V between 3V and 8V OUT , the binary word "01" represents a range of the output voltage V between 8V and 11.2V OUT , the binary word "10" represents a range of the output voltage V between 11.2V and 16V OUT , and the binary word "11" represents a range of the output voltage V between 16V and 24V OUT . It should be understood that the binary word can contain more digits to more finely represent the range of the output voltage V OUT .

[0064] Thus, based on the binary word, the control circuit 66 can retrieve the corresponding configurable transconductance G m . Thus, the control circuit 66 can configure the error amplifier 82 based on the determined configurable transconductance G m to generate a control current I CTRL . Additionally, the control circuit can also be configured to provide a reference voltage V REF to the error amplifier 82.

[0065] Although it may be preferred to adjust only the configurable transconductance G based on V OUT-FB m ​to maintain the stability of the DC-DC converter circuit 52, it should be understood that the DC-DC converter circuit 52 can also be configured to adjust the configurable transconductance G in combination with the adjustment resistor R comp , resistor R ramp and / or capacitor C ramp and adjust the configurable transconductance G m . In addition, as shown in the above equation (Equation 4), it is also possible to adjust V m , resistor R comp , resistor R ramp and / or capacitor C ramp and adjust the cut-off frequency F by combining or independently of adjusting the configurable transconductance G OUT-FB and / or inductor L0 C .

[0066] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A DC-DC converter circuit, comprising: A modulator circuit configured to generate a pulse train based on an input waveform and a control voltage, the control voltage setting a duty cycle of the pulse train; An output filter circuit coupled to the modulator circuit and configured to generate a bias voltage based on an input voltage and the duty cycle of the pulse train to cause current to flow through a multilayer ceramic capacitor (MLCC), thereby generating an output voltage within a predefined voltage range; A compensator circuit having a configurable transconductance and configured to: Generate a control current according to the configurable transconductance; And Generate the control voltage based on the control current and provide the control voltage to the modulator circuit, thereby setting the duty cycle of the pulse train; And A control circuit coupled to the output filter circuit and the compensator circuit and configured to: Receive an indication of the predefined voltage range of the output voltage; Determine the configurable transconductance based on the predefined voltage range of the output voltage; And Configure the compensator circuit to generate the control current based on the determined configurable transconductance, thereby reducing instability of the output voltage caused by fluctuations in the capacitance value of the MLCC as a result of changes in the bias voltage.

2. The DC-DC converter circuit according to claim 1, wherein the control circuit is further configured to: Reduce the configurable transconductance of the compensator circuit when the capacitance value of the MLCC increases; and Increase the configurable transconductance of the compensator circuit when the capacitance value of the MLCC decreases.

3. The DC-DC converter circuit according to claim 1, wherein the control circuit is further configured to retrieve the configurable transconductance from a look-up table (LUT), the look-up table being configured to associate a plurality of configurable transconductances with a plurality of predefined ranges of the output voltage respectively.

4. The DC-DC converter circuit according to claim 3, wherein the control circuit is further configured to: Receive a binary word indicating the predefined voltage range of the output voltage among the plurality of predefined ranges of the output voltage; and Retrieve from the LUT the configurable transconductance corresponding to the predefined voltage range of the output voltage represented by the binary word.

5. The DC-DC converter circuit according to claim 1, wherein the compensator circuit comprises: An error amplifier having the configurable transconductance and configured to generate the control current based on an indication of the predefined voltage range of the output voltage and a reference voltage representing a scaled target of the output voltage; And A circuit configured to generate the control voltage based on the control current and provide the control voltage to the modulator circuit.

6. The DC-DC converter circuit according to claim 5, wherein the control circuit is further configured to control the error amplifier to generate the control current based on the determined configurable transconductance.

7. The DC-DC converter circuit according to claim 6, wherein the control circuit is further configured to: When the output voltage is greater than or equal to 3V and less than 8V, the error amplifier is controlled based on a first transconductance to generate the control current; When the output voltage is greater than or equal to 8V and less than 11.2V, the error amplifier is controlled based on a second transconductance that is 25% lower than the first transconductance to generate the control current; When the output voltage is greater than or equal to 11.2V and less than 16V, the error amplifier is controlled based on a third transconductance that is 25% lower than the second transconductance to generate the control current; and When the output voltage is greater than or equal to 16V and less than or equal to 24V, the error amplifier is controlled based on a fourth transconductance that is 25% lower than the third transconductance to generate the control current.

8. The DC-DC converter circuit according to claim 6, wherein the control circuit is further configured to generate the reference voltage and provide the reference voltage to the error amplifier.

9. The DC-DC converter circuit according to claim 5, wherein the output filter circuit includes: An LC filter circuit configured to regulate the output voltage to the predefined voltage range based on the bias voltage; A power stage switching circuit configured to switch between the input voltage and ground to thereby set the bias voltage of the LC filter circuit; And A driver stage circuit configured to switch the power stage switching circuit between the input voltage and ground based on the duty cycle of the pulse train.

10. The DC-DC converter circuit according to claim 9, wherein the compensator circuit is further configured to change the control voltage such that the modulator circuit changes the duty cycle of the pulse train.

11. The DC-DC converter circuit according to claim 9, wherein the LC filter circuit includes a multilayer ceramic capacitor MLCC having a capacitance value inversely proportional to the output voltage.

12. The DC-DC converter circuit according to claim 11, corresponding to a cut-off frequency proportional to the configurable transconductance of the error amplifier and inversely proportional to the capacitance value of the MLCC.

13. The DC-DC converter circuit according to claim 5, wherein the error amplifier is further configured to: Increase the control current in response to an increase in the difference between the output voltage and the reference voltage; and Decrease the control current in response to a decrease in the difference between the output voltage and the reference voltage.

14. A DC-DC converter circuit, comprising: A modulator circuit configured to generate a pulse train based on an input waveform and a control voltage, the control voltage setting the duty cycle of the pulse train; An output filter circuit including an LC filter circuit formed based on an inductor and a multilayer ceramic capacitor MLCC, the output filter circuit being configured to generate a bias voltage based on the input voltage and the duty cycle of the pulse train such that current flows through the MLCC, thereby generating an output voltage within a predefined voltage range; A compensator circuit having a configurable transconductance and configured to: Generate a control current according to the configurable transconductance; and Generate the control voltage based on the control current and provide the control voltage to the modulator circuit to set the duty cycle of the pulse train; and A control circuit coupled to the output filter circuit and the compensator circuit and configured to: Receive an indication of the predefined voltage range of the output voltage; Determine the configurable transconductance based on the predefined voltage range of the output voltage; and Configure the compensator circuit to generate the control current based on the determined configurable transconductance, thereby reducing the instability of the output voltage caused by fluctuations in the capacitance value of the MLCC as a result of the change in the bias voltage.

15. The DC-DC converter circuit according to claim 14, wherein the control circuit is further configured to: Reduce the configurable transconductance of the compensator circuit when the capacitance value of the MLCC increases; and Increase the configurable transconductance of the compensator circuit when the capacitance value of the MLCC decreases.

16. The DC-DC converter circuit according to claim 14, wherein the control circuit is further configured to retrieve the configurable transconductance from a look-up table LUT, the look-up table being configured to associate a plurality of configurable transconductances with a plurality of predefined ranges of the output voltage respectively.

17. The DC-DC converter circuit according to claim 14, wherein the compensator circuit includes: An error amplifier having the configurable transconductance and configured to generate the control current based on an indication of the predefined voltage range of the output voltage and a reference voltage representing a scaled target of the output voltage; and A circuit configured to generate the control voltage based on the control current and provide the control voltage to the modulator circuit.

18. The DC-DC converter circuit according to claim 17, wherein the output filter circuit includes: An LC filter circuit configured to regulate the output voltage to the predefined voltage range based on the bias voltage; A power stage switch circuit configured to switch between the input voltage and ground to set the bias voltage of the LC filter circuit; and A driver stage circuit configured to switch the power stage switch circuit between the input voltage and ground based on the duty cycle of the pulse train.

19. The DC-DC converter circuit according to claim 18, wherein the MLCC has a capacitance value inversely proportional to the output voltage.

20. The DC-DC converter circuit according to claim 19, corresponding to a cut-off frequency proportional to the configurable transconductance of the error amplifier and inversely proportional to the capacitance value of the MLCC.

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