Solid-state imaging element

Abstract

The present invention provides a solid-state imaging element capable of preventing image quality degradation and reducing power consumption and AD conversion time, comprising a first comparator and a second comparator. The first and second comparators respectively comprise: a first and a second input transistor, which outputs a first and a second voltage corresponding to an input voltage from a first pixel input to the source of the input transistor based on a first and a third voltage difference between the first and the second reference voltages input to the gate of the input transistor from the drain of the input transistor; and a first and a second output transistor, which outputs a comparison result of the input voltage and the first and the second reference voltages from the drain of the output transistor based on a second and a fourth voltage difference between the input voltage input to the source of the output transistor and the first and the second voltages input to the gate of the output transistor.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element. Background Art

[0002] In solid-state imaging elements, a single-slope type ADC (Analog to Digital Converter) has been used for AD (Analog to Digital) conversion. The single-slope ADC includes a comparator and a counter. The comparator compares a pixel signal with a reference signal and outputs the comparison result to the counter. The counter measures the period from when the comparison between the pixel signal and the reference signal starts to when the output from the comparator is reversed. The solid-state imaging element detects the level of the pixel signal based on the period measured by the counter.

[0003] [Citation list]

[0004] [Patent Document]

[0005] [Patent Document 1]: Japanese Patent Laid-Open No. 2013-026734

[0006] [Patent Document 2]: Japanese Patent Laid-Open No. 2017-200140 Summary of the invention

[0007] [Technical issues to be solved]

[0008] In the above-mentioned solid-state imaging element, it is currently being considered to reduce power consumption by using a common power supply shared by the comparator and the pixel circuit. However, in this case, the inversion time of the comparison result sometimes deviates from the ideal time when the reference signal and the pixel signal become approximately equal. Due to such an error in the inversion time, an error or nonlinearity will occur in the digital signal generated by AD conversion of the pixel signal, resulting in a problem of image quality degradation of the image data.

[0009] In addition, in the case where the comparator uses a single gain to perform AD conversion of a pixel signal, when the operating frequency of the counter is reduced and the number of counts is reduced in order to reduce power consumption, the grayscale of the dark area of ​​the image data is rough. In this case, the image quality is deteriorated. On the other hand, when the operating frequency of the counter is increased and the number of counts is increased, the image quality of the dark area of ​​the image data is improved. However, the power consumption of the counter increases, and the AD conversion takes a long time. As described above, in the case of using a single gain to perform AD conversion of a pixel signal, a problem of a trade-off relationship between image quality, power consumption, and AD conversion time is caused.

[0010] The present technology has been developed in view of the above situation. An object of the present technology is to provide a solid-state imaging element that can reduce power consumption and AD conversion time while suppressing image quality degradation.

[0011] [Technical solution to the problem]

[0012] A solid-state imaging element according to one aspect of the present invention includes a first comparator and a second comparator. The first comparator includes a first input transistor and a first output transistor. The first input transistor outputs a first voltage corresponding to the input voltage from the drain of the first input transistor based on a first voltage difference between an input voltage from a first pixel input to the source of the first input transistor and a first reference voltage input to the gate of the first input transistor. The first output transistor outputs a comparison result of the input voltage and the first reference voltage from the drain of the first output transistor based on a second voltage difference between the input voltage input to the source of the first output transistor and the first voltage input to the gate of the first output transistor. The second comparator includes a second input transistor and a second output transistor. The second input transistor outputs a second voltage corresponding to the input voltage from the drain of the second input transistor based on a third voltage difference between the input voltage input to the source of the second input transistor and the second reference voltage input to the gate of the second input transistor. The second output transistor outputs a comparison result between the input voltage and the second reference voltage from a drain of the second output transistor based on a fourth voltage difference between the input voltage input to the source of the second output transistor and the second voltage input to the gate of the second output transistor.

[0013] The first comparator may further include: a first current source connected to the drain of the first input transistor; a first clamp transistor disposed between the source and the drain of the first input transistor; a second current source connected to the drain of the first output transistor; and a second clamp transistor disposed between the source and the drain of the first output transistor. The second comparator may further include: a third current source connected to the drain of the second input transistor; a third clamp transistor disposed between the source and the drain of the second input transistor; a fourth current source connected to the drain of the second output transistor; and a fourth clamp transistor disposed between the source and the drain of the second output transistor. Moreover, in each of the first clamp transistor to the fourth clamp transistor, the gate and the drain may be short-circuited to each other.

[0014] The first comparator may further include: a first switch disposed between the gate and drain of the first input transistor; and a second switch disposed between the gate and drain of the first output transistor. The second comparator may further include: a third switch disposed between the gate and drain of the second input transistor; and a fourth switch disposed between the gate and drain of the second output transistor.

[0015] The first reference voltage and the second reference voltage change over time with slopes different from each other. The solid-state imaging element may further include a first counter and a second counter. In the first counter, a comparison result from the first comparator is received, a first period from the beginning of the slope of the first reference voltage to the inversion of the comparison result received from the first comparator is counted, and a first digital signal is output based on the count value of the first period. In the second counter, a comparison result from the second comparator is received, a second period from the beginning of the slope of the second reference voltage to the inversion of the comparison result received from the second comparator is counted, and a second digital signal is output based on the count value of the second period. The first counter and the second counter may operate almost simultaneously.

[0016] The slope of the second reference voltage may be steeper than that of the first reference voltage, and the first counter and the second counter may measure the first period and the second period, respectively, by using clock signals having substantially the same frequency.

[0017] The solid-state image pickup element may further include: a selection section that selects the first digital signal or the second digital signal to synthesize an image.

[0018] The solid-state imaging element may further include: a pixel signal line connected between the first pixel and the first comparator and between the first pixel and the second comparator. The current flowing through the pixel signal line may be the sum of the currents flowing through the first current source to the fourth current source.

[0019] When the input voltage and the first reference voltage become approximately equal, the first input transistor may output the first voltage from the drain of the first input transistor. The first output transistor may output a signal indicating whether the difference between the input voltage and the first voltage exceeds the threshold voltage of the first output transistor as a comparison result of the comparison between the input voltage and the first reference voltage. When the input voltage and the second reference voltage become approximately equal, the second input transistor may output the second voltage from the drain of the second input transistor. The second output transistor may output a signal indicating whether the difference between the input voltage and the second voltage exceeds the threshold voltage of the second output transistor as a comparison result of the comparison between the input voltage and the second reference voltage.

[0020] The solid-state imaging element may further include: a first reference voltage supply unit, which supplies the first reference voltage; a first automatic zeroing capacitor, which is arranged between the gate of the first input transistor and the first reference voltage supply unit; a first buffer, which is arranged between the first reference voltage supply unit and the first automatic zeroing capacitor; a second reference voltage supply unit, which supplies the second reference voltage; a second automatic zeroing capacitor, which is arranged between the gate of the second input transistor and the second reference voltage supply unit; and a second buffer, which is arranged between the second reference voltage supply unit and the second automatic zeroing capacitor.

[0021] Each of the first input transistor, the second input transistor, the first output transistor and the second output transistor may be a P-type transistor.

[0022] Each of the first to fourth clamp transistors is a P-type transistor that short-circuits a gate and a drain to each other. The solid-state imaging element may further include: a fifth to eighth clamp transistor, which are connected in parallel with the first to fourth clamp transistors, respectively, and each of which is composed of an N-type transistor.

[0023] The first current source to the fourth current source may respectively include: first current source transistors to fourth current source transistors, which are respectively arranged between the drains of the first input transistor, the first output transistor, the second input transistor and the second output transistor and a predetermined reference terminal; first capacitors to fourth capacitors, which are respectively connected between the gates of the first current source transistor to the fourth current source transistor and the reference terminal; and first sampling and holding switches to fourth sampling and holding switches, which are respectively connected to the gates of the first current source transistor to the fourth current source transistor.

[0024] The solid-state imaging element may further include: a first logic gate connected to a drain of the first output transistor; and a second logic gate connected to a drain of the second output transistor.

[0025] The solid-state imaging element may further include: a pixel signal line connected between the first pixel and the first comparator and between the first pixel and the second comparator; and a fifth current source connected to the pixel signal line.

[0026] The solid-state imaging element may further include: a fifth capacitor, which is arranged between the drain of the first input transistor and the gate of the first output transistor; a fifth switch, which is arranged between the gate and the drain of the first output transistor; a sixth capacitor, which is arranged between the drain of the second input transistor and the gate of the second output transistor; and a sixth switch, which is arranged between the gate and the drain of the second output transistor.

[0027] The solid-state imaging element may include: a first buffer transistor connected between a power supply and a source of the first output transistor, a gate of the first buffer transistor being connected to the source of the first input transistor; and a second buffer transistor connected between the power supply and the source of the second output transistor, a gate of the second buffer transistor being connected to the source of the second input transistor.

[0028] The solid-state imaging element may also include: a common reference voltage supply unit that supplies a common reference voltage; a first auto-zero capacitor that is disposed between the gate of the first input transistor and the common reference voltage supply unit; a voltage-dividing capacitor that is connected between the gate of the first input transistor and a predetermined reference terminal; and a second auto-zero capacitor that is disposed between the gate of the second input transistor and the common reference voltage supply unit. In addition, the first auto-zero capacitor and the voltage-dividing capacitor may divide the common reference voltage, and transmit the divided common reference voltage as the first reference voltage to the gate of the first input transistor. Furthermore, the second auto-zero capacitor may transmit the common reference voltage as the second reference voltage to the gate of the second input transistor.

[0029] The selection section may include: a digital comparator that compares one or both of the first digital signal and the second digital signal with a threshold; a register that stores the threshold; and a multiplexer that selects the first digital signal or the second digital signal based on a comparison result received from the digital comparator, and outputs the selected digital signal as a pixel signal of the first pixel together with the comparison result.

[0030] The slope of the second reference voltage may be steeper than the slope of the first reference voltage. When one or both of the first digital signal and the second digital signal are lower than the threshold value, the multiplexer may select the first digital signal. When one or both of the first digital signal and the second digital signal are higher than the threshold value, the multiplexer may select the second digital signal. In addition, the solid-state imaging element may further include: a calculation unit that converts the first digital signal based on the ratio of the slope of the first reference voltage to the slope of the second reference voltage.

[0031] The solid-state imaging element may include a third comparator. The third comparator includes a third input transistor. The third input transistor outputs a third voltage corresponding to the input voltage from the drain of the third input transistor based on a fifth voltage difference between the input voltage input to the source of the third input transistor and a third reference voltage input to the gate of the third input transistor.

[0032] The third comparator further includes a third output transistor that outputs a comparison result of the input voltage and the third reference voltage from a drain of the third output transistor based on a sixth voltage difference between the input voltage input to the source of the third output transistor and the third voltage input to the gate of the third output transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 : is a block diagram showing one configuration example of an image pickup device according to a first embodiment of the present technology.

[0034] Figure 2 is a block diagram showing one configuration example of a solid-state image pickup element according to a first embodiment of the present technology.

[0035] Figure 3 : is a conceptual diagram showing an example of a solid-state imaging element formed by stacking a semiconductor chip of a pixel array section and a semiconductor chip of a peripheral circuit section.

[0036] Figure 4 is a circuit diagram showing one configuration example of a pixel circuit according to the first embodiment of the present technology.

[0037] Figure 5 : is a block diagram showing one configuration example of a column signal processing section according to the first embodiment of the present technology.

[0038] Figure 6 is a circuit diagram showing one configuration example of ADC1 and ADC2 according to the first embodiment of the present technology.

[0039] Figure 7 is a circuit diagram showing one example of the internal configuration of the current source of the present technology.

[0040] Figure 8 is a timing chart presenting one example of the operation of the comparator according to the first embodiment of the present technology.

[0041] Fig. 9 is a timing chart presenting one example of the operation of the comparator according to the first embodiment of the present technology.

[0042] Fig.10 : is a graph presenting one example of the relationship between the input voltage and the output value of each of ADC1 and ADC2 according to the present invention.

[0043] Fig.11 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to the second embodiment of the present technology.

[0044] Fig.12 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to the third embodiment of the present technology.

[0045] Fig.13 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a fourth embodiment of the present technology.

[0046] Fig.14 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a fifth embodiment of the present technology.

[0047] Fig.15 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a sixth embodiment of the present technology.

[0048] Fig.16 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a seventh embodiment of the present technology.

[0049] Fig.17 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to an eighth embodiment of the present technology.

[0050] Fig.18 is a circuit diagram showing a configuration example of a selection section according to a ninth embodiment of the present technology.

[0051] Fig.19 is a circuit diagram showing a configuration example of a solid-state image pickup element according to a tenth embodiment of the present technology.

[0052] Fig. 20: is a graph showing an example of the relationship between the input voltage and the output value of each of ADC1 , ADC2 , and ADCm according to the tenth embodiment of the present invention.

[0053] Fig.21 is a circuit diagram showing a configuration example of an ADC and peripheral circuits according to an eleventh embodiment of the present invention.

[0054] Fig. 22 is a timing chart presenting an operation example of the ADC according to the eleventh embodiment of the present invention.

[0055] Fig.23 is a circuit diagram showing a configuration example of an ADC and peripheral circuits according to a twelfth embodiment of the present invention.

[0056] Fig.24 is a timing chart presenting an operation example of the ADC according to the twelfth embodiment of the present invention.

[0057] Fig.25 : is a circuit diagram showing a configuration example of ADC1 , ADC2 , and peripheral circuits according to Modification 1 of the present invention.

[0058] Fig.26 is a circuit diagram showing a configuration example of an ADC and peripheral circuits according to Modification 2 of the present invention.

[0059] Fig.27A It is a schematic diagram showing the layout arrangement of ADC1 and ADC2 of the present invention.

[0060] Fig.27B It is a schematic diagram showing the layout arrangement of ADC1 and ADC2 of the present invention.

[0061] Fig.27C It is a schematic diagram showing the layout arrangement of ADC1 and ADC2 of the present invention.

[0062] Fig.28A Schematic diagram showing the layout arrangement of the solid-state imaging element of the present invention.

[0063] Fig.28B Schematic diagram showing the layout arrangement of the solid-state imaging element of the present invention.

[0064] Fig.29 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0065] Fig.30 It is a diagram for assisting in explaining an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0066] Specific embodiments to which the present technology is applicable will be described in detail below with reference to the accompanying drawings. The accompanying drawings are merely schematic diagrams or conceptual diagrams. The proportions of the various components are not necessarily consistent with the actual proportions. In the specification and the accompanying drawings, elements similar to those already described with reference to the accompanying drawings will be given the same reference numerals, and detailed descriptions of these elements will be appropriately omitted.

[0067] (First embodiment)

[0068] [Configuration Example of Image Capture Device]

[0069] Figure 1 1 is a block diagram showing a configuration example of an image pickup device 100 according to a first embodiment of the present technology. The image pickup device 100 is a device for picking up an image of a subject and generating image data of the subject, and includes an optical section 110, a solid-state image pickup element 200, and a DSP (digital signal processing) circuit 120. The image pickup device 100 also includes a display section 130, an operation section 140, a bus 150, a frame memory 160, a storage section 170, and a power supply section 180. It is assumed that the image pickup device 100 is a camera mounted on a smartphone, a car-mounted camera, or the like.

[0070] The optical section 110 collects light from a subject and guides the collected light to the solid-state imaging element 200 . The solid-state imaging element 200 generates image data by photoelectric conversion. The solid-state imaging element 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .

[0071] The DSP circuit 120 performs predetermined signal processing on the image data. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150.

[0072] The display section 130 is used to display image data. For example, it is assumed that the display section 130 is a liquid crystal panel or an organic EL (Electro Luminescence) panel. The operation section 140 generates an operation signal according to an operation performed by a user.

[0073] The bus 150 is a common path provided for data exchange among the optical section 110 , the solid-state imaging element 200 , the DSP circuit 120 , the display section 130 , the operation section 140 , the frame memory 160 , the storage section 170 , and the power supply section 180 .

[0074] The frame memory 160 is used to hold image data. The storage section 170 is used to store various types of data such as image data. The power supply section 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display section 130, and the like.

[0075] [Configuration Example of Solid-State Image Pickup Element]

[0076] Figure 2 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 210, a timing control section 220, DACs (Digital to Analog Converters) 231 and 232, a pixel array section 240, a column signal processing section 260, and a horizontal scanning circuit 270.

[0077] A plurality of pixel circuits 250 are arranged in a two-dimensional grid on the pixel array section 240. In the following description, a set of pixel circuits 250 arranged in a predetermined horizontal direction is referred to as a "row", and a set of pixel circuits 250 arranged in a direction perpendicular to the row is referred to as a "column".

[0078] The vertical scanning circuit 210 sequentially drives each row to obtain outputs from the pixel circuit 250 .

[0079] The timing control section 220 controls the operation timing of each of the vertical scanning circuit 210, DACs 231 and 232, the column signal processing section 260, and the horizontal scanning circuit 270 in synchronization with the vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal for indicating imaging timing and having a predetermined frequency (eg, 60 Hz).

[0080] DACs 231 and 232 generate a first reference signal and a second reference signal by DA (Digital to Analog) conversion, respectively. For example, each of the first and second reference signals includes a ramp signal having a sawtooth shape. DACs 231 and 232 provide the first and second reference signals to the column signal processing unit 260, respectively. The first and second reference signals are signals that allow voltages to vary over time with slopes that are different from each other, and are used by the column signal processing unit 260 to detect pixel signals with different gains. Note that each of DACs 231 and 232 is an example of a reference signal supply unit described in the claims.

[0081] Each of the pixel circuits 250 generates an analog pixel signal through photoelectric conversion, and supplies the generated analog pixel signal to the column signal processing section 260 .

[0082] The column signal processing section 260 performs signal processing such as AD conversion processing and CDS (Correlated Double Sampling) processing on the pixel signals column by column and supplies image data including the processed digital signals to the DSP circuit 120 via the signal line 209 .

[0083] The horizontal scanning circuit 270 controls the column signal processing section 260 to cause the column signal processing section 260 to sequentially output digital signals.

[0084] Notice, Figure 2 The solid-state imaging element 200 shown may include one semiconductor chip as a whole or may include a plurality of semiconductor chips. In the case where the solid-state imaging element 200 includes a plurality of semiconductor chips, the semiconductor chips 511 and 512 may be formed separately to be provided with the pixel array section 240 and the peripheral circuit section 15 other than the pixel array section 240, respectively, and the semiconductor chip 511 for forming the pixel array section 240 and the semiconductor chip 512 for forming the peripheral circuit section 15 may be stacked.

[0085] For example, Figure 3 2 is a conceptual diagram showing an example of a solid-state imaging element 200 manufactured by stacking a semiconductor chip 511 for forming a pixel array section 240 and a semiconductor chip 512 for forming a peripheral circuit section 15. Figure 3 As shown, the solid-state imaging element 200 includes two semiconductor chips, ie, semiconductor chips 511 and 512, which are stacked on each other.

[0086] The number of stacked semiconductor chips may be more than three. The semiconductor chip 511 includes a pixel array unit 240 formed on a semiconductor substrate. The semiconductor chip 512 includes a peripheral circuit unit 15 formed on another semiconductor substrate. For example, the individual pixels of the pixel array unit 240 of the semiconductor chip 511 and the elements of the peripheral circuit unit 15 of the semiconductor chip 512 can be electrically connected to each other using through electrodes such as TSV (Through Silicon Via) formed in the VIA (conductive via) area 513 and the VIA (conductive via) area 514. In addition, the two semiconductor chips can be bonded to each other (Cu-Cu bonding) in such a manner that the wiring in the semiconductor chip 511 for forming the pixel array unit 240 and the wiring in the semiconductor chip 512 for forming the peripheral circuit unit 15 are in contact with each other. In addition, Figure 2 A part of the pixel array section 240 and a part of the peripheral circuit section 15 shown may also be configured by one semiconductor chip, and the other parts may be configured by another semiconductor chip.

[0087] [Configuration Example of Pixel Circuit]

[0088] Figure 4 2 is a circuit diagram showing a configuration example of a pixel circuit 250 according to the first embodiment of the present technology. The pixel circuit 250 includes a photoelectric conversion element 251, a transfer transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256. In addition, vertical signal lines VSL are wired on the pixel array section 240 column by column, and each extends in the vertical direction.

[0089] The photoelectric conversion element 251 performs photoelectric conversion on incident light to generate electric charges. The transfer transistor 252 transfers the electric charges from the photoelectric conversion element 251 to the floating diffusion layer 254 according to the drive signal TRG received from the vertical scanning circuit 210 .

[0090] The reset transistor 253 takes out electric charge from the floating diffusion layer 254 and initializes it according to the driving signal RST received from the vertical scanning circuit 210 .

[0091] The floating diffusion layer 254 accumulates charges and generates a voltage corresponding to the amount of the charges. The amplifier transistor 255 amplifies the voltage of the floating diffusion layer 254.

[0092] The selection transistor 256 outputs a signal of an amplified voltage as a pixel signal to the column signal processing unit 260 via the vertical signal line VSL in accordance with the drive signal SEL received from the vertical scanning circuit 210 .

[0093] Note that the pixel circuit 250 may be a circuit different from that shown in the figure as long as the pixel circuit 250 can generate a pixel signal through photoelectric conversion.

[0094] [Configuration Example of Column Signal Processing Section]

[0095] Figure 5 1 is a block diagram showing one configuration example of the column signal processing section 260 according to the first embodiment of the present technology. The column signal processing section 260 includes comparators 301 and 302 , counters 261 and 262 , a selection section 400 , and a latch 410 . Figure 5 FIG. 2 shows the configuration of the column signal processing section 260 corresponding to one vertical signal line VSL. Figure 5 The column signal processing unit 260 is shown as being arranged column by column. When the number of columns is N (N is an integer), N comparators 301, N comparators 302, N counters 261, N counters 262, N selection units 400 and N latches 410 are provided.

[0096] Comparators 301 and 302 compare the first reference signal and the second reference signal received from DAC 231 and DAC 232, respectively, with the pixel signals received from the corresponding columns. In the following, it is assumed that the voltages of the first and second reference signals are the first and second reference voltages V RAMP1 and V RAMP2 , and the voltage of the pixel signal input via the vertical signal line VSL is the input voltage V VSL The comparators 301 and 302 respectively convert the first reference voltage V RAMP1 and the second reference voltage V RAMP2 With input voltage V VSL The comparison results COMP1 and COMP2 compared with each other are provided to the counters 261 and 262 of the corresponding columns.

[0097] In addition, in the following, when the pixel circuit 250 is initialized, the input voltage V VSL is called the “reset level” and is the input voltage V when the charge is transferred to the floating diffusion layer 254 VSL It is called "signal level".

[0098] The first counter 261 and the second counter 262 continue to count respectively to obtain the count value until the comparison results COMP1 and COMP2 are inverted. RMP1 The slope starts at the first reference voltage V RMP1 The first counter 261 further counts down the period during which the comparison result COMP1 compared with the reset level is inverted. RMP1 The slope starts at the first reference voltage V RMP1 The first counter 261 performs an up-counting during the period where the comparison result COMP1 compared with the signal level is inverted. In this way, a count value of the difference between the up-counting and the down-counting is obtained. The count value of the difference corresponds to the difference between the reset level and the signal level. The first counter 261 outputs the count value as a first digital signal. In this way, CDS processing for obtaining the difference between the reset level and the signal level is implemented by using the first reference signal.

[0099] In addition, for example, the second counter 262 receives the second reference voltage V RMP2 The slope starts at the second reference voltage V RMP2 The second counter 262 further counts down the period during which the comparison result COMP2 between the second reference voltage V RMP2The slope starts at the second reference voltage V RMP2 The second counter 262 is configured to count up during the period at which the comparison result COMP2 compared with the signal level is inverted. In this way, the difference between the count up and the count down is obtained. The count value of the difference corresponds to the difference between the reset level and the signal level. The second counter 262 outputs the count value as a second digital signal. In this way, the CDS process for obtaining the difference between the reset level and the signal level is implemented by using the second reference signal.

[0100] The first counter 261 and the second counter 262 respectively perform substantially simultaneous counting operations according to the same clock signal received from the timing control section 220 .

[0101] Thereafter, counters 261 and 262 output the first and second digital signals respectively used to represent the count values ​​obtained by CDS processing using the first and second reference signals to the selection section 400. Using comparators 301 and 302 and counters 261 and 262, AD conversion processing for converting analog pixel signals into digital signals is implemented. In other words, each of comparators 301 and 302 and counters 261 and 262 plays the role of ADC. Hereinafter, in some cases, comparator 301 and counter 261 are referred to as ADC1, and comparator 302 and counter 262 are referred to as ADC2. The ADC using comparators and counters described above is generally referred to as a single slope ADC. Note that each of the first and second digital signals corresponds to the difference between the same reset level and the same signal level. In this case, as described later, the slope of the first reference signal and the slope of the second reference signal are different from each other, so the first and second digital signals have different digital values.

[0102] According to the present invention, CDS processing is implemented by up-counting and down-counting. However, the structure for implementing CDS processing is not limited to this structure. Each of counters 261 and 262 can be configured to perform only up-counting or down-counting. In this case, the CDS processing for finding the difference can be implemented by a circuit arranged in the latter stage.

[0103] The selection section 400 selects either the first or second digital signal received from the counters 261 and 262, and performs necessary calculations for the selected first or second digital signal in order to synthesize an image. RMP1 The slope of the second reference voltage V RMP2 The slope ratio of the first reference voltage V RMP2 In this case, when the first and second reference signals start to climb the slope at substantially the same time, the second reference voltage VRMP2 Compared with the first reference voltage V RMP2 Earlier with input voltage V VSL Therefore, ADC1 is considered to detect the input voltage V with a higher gain (higher resolution) than ADC2. VSL .

[0104] On the other hand, each of the counters 261 and 262 operates according to a clock signal having substantially the same frequency received from the timing control unit 220. Therefore, ADC1 uses the same grayscale (same bit) as ADC2 to realize the input voltage V VSL AD conversion.

[0105] As described above, the first digital signal is a signal having the same grayscale as the second digital signal but obtained by performing AD conversion with a higher gain than the gain of the second digital signal. The gain ratio of ADC1 to ADC2 depends on the first reference voltage V RMP1 and the second reference voltage V RMP2 For example, assuming that the gain ratio of ADC1 to ADC2 is equal to the first reference voltage V RMP1 and the second reference voltage V RMP2 In this case, assuming that the slope of the first digital signal is one eighth of the slope of the second digital signal, the gain of ADC1 is eight times the gain of ADC2. Therefore, ADC1 can detect the image signal with a resolution eight times that of ADC2.

[0106] On the other hand, the clock signal CLK for operating the counters 261 and 262 is a common clock signal for the counters 261 and 262. In this case, the operating speed of ADC1 is substantially equal to the operating speed of ADC2. Therefore, ADC1 operates at the same operating speed as that of ADC2 and realizes the input voltage V with a higher gain than that of ADC2. VSL AD conversion.

[0107] By using the above-mentioned configuration in which ADC1 and ADC2 are provided on the same vertical signal line VSL as a common signal line, it is possible to: VSL When the signal level is low (the image is darker), ADC1 is selected to perform input voltage V with a higher gain. VSL The first digital signal is obtained by AD conversion. VSL When the signal level is high (the image is brighter), ADC2 is selected to perform input voltage V with a lower gain. VSLAs described above, the solid-state imaging element 200 according to the present technology can obtain a second digital signal based on the input voltage V VSL The first digital signal or the second digital signal is selected according to the signal level of the image, and the selected digital signal is output. For example, a method of detecting only the dark area of ​​the image with high gain (high resolution) and detecting the bright area of ​​the image with normal gain can be adopted.

[0108] The latch 410 holds the first digital signal or the second digital signal received from the selection section 400. The latch 410 outputs the held first digital signal or the second digital signal to the DSP circuit 120 under the control of the horizontal scanning circuit 270.

[0109] [Comparator Configuration Example]

[0110] Figure 6 2 is a circuit diagram showing one configuration example of ADC1 and ADC2 according to the first embodiment of the present technology. ADC1 includes a comparator 301 and a counter 261. ADC2 includes a comparator 302 and a counter 262.

[0111] The comparator 301 includes capacitors 311_1 and 314_1 , an input transistor 312_1 , an auto-zero switch 313_1 , an initialization switch 343_1 , an output transistor 315_1 , current sources 320_1 and 330_1 , and clamp transistors 342_1 and 344_1 .

[0112] The auto-zero capacitor 311_1 as a first auto-zero capacitor is provided between the DAC 231 and the gate of the input transistor 312_1. The DAC 231 as a first reference voltage supply section generates and outputs a first reference signal (ramp signal) RMP1. The DAC 232 as a second reference voltage supply section generates and outputs a second reference signal (ramp signal) RMP2. As described above, the reference signals RMP1 and RMP2 are signals having voltage slopes different from each other.

[0113] The source of the input transistor 312_1 as the first input transistor is connected to the vertical signal line VSL. VSL is input to the source. In addition, the reference voltage V RMP1 The input voltage V is input to the gate of the input transistor 312_1 via the auto-zero capacitor 311_1. VSL The reference voltage V input to the gate of the input transistor 312_1 RMP1 The input transistor 312_1 outputs a voltage corresponding to the input voltage V VSLFor example, when the input voltage V VSL and reference voltage V RMP1 When the input voltage V VSL The state of "substantially equal to each other" here means that the changes of the voltages relative to the voltage value during the automatic zero adjustment are equal to each other or the difference between these changes falls within a predetermined allowable value. For example, a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the input transistor 312_1. Preferably, the back gate and the source of the input transistor 312_1 are short-circuited to each other to reduce the back gate effect.

[0114] The auto-zero switch 313_1 as the first switch is provided between the gate and the drain of the input transistor 312_1. The auto-zero switch 313_1 implements a short circuit between the gate and the drain of the input transistor 312_1 according to a control signal from the timing control section 220. Before the reset level is detected, the auto-zero switch 313_1 makes the voltage at the gate and the voltage at the drain of the input transistor 312_1 equal.

[0115] The initialization switch 343_1 as the second switch is provided between the gate and the drain of the output transistor 315_1. The initialization switch 343_1 implements a short circuit between the gate and the drain of the output transistor 315_1 according to a control signal from the timing control section 220. Before the signal level is detected, the initialization switch 343_1 makes the voltage at the gate and the voltage at the drain of the output transistor 315_1 equal to each other for initialization.

[0116] The current source 320_1 as the first current source is inserted between the drain of the input transistor 312_1 and a predetermined reference terminal (eg, a ground terminal). The current source 320_1 provides a constant current Id1_1. The current source 320_1 is implemented by an N-type MOSFET or the like. The circuit configuration of the current source 320_1 will be described later.

[0117] The capacitor 314_1 is provided between the source and the drain of the input transistor 312_1 to remove high frequency noise.

[0118] The source of the output transistor 315_1 as the first output transistor is connected to the vertical signal line VSL. VSLis input to the source. In addition, the gate of the output transistor 315_1 is connected to the drain of the input transistor 312_1 to receive the input of the drain voltage Vd1. For example, a P-type MOSFET is used as the output transistor 315_1. In addition, it is preferable that the back gate and the source of the output transistor 315_1 are short-circuited to each other.

[0119] Based on the input voltage V input to the source of the output transistor 315_1 VSL The voltage difference (second voltage difference) between the input voltage Vd1 and the drain voltage Vd1 input to the gate of the output transistor 315_1, and the output transistor 315_1 outputs the input voltage Vd1 from the drain. VSL With reference voltage V RMP1 For example, the output transistor 315_1 outputs a signal indicating the input voltage V VSL The difference between the drain voltage Vd1 and the drain voltage Vd2 exceeds the threshold voltage of the output transistor 315_1 as the comparison result COMP1. The comparison result COMP1 is provided to the counter 261.

[0120] The current source 330_1 as the second current source is inserted between the drain of the output transistor 315_1 and a predetermined reference terminal (eg, a ground terminal) to provide a constant current Id2_1. The current source 330_1 is implemented by an N-type MOSFET, etc. The circuit configuration of the current source 330_1 will be described later.

[0121] The clamp transistor 342_1 as the first clamp transistor is provided between the source and the drain of the input transistor 312_1. For example, the clamp transistor 342_1 is a P-type MOSFET. The source of the clamp transistor 342_1 is connected to the vertical signal line VSL (input transistor 312_1), and the gate and the drain of the clamp transistor 342_1 are short-circuited to each other and connected to the drain of the input transistor 312_1 as a common connection destination. The clamp transistor 342_1 is provided to suppress an excessive drop in the drain voltage Vd1 of the input transistor 312_1 and to maintain the supply of the current Id1_1.

[0122] If the clamp transistor 342_1 is not provided, the transistor of the current source 320_1 may enter a non-conductive state because the drain voltage Vd1 of the input transistor 312_1 drops excessively when the constant current Id1_1 from the current source 320_1 is supplied. In this case, the supply of the drain current Id1_1 stops.

[0123] However, according to the present invention, the clamp transistor 342_1 is provided. In this case, the supply of the current Id1_1 can be maintained by limiting the drain voltage Vd1 to a voltage equal to or higher than a predetermined lower limit voltage.

[0124] A clamp transistor 344_1 as a second clamp transistor is provided between the source and drain of the output transistor 315_1. For example, the clamp transistor 344_1 is a P-type MOSFET. The source of the clamp transistor 344_1 is connected to the vertical signal line VSL (output transistor 315_1), and the gate and drain of the clamp transistor 344_1 are short-circuited to each other and connected to the drain of the input transistor 312_1 as a common connection destination. The clamp transistor 344_1 is provided to suppress an excessive drop in the drain voltage of the output transistor 315_1 and maintain the supply of the current Id2_1.

[0125] In the case where the clamp transistor 344_1 is not provided, the drain voltage of the output transistor 315_1 may excessively drop when the constant current Id2_1 from the current source 330_1 is supplied, so the transistor of the current source 330_1 enters a non-conductive state. In this case, the supply of the drain current Id2_1 stops.

[0126] However, according to the present invention, the clamp transistor 344_1 is provided. In this case, the supply of the current Id2_1 can be maintained by limiting the drain voltage of the output transistor 315_1 to a voltage equal to or higher than a predetermined lower limit voltage.

[0127] The counter 261 obtains a first digital signal by measuring a period from the start of the slope of the reference signal RMP1 to the inversion of the comparison result COMP1 and performing CDS processing, and outputs the first digital signal thus obtained to the selection section 400 .

[0128] The comparator 302 includes capacitors 311_2 and 314_2, an input transistor 312_2, an auto-zero switch 313_2, an initialization switch 343_2, an output transistor 315_2, current sources 320_2 and 330_2, and clamp transistors 342_2 and 344_2. Note that the configuration and function of the comparator 302 are similar to those of the comparator 301, and can be easily understood from the description of the comparator 301 by replacing the reference numeral ***_1 with ***_2. In this case, *** is a number of the reference numeral.

[0129] The source of the input transistor 312_2 as the second input transistor is connected to the vertical signal line VSL. VSL is input to the source. In addition, the reference voltage V RMP2The voltage V is input to the gate of the input transistor 312_2 via the auto-zero capacitor 311_2 as the second auto-zero capacitor. The auto-zero capacitor 311_2 is provided between the DAC 232 and the gate of the input transistor 312_2. Based on the input voltage V input to the source of the input transistor 312_2 VSL The reference voltage V input to the gate of the input transistor 312_2 RMP2 The input transistor 312_2 outputs a voltage corresponding to the input voltage V VSL For example, when the input voltage V VSL and reference voltage V RMP2 When the input voltage V VSL For example, a P-type MOSFET is used as the input transistor 312_2. Preferably, the back gate and the source of the input transistor 312_2 are short-circuited to each other to reduce the back gate effect.

[0130] The auto-zero switch 313_2 as the third switch is provided between the gate and the drain of the input transistor 312_2. The auto-zero switch 313_2 implements a short circuit between the gate and the drain of the input transistor 312_2 according to a control signal from the timing control section 220. Before the reset level is detected, the auto-zero switch 313_2 makes the voltage at the gate and the voltage at the drain of the input transistor 312_2 equal.

[0131] The initialization switch 343_2 as the fourth switch is provided between the gate and the drain of the output transistor 315_2. The initialization switch 343_2 implements a short circuit between the gate and the drain of the output transistor 315_2 according to a control signal from the timing control section 220. Before the signal level is detected, the initialization switch 343_2 makes the voltage at the gate and the voltage at the drain of the output transistor 315_2 equal to initialize.

[0132] The current source 320_2 as the third current source is provided between the drain of the input transistor 312_2 and a predetermined reference terminal. The current source 320_2 provides a constant current Id1_2. The current source 320_2 is implemented by an N-type MOSFET or the like. The circuit configuration of the current source 320_2 will be described later.

[0133] The capacitor 314_2 is provided between the source and the drain of the input transistor 312_2 to remove high frequency noise.

[0134] The source of the output transistor 315_2 as the second output transistor is connected to the vertical signal line VSL. VSL is input to the source. In addition, the gate of the output transistor 315_2 is connected to the drain of the input transistor 312_2 to receive the input of the drain voltage Vd2. For example, a P-type MOSFET is used as the output transistor 315_2. In addition, it is preferred that the back gate and the source of the output transistor 315_2 are short-circuited to each other.

[0135] Based on the input voltage V input to the source of the output transistor 315_2 VSL The output transistor 315_2 outputs the input voltage Vd1 from the drain of the output transistor 315_2. VSL and reference voltage V RMP2 For example, the output transistor 315_2 outputs a signal indicating the input voltage V VSL The difference between the drain voltage Vd2 and the drain voltage Vd1 exceeds the threshold voltage of the output transistor 315_2 as the comparison result COMP2. The comparison result COMP2 is provided to the counter 262.

[0136] The current source 330_2 as the fourth current source is provided between the drain of the output transistor 315_2 and a predetermined reference terminal to provide a constant current Id2_2. The current source 330_2 is implemented by an N-type MOSFET, etc. The circuit configuration of the current source 330_2 will be described later.

[0137] Note that the current flowing in the vertical signal line VSL is the sum of the currents flowing in the first to fourth current sources 320_1, 320_2, 330_1, and 330_2. In addition, the amount of current flowing in each current source 320_1, 320_2, 330_1, and 330_2 is almost equal to reduce interference between the comparators 301 and 302.

[0138] The clamp transistor 342_2 as the third clamp transistor is provided between the source and the drain of the input transistor 312_2. For example, the clamp transistor 342_2 is a P-type MOSFET. The source of the clamp transistor 342_2 is connected to the vertical signal line VSL (input transistor 312_2), and the gate and drain of the clamp transistor 342_2 are short-circuited and connected to the drain of the input transistor 312_2 as a common connection destination. The clamp transistor 342_2 is provided to suppress an excessive drop in the drain voltage Vd2 of the input transistor 312_2 and maintain the supply of the current Id1_2.

[0139] The clamp transistor 344_2 as the fourth clamp transistor is provided between the source and the drain of the output transistor 315_2. For example, the clamp transistor 344_2 is a P-type MOSFET. The source of the clamp transistor 344_2 is connected to the vertical signal line VSL (output transistor 315_2), and the gate and the drain of the clamp transistor 342_2 are short-circuited to each other and connected to the drain of the input transistor 312_2 as a common connection destination. The clamp transistor 344_2 is provided to suppress an excessive drop in the drain voltage of the output transistor 315_2 and maintain the supply of the current Id2_2.

[0140] The counter 262 obtains a second digital signal by measuring a period from the start of the slope of the reference signal RMP2 to the inversion of the comparison result COMP2 and performing CDS processing, and outputs the second digital signal thus obtained to the selection section 400 .

[0141] [Configuration example of current source]

[0142] Figure 7 1 is a circuit diagram showing an example of the internal structure of the current sources 320_1, 330_1, 320_2 and 330_2 of the present technology. The current sources 320_1, 330_1, 320_2 and 330_2 may use the same structure. Therefore, for convenience, Figure 7 The construction of only one of these current sources is shown.

[0143] The current sources 320_1 , 330_1 , 320_2 and 330_2 respectively include current source transistors 321_1 ˜ 321_4 , capacitors 322_1 ˜ 322_4 and switches 323_1 ˜ 323_4 .

[0144] The first current source transistor 321_1 is provided between the drain of the input transistor 312_1 and a predetermined reference terminal. The second current source transistor 321_2 is provided between the drain of the output transistor 315_1 and a predetermined reference terminal. The third current source transistor 321_3 is provided between the drain of the input transistor 312_2 and a predetermined reference terminal. The fourth current source transistor 321_4 is provided between the drain of the output transistor 315_2 and a predetermined reference terminal. For example, each of the current source transistors 321_1 to 321_4 is formed by an N-type MOSFET.

[0145] The first to fourth capacitors 322_1 to 322_4 are respectively connected between the gate of each of the current source transistors 321_1 to 321_4 and the reference terminal.

[0146] The first to fourth sample-and-hold switches 323_1 to 323_4 are connected to gates of the current source transistors 321_1 to 321_4 , respectively.

[0147] A predetermined bias voltage is applied to the gate of each of the current source transistors 321_1 to 321_4. In the initial state, these bias voltages are sampled by the capacitors 322_1 to 322_4 when the sample-hold switches 323_1 to 323_4 are turned on. Thereafter, the bias voltages are held in the capacitors 322_1 to 322_4 when the sample-hold switches 323_1 to 323_4 are turned off. Each of the sample-hold switches 323_1 to 323_4 only needs to enter the on state at the same timing as the timing of the auto-zero switch 313_1 (see Figure 8 ).

[0148] The current source transistors 321_1 to 321_4 provide constant currents Id1_1 , Id2_1 , Id1_2 , and Id2_2 , respectively, according to the bias voltages held in the capacitors 322_1 to 322_4 .

[0149] Next, the operations of the comparators 301 and 302 will be described.

[0150] Figure 8 is a timing chart presenting one example of the operation of the comparator 301 according to the first embodiment of the present technology.

[0151] At time T0 immediately before AD conversion starts, the auto-zero switch 313_1 enters an on state for a predetermined auto-zero period. In this way, the gate and drain of the input transistor 312_1 are short-circuited to each other, thereby initializing the comparator 301 (implementing auto-zero of the comparator 301).

[0152] Next, DAC 231 starts to make the reference voltage V RMP1 Lower, and let the reference voltage V RMP1 At the same time, assuming that the input voltage V VSL The reset level (P phase level) is V VSLp .

[0153] Then, assuming that the reference voltage V RMP1 and reset level V VSLp At time T3, the drain voltage Vd1 of the input transistor 312_1 becomes substantially equal to each other. Assume that at time T3, the drain voltage Vd1 of the input transistor 312_1 is Vdp. Further, assume that a level lower than Vdp is a low level, and a level equal to or higher than Vdp is a high level. In this case, at time T3, the drain voltage Vd1 of the input transistor 312_1 is reversed from a low level to a high level. As a result, the gate voltage (Vd1) of the output transistor 315_1 is changed from a low level to a high level, and the comparison result COMP1 is reversed.

[0154] Then, DAC 231 converts the reference voltage V RMP1 Initialization, and, at time T4 before AD conversion of the signal level, the initialization switch 343_1 enters the on state for a predetermined period of time. In this way, the gate and drain of the output transistor 315_1 are short-circuited to each other, thereby initializing the output transistor 315_1.

[0155] Next, DAC 231 starts to make the reference voltage V RMP1 Lower, and let the reference voltage V RMP1 The charge is gradually reduced at a predetermined slope over a constant period of time. Figure 4 As a result, the input voltage V VSL The signal level (D-phase level) V VSLd Assuming the signal level V VSLd than the reset level V VSLp Low ΔV.

[0156] Then, assuming that the reference voltage V RMP1 and signal level V VSLd At time T6, they become substantially equal to each other. Assuming that at time T6, the drain voltage Vd1 of the input transistor 312_1 is Vdd, the drain voltage Vdd at this time has a value lower by ΔV than the drain voltage Vdp. Specifically, the drain voltage Vdd at time T6 depends on the input voltage (signal level V VSLd ), and as the signal level V VSLd The drain voltage Vdd of the input transistor 312_1 is a voltage lower by ΔV than the drain voltage Vdp at the time of reset level conversion.

[0157] Therefore, if the drain voltage Vd1 is used as the comparison result COMP1, the inversion timing of the drain voltage Vd1 is at time T7 after time T6. The time T7 deviates from the reference voltage V RMP1 and signal level V VSLd The ideal time T6 when the comparison result COMP1 becomes substantially equal to each other. In this case, ADC1 will cause a linear error or offset. This error may cause image quality degradation. In other words, if the comparison result COMP1 is output from the drain of the input transistor 312_1 in a configuration in which the output transistor 315_1 is not provided, the image quality may be degraded.

[0158] In contrast, according to the present invention, an output transistor 315_1 is provided in the subsequent stage of the input transistor 312_1, and the source and drain of the input transistor 312_1 are connected to the source and gate of the output transistor 315_1. Through this connection, the drain-source voltage of the input transistor 312_1 is input as the gate-source voltage of the output transistor 315_1.

[0159] At the reference voltage V RMP1 and input voltage V VSL At time T3 and time T6, the input voltage V VSL The voltage drop ΔV of is equal to the voltage drop of the drain voltage Vd1. Therefore, the drain-source voltage of the input transistor 312_1 has the same value at time T3 as at time T6. Specifically, the drain-source voltage of the input transistor 312_1 is equal to the voltage during the auto-zero adjustment at both time T3 and time T6. Since the drain-source voltage of the input transistor 312_1 is equal to the gate-source voltage of the output transistor 315_1, the drain voltage of the output transistor 315_1 is reversed at time T3 and at time T6.

[0160] As described above, the comparator 301 according to the present invention has a two-stage structure including the input transistor 312_1 and the output transistor 315_1. In this case, the inversion timing of the comparison result COMP1 is at the reference voltage V RMP1 and signal level V VSLd At the ideal times T3 and T6 when the drain voltage Vd1 becomes substantially equal to each other. Therefore, the error at the inversion time is suppressed. As a result, compared with the case where the drain voltage Vd1 is used as the comparison result COMP1, the solid-state imaging element 200 according to the present invention can reduce linear errors and offsets, thereby further achieving an improvement in image quality.

[0161] Fig. 9 is a timing chart presenting one example of the operation of the comparator 302 according to the first embodiment of the present technology. Note that the operation of the comparator 302 is substantially the same as the operation of the comparator 301, except that the reference signal RMP2 has a voltage slope different from that of the reference signal RMP1. In addition, the comparator 302 operates simultaneously with the comparator 301.

[0162] At time T0, the auto-zero switch 313_2 enters the on state for a predetermined auto-zero period. In this way, the gate and drain of the input transistor 312_2 are short-circuited to each other, thereby initializing the comparator 302 (achieving auto-zero of the comparator 302).

[0163] Next, DAC 232 starts to make the reference voltage V RMP2Lower, and let the reference voltage V RMP2 The reference voltage V RMP2 Voltage slope ratio Figure 8 The reference voltage V RMP1 The voltage slope is steeper.

[0164] Then, assuming that the reference voltage V RMP2 and reset level V VSLp At time T3_2, they become substantially equal to each other. Time T3_2 is earlier than time T3. In this case, at time T3_2, the drain voltage Vd2 of the input transistor 312_2 is inverted from a low level to a high level, and the gate voltage (comparison result COMP2) of the output transistor 315_2 is inverted.

[0165] Then, DAC 232 converts the reference voltage V RMP2 Initialization, and at time T4, the initialization switch 343_2 enters the on state for a predetermined period of time. In this way, the gate and drain of the output transistor 315_2 are short-circuited to each other, thereby initializing the output transistor 315_2.

[0166] Next, DAC 232 starts to make the reference voltage V RMP2 Lower, and let the reference voltage V RMP2 The charge is gradually reduced at a predetermined slope over a constant period of time. Figure 4 As a result, the input voltage V VSL The signal level (D-phase level) V VSLd .

[0167] Then, assuming that the reference voltage V RMP2 and signal level V VSLd At time T6_2, they become substantially equal to each other. Time T6_2 is earlier than time T6. Assuming that at time T6_2, the drain voltage Vd2 of the input transistor 312_2 is Vdd, the drain voltage Vdd at this time has a value lower by ΔV than the drain voltage Vdp. Specifically, the drain voltage Vdd at time T6_2 depends on the input voltage (signal level V VSLd ), and as the signal level V VSLd The drain voltage Vdd of the input transistor 312_2 is lower by ΔV than the drain voltage Vdp at the reset level transition.

[0168] If the drain voltage Vd2 is used as the comparison result COMP2, the inversion of the drain voltage Vd2 is at a time T7_2 after the time T6_2. The time T7_2 deviates from the reference voltage V RMP2 and signal level VVSLd The ideal time when the ADC2 and the ADC2 become substantially equal is T6_2. In this case, ADC2 will cause linearity error or offset. This error will cause image quality degradation.

[0169] In contrast, according to the present invention, an output transistor 315_2 is provided in the subsequent stage of the input transistor 312_2, and the source and drain of the input transistor 312_2 are connected to the source and gate of the output transistor 315_2. Through this connection, the drain-source voltage of the input transistor 312_2 is input as the gate-source voltage of the output transistor 315_2.

[0170] At the reference voltage V RMP2 and input voltage V VSL At time T3_2 and time T6_2, the input voltage V VSL The voltage drop ΔV of is equal to the voltage drop of the drain voltage Vd2. Therefore, the drain-source voltage of the input transistor 312_2 has the same value at time T3_2 as at time T6_2. Specifically, the drain-source voltage of the input transistor 312_2 is equal to the voltage during the auto-zero adjustment at both time T3_2 and time T6_2. Since the drain-source voltage of the input transistor 312_2 is equal to the gate-source voltage of the output transistor 315_2, the drain voltage of the output transistor 315_2 is reversed at time T3_2 and at time T6_2.

[0171] As described above, the comparator 302 according to the present invention has a two-stage structure including an input transistor 312_2 and an output transistor 315_2. In this case, the inversion timing of the comparison result COMP2 is at the reference voltage V RMP2 and signal level V VSLd At the ideal time T3_2 and time T6_2 when the drain voltage Vd2 becomes substantially equal to each other. Therefore, the error at the inversion time is suppressed. As a result, compared with the case where the drain voltage Vd2 is used as the comparison result COMP2, the solid-state imaging element 200 according to the present invention can reduce linear errors and offsets, thereby further achieving an improvement in image quality.

[0172] In addition, according to the present invention, a plurality of ADC1 and ADC2 with different gains are provided for one vertical signal line VSL. This configuration can generate first and second digital signals by performing AD conversion with different gains from one pixel signal. The selection unit 400 can select a digital signal that has been AD converted with an appropriate gain from the first and second digital signals.

[0173] Fig.10 is the input voltage V of ADC1 and ADC2 according to the present invention.VSL Graph showing an example of the relationship between the output values ​​(first and second digital signals). The horizontal axis of the graph represents the input voltage V to ADC1 and ADC2. VSL (Analog value) The vertical axis represents the first and second digital signals (digital values) outputted from ADC1 and ADC2, respectively.

[0174] refer to Fig.10 The effect produced by providing two comparators 301 and 302 having different gains corresponding to one vertical signal line VSL will be described.

[0175] Generally, if the number of counts of the counter is reduced by reducing the gain of the ADC, the length of time and power consumption required for AD conversion are usually reduced. However, in this case, the resolution of the image is reduced, and the grayscale of the pixel data obtained after the AD conversion becomes larger (becomes coarse). Such grayscale coarseness of pixel data is not obvious in a bright image area containing a large amount of noise, but becomes significant in a dark image area containing a small amount of noise. Therefore, the brightness difference between the grayscales of the pixel data appears on the screen in the dark image area.

[0176] On the other hand, if the counter counts are increased by increasing the gain of the ADC, the resolution of the image is improved. Therefore, the grayscale of the pixel data obtained after the AD conversion becomes smaller (becomes finer). In this case, even in the dark image area, the brightness difference between the grayscales of the pixel data is not obvious. As a result, pixel data with less degradation can be obtained. However, the time required for AD conversion becomes longer, and the power consumption is large. In other words, there is a trade-off relationship between image quality and the time required for AD conversion or power consumption.

[0177] In contrast, according to the present invention, when the frequency of the clock signal CLK increases to a certain extent, ADC1 AD-converts the pixel signal with a relatively high gain to generate a first digital signal D1, and ADC2 AD-converts the pixel signal with a relatively low gain to generate a second digital signal D2.

[0178] In addition, when the image is dark and the input voltage V VSL Below the threshold V VSL_th In the case of , the selection unit 400 selects the first digital signal D1 obtained by AD conversion with a high gain. VSL Equal to or above the threshold V VSL_th In the case of , the selection unit 400 selects the second digital signal D2 obtained by AD conversion with a low gain.

[0179] The selection section 400 outputs the selected digital signal D1 or D2 to the latch 410 to latch the selected digital signal D1 or D2 through the latch 410. Thereafter, the DSP circuit 120 performs a calculation process on the selected digital signal to generate image data.

[0180] In the case where the first digital signal D1 is selected, the DSP circuit 120 converts (compresses) data about the first digital signal D1 in such a manner that the gain of the first digital signal D1 matches the gain of the second digital signal D2. For example, in the case where the gain of ADC1 is eight times the gain of ADC2, that is, in the case where the slope of the reference signal RMP1 is one eighth of the slope of the reference signal RMP2, the DSP circuit 120 compresses the grayscale of the first digital signal D1 to one eighth. As a result, the gain of the first digital signal (hereinafter referred to as the compressed digital signal) D1c obtained after compression is equal to the gain of the second digital signal D2. Therefore, an image can be formed.

[0181] Here, in the case where the grayscales of the first digital signal D1 and the second digital signal D2 are AD-converted with 11 bits, the compressed digital signal D1c obtained by reducing the grayscale of the first digital signal D1 to one eighth is equivalent to a signal obtained by AD-converting with a grayscale of 14 bits. Specifically, the compressed digital signal D1c for a dark image area is image data having a relatively small (fine) grayscale, and the second digital signal D2 for a relatively bright image area is image data having a relatively large (coarse) grayscale.

[0182] As described above, according to the present invention, while reducing the frequency of the clock signal CLK, ADC1 performs AD conversion on the pixel signal with a relatively high gain to generate the first digital signal D1. Thereafter, the DSP circuit 120 compresses the grayscale of the first digital signal D1 to generate a compressed digital signal D1c and form an image. The grayscale of the second digital signal D2 may not need to be converted.

[0183] In this way, the time required for AD conversion can be shortened, power consumption can be reduced, and image quality degradation in dark image areas can also be suppressed. In other words, the solid-state imaging element 200 according to the present invention can eliminate the trade-off relationship between image quality and the time required for AD conversion or power consumption.

[0184] In addition, the input voltage V can be arbitrarily set at the selection unit 400. VSL The threshold is used to change the switching point of the AD conversion gain.

[0185] Note that the grayscale of the second digital signal D2 or the grayscales of both the first digital signal D1 and the second digital signal D2 may be converted in such a manner that the gain of the first digital signal D1 and the gain of the second digital signal D2 match.

[0186] According to the present invention, the reference signals RMP1 and RMP2 are signals each having a falling slope. However, the reference signals RMP1 and RMP2 may be signals each having a rising slope. In the case where each of the reference signals RMP1 and RMP2 has a rising slope, the reset level becomes lower than the signal level. Therefore, in the case where the reference voltage circuit has a current source that supplies current to the resistor on the GND side, the lower the reset level, the smaller the current used to generate the reference voltage. Therefore, the noise contained in the reference signals RMP1 and RMP2 can be reduced. For the reference signals RMP1 and RMP2, the relationship between the signal level and the reset level becomes opposite. Therefore, the noise becomes smaller in the reset level or in the dark image area. On the other hand, in the case where the reference signals RMP1 and RMP2 each have a rising slope, for a high input voltage V VSL Therefore, each of the reference signals RMP1 and RMP2 may be a signal having a falling slope or a signal having a rising slope.

[0187] (Second embodiment)

[0188] Fig.11 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a second embodiment of the present technology. According to the second embodiment, ADC1 and ADC2 further include clamp transistors 345_1, 347_1, 345_2, and 347_2. The clamp transistor 345_1 as the fifth clamp transistor is connected in parallel to the clamp transistor 342_1, and a predetermined bias voltage is applied to the gate of the clamp transistor 345_1. The clamp transistor 347_1 as the sixth clamp transistor is connected in parallel to the clamp transistor 344_1, and a predetermined bias voltage is applied to the gate of the clamp transistor 347_1. The clamp transistor 345_2 as the seventh clamp transistor is connected in parallel to the clamp transistor 342_2, and a predetermined bias voltage is applied to the gate of the clamp transistor 345_2. A clamp transistor 347_2 as an eighth clamp transistor is connected in parallel to the clamp transistor 344_2 , and a predetermined bias voltage is applied to the gate of the clamp transistor 347_2 .

[0189] Each of the clamp transistors 345_1 , 347_1 , 345_2 , and 347_2 is formed of an N-type MOSFET.

[0190] The bias voltage is applied to the gate of each of the clamp transistors 345_1, 347_1, 345_2, and 347_2. VSL The lower limits of the drain voltages Vd1 and Vd2 are independently constrained. In this way, the supply stop of the drain currents Id1 and Id2 can be prevented more reliably. According to the second embodiment, with the input voltage V VSL The lower limit of the drain voltage Vd is constrained independently of the bias voltage. Therefore, a decrease in the dynamic range or an increase in noise can be suppressed.

[0191] Note that the gates of the clamp transistors 345_1, 347_1, 345_2, and 347_2 may be connected to their respective drains without causing problems with dynamic range or noise. In this case, the lower limit voltage of the drain voltages Vd1 and Vd2 is equal to the input voltage V VSL Therefore, the dependence of the maximum amplitude of the gate-source voltage of each of the output transistors 315_1 and 315_2 on the signal level is suppressed, and thus the reduction of the linearity error and the gain error can be achieved.

[0192] The other configurations of the second embodiment may be similar to the corresponding configurations of the first embodiment. Therefore, the second embodiment may provide similar beneficial effects to those of the first embodiment.

[0193] (Third Implementation Method)

[0194] Fig.12 3 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a third embodiment of the present technology. The third embodiment is different from the first embodiment in that ADC1 further includes a NOR gate (NOR gate) 350_1 and an inverter 351_1, and ADC2 further includes a NOR gate 350_2 and an inverter 351_2.

[0195] The NOR gate 350_1 as a first logic gate is connected to the drain of the output transistor 315_1 to output the NOR (or negation logic result) of the output from the output transistor 315_1 and the control signal XEN_1 to the inverter 351_1. The inverter 351_1 inverts the output of the NOR gate 350_1 and outputs the inverted output as the comparison result COMP1 to the counter 261.

[0196] The NOR gate 350_2 as the second logic gate is connected to the drain of the output transistor 315_2 to output the NOR (or negation logic result) of the output from the output transistor 315_2 and the control signal XEN_2 to the inverter 351_2. The inverter 351_2 inverts the output of the NOR gate 350_2 and outputs the inverted output as the comparison result COMP2 to the counter 262.

[0197] According to the configuration described above, the voltages of the comparison results COMP1 and COMP2 can be adjusted to the power supply voltage level of other logic circuits. In addition, the logic of the outputs of the NOR gates 350_1 and 350_2 is fixed during the auto-zero period, the AD conversion period of the reset level, and the AD conversion period of the signal level. In this way, even when the drain voltage of the output transistor 315_1 is an intermediate voltage, the through-current can be stopped from flowing into the NOR gate 350 of the third stage.

[0198] The third embodiment can provide beneficial effects similar to those of the first embodiment. In addition, the third embodiment can be combined with the second embodiment. Note that in each of ADC1 and ADC2, more logic gates can be connected in a multi-stage manner.

[0199] (Fourth Implementation Method)

[0200] Fig.13 : is a circuit diagram showing a configuration example of ADC1 and ADC2 according to a fourth embodiment of the present technology. The solid-state imaging element 200 according to the fourth embodiment is different from that of the first embodiment in that a VSL current source 353 is additionally provided.

[0201] The VSL current source 353 as a fifth current source is connected between the vertical signal line VSL and the reference terminal. The current amounts of the currents Id1_1 , Id2_1 , Id1_2 , and Id2_2 can each reduce the current amount supplied from the VSL current source 353 to the vertical signal line VSL.

[0202] Other configurations of the fourth embodiment can be similar to the corresponding configurations of the first embodiment. In this way, the fourth embodiment can provide a beneficial effect similar to the beneficial effect of the first embodiment. In addition, the fourth embodiment can be combined with the second or third embodiment. In this way, the fourth embodiment can provide the beneficial effect of the second or third embodiment.

[0203] (Fifth Implementation Method)

[0204] Fig.14ADC1 and ADC2 according to the fifth embodiment of the present technology are different from those of the first embodiment in that they are further provided with buffers 355_1 and 355_2 , respectively.

[0205] The first buffer 355_1 is provided between the DAC 231 and the auto-zero capacitor 311_1. The buffer 355_1 may be arranged corresponding to each vertical signal line VSL, or may be arranged corresponding to a plurality of vertical signal lines VSL.

[0206] The second buffer 355_1 is provided between the DAC 232 and the auto-zero capacitor 311_2. The buffer 355_2 may be arranged corresponding to each vertical signal line VSL, or may be arranged corresponding to a plurality of vertical signal lines VSL.

[0207] The buffers 355_1 and 355_2 can respectively make the loads of ADC1 and ADC2 hidden from the DACs 231 and 232. Furthermore, interference of a voltage kickback from each of ADC1 and ADC2 with respect to a vertical signal line VSL arranged adjacent to ADC1 or ADC2 across a reference signal transmission line can be suppressed.

[0208] Other configurations of the fifth embodiment may be similar to the corresponding configurations of the first embodiment. In this way, the fifth embodiment may provide a beneficial effect similar to that of the first embodiment. In addition, the fifth embodiment may be combined with any one of the second to fourth embodiments. In this way, the fifth embodiment may provide a beneficial effect similar to that of any one of the second to fourth embodiments.

[0209] (Sixth Implementation Method)

[0210] Fig.15 ADC1 and ADC2 according to the sixth embodiment of the present technology are different from those of the first embodiment in that they are further provided with capacitors 348_1 and 348_2 and automatic zeroing switches 349_1 and 349_2, respectively.

[0211] The capacitor 348_1 as the fifth capacitor is provided between the drain of the input transistor 312_1 and the gate of the output transistor 315_1. The auto-zero switch 349_1 as the fifth switch is provided between the gate and the drain of the output transistor 315_1. The auto-zero switch 349_1 implements a short circuit between the gate and the drain of the output transistor 315_1 according to a control signal from the timing control section 220.

[0212] Furthermore, the initialization switch 343_1 opens and closes a path between the drain of the input transistor 312_1 and the drain of the output transistor 315_1 according to another control signal from the timing control section 220 .

[0213] The capacitor 348_2 as the sixth capacitor is provided between the drain of the input transistor 312_2 and the gate of the output transistor 315_2. The auto-zero switch 349_2 as the sixth switch is provided between the gate and the drain of the output transistor 315_2. The auto-zero switch 349_2 implements a short circuit between the gate and the drain of the output transistor 315_2 according to a control signal from the timing control section 220.

[0214] Furthermore, the initialization switch 343_2 opens and closes a path between the drain of the input transistor 312_2 and the drain of the output transistor 315_2 according to another control signal from the timing control section 220 .

[0215] According to the sixth embodiment, auto-zero switches 349_1 and 349_2 are added to output transistors 315_1 and 315_2, respectively. Therefore, even when current sources 320_1, 330_1, 320_2, and 330_2 generate currents Id1_1, Id2_1, Id1_2, and Id2_2 individually, differences in these current values ​​can be suppressed.

[0216] Other configurations of the sixth embodiment may be similar to the corresponding configurations of the first embodiment. In this way, the sixth embodiment may provide a beneficial effect similar to that of the first embodiment. In addition, the sixth embodiment may be combined with any one of the second to fifth embodiments. In this way, the sixth embodiment may provide a beneficial effect similar to that of any one of the second to fifth embodiments.

[0217] (Seventh Implementation Plan)

[0218] Fig.16 ADC1 and ADC2 according to the seventh embodiment of the present technology are different from those of the first embodiment in that they are further provided with buffer transistors 317_1 and 317_2 , respectively.

[0219] The buffer transistor 317_1 as a first buffer transistor is connected between the power supply and the source of the output transistor 315_1. The gate of the buffer transistor 317_1 is connected to the source of the input transistor 312_1.

[0220] The buffer transistor 317_2 as the second buffer transistor is connected between the power supply and the source of the output transistor 315_2. The gate of the buffer transistor 317_2 is connected to the source of the input transistor 312_2. During the inversion of the drain voltages (COMP1 and COMP2) of the output transistors 315_1 and 315_2, the buffer transistors 317_1 and 317_2 can suppress the propagation of the voltage kickback toward the vertical signal line VSL.

[0221] Other configurations of the seventh embodiment may be similar to the corresponding configurations of the first embodiment. In this way, the seventh embodiment may provide a beneficial effect similar to that of the first embodiment. In addition, the seventh embodiment may be combined with any one of the second to sixth embodiments. In this way, the seventh embodiment may provide a beneficial effect similar to that of any one of the second to sixth embodiments.

[0222] (Eighth Implementation Plan)

[0223] Fig.17 1 is a circuit diagram showing a configuration example of ADC1 and ADC2 according to an eighth embodiment of the present technology. ADC1 and ADC2 according to the eighth embodiment share a DAC 232 as a common reference voltage supply section. DAC1 is omitted. ADC1 receives an input of a reference signal RMP1 generated by dividing the voltage of a reference signal RMP2. ADC1 also includes an auto-zero capacitor 311_1 and a voltage-dividing capacitor 354 so as to generate a reference signal RMP1 using the reference signal RMP2.

[0224] The auto-zero capacitor 311_1 is provided between the output of the DAC 232 and the gate of the input transistor 312_1. The voltage-dividing capacitor 354 is connected between the gate of the input transistor 312_1 and the reference terminal.

[0225] The auto-zero capacitor 311_1 and the voltage-dividing capacitor 354 divide the voltage of the common reference signal RMP2 to generate a reference signal RMP1, and input the reference signal RMP1 to the gate of the input transistor 312_1. The voltage-dividing ratio at this time is determined by the capacitance ratio of the auto-zero capacitor 311_1 and the voltage-dividing capacitor 354. For example, assuming that the ratio (C311 / C354) of the capacitance C311 of the auto-zero capacitor 311_1 and the capacitance C354 of the voltage-dividing capacitor 354 is 1 / 7, then the reference voltage V RMP1The slope becomes the reference voltage V RMP2 In other words, the ratio of the gain G1 of ADC1 to the gain G2 of ADC2 (G1 / G2) becomes 8.

[0226] According to the eighth embodiment, it is allowed to omit the DAC 231. Therefore, the circuit scale of the ADC 1 can be reduced, and the power consumption can be reduced.

[0227] Other configurations of the eighth embodiment may be similar to the corresponding configurations of the first embodiment. In this way, the eighth embodiment may provide a beneficial effect similar to that of the first embodiment. In addition, the eighth embodiment may be combined with any one of the second to seventh embodiments. In this way, the eighth embodiment may provide a beneficial effect similar to that of any one of the second to seventh embodiments.

[0228] (Ninth Implementation Plan)

[0229] Fig.18 400 is a circuit diagram showing a configuration example of a selection section 400 according to a ninth embodiment of the present technology. The selection section 400 includes a digital comparator 401 , a register 402 , and a multiplexer 403 .

[0230] The digital comparator 401 compares one or both of the first and second digital signals D1 and D2 with a threshold value to determine whether the input voltage V VSL The input voltage V VSL The size indicates the brightness of the image. Therefore, when the first digital signal D1 or the second digital signal D2 is lower than the threshold, it can be judged that the image is darker than the predetermined brightness. When the first digital signal D1 or the second digital signal D2 is equal to or higher than the threshold, it can be judged that the image is brighter than the predetermined brightness.

[0231] The judgment result is output to the multiplexer 403 as a flag FLG. For example, the flag FLG can be one-bit data. For example, when the first digital signal D1 or the second digital signal D2 is lower than the threshold, the digital comparator 401 only needs to set the flag FLG to "1 (high level)". When the first digital signal D1 or the second digital signal D2 is equal to or higher than the threshold, the digital comparator 401 only needs to set the flag FLG to "0 (low level)". In this way, the multiplexer 403 can select the first digital signal D1 or the second digital signal D2 according to the brightness of the image.

[0232] Fig.18In the embodiment, one input terminal of the digital comparator 401 is connected to the output terminal of the counter 262 to receive the input of the second digital signal D2. However, the digital comparator 401 can also receive the input of the first digital signal D1, and compare the first digital signal D1 with another threshold value to determine the image brightness. The other input terminal of the digital comparator 401 is connected to the register 402 to receive the input of a predetermined threshold value.

[0233] The register 402 stores the threshold value of the first digital signal D1 or the second digital signal D2 and provides the threshold value to the other input terminal of the digital comparator 401 .

[0234] The multiplexer 403 is configured to receive the first and second digital signals D1 and D2 from the counters 261 and 262, and select one of the first and second digital signals D1 and D2 based on the flag FLG. For example, when the flag FLG is "1", the multiplexer 403 selects and outputs the first digital signal D1. When the flag FLG is "0", the multiplexer 403 selects and outputs the second digital signal D2. The multiplexer 403 also outputs the flag FLG together with the digital signal D1 or D2. In this way, the DSP circuit 120 arranged after the multiplexer 403 is able to know the gain during the AD conversion of the selected digital signal (D1 or D2). When the first digital signal D1 is selected, the DSP circuit 120 only needs to select the first digital signal D1 based on the reference voltage V RMP1 With reference voltage V RMP2 The first digital signal D1 is converted according to the slope ratio (gain ratio of ADC1 and ADC2) to synthesize image data.

[0235] As described above, the selection unit 400 can selectively output a digital signal from a plurality of digital signals obtained by AD conversion with different gains according to image brightness. In addition, the selection unit 400 can change the gain of AD conversion to an arbitrary gain by setting a threshold. Other configurations of the ninth embodiment can be similar to the corresponding configurations of the first embodiment. In this way, the ninth embodiment can provide a beneficial effect similar to that of the first embodiment. In addition, the ninth embodiment can be combined with any one of the second to eighth embodiments. In this way, the ninth embodiment can provide a beneficial effect similar to that of any one of the second to eighth embodiments.

[0236] (Tenth Implementation Plan)

[0237] Fig.191 is a circuit diagram showing an example of the configuration of a solid-state imaging element according to the tenth embodiment of the present technology. The solid-state imaging element 200 according to the tenth embodiment includes ADCm as an AD converter in addition to ADC1 and ADC2. ADCm has the same configuration as that of ADC1 and ADC2. However, the reference voltage V RMPm The slope is different from the reference voltage V RMP1 and V RMP2 The reference voltage V RMPm The slope ratio of the reference voltage V RMP1 The slope is steeper than the reference voltage V RMP2 In other words, the gain of ADCm is lower than that of ADC1, but higher than that of ADC2.

[0238] The comparator 303 of ADCm includes an input transistor 312_m as a third input transistor and an output transistor 315_m as a third output transistor. Based on the input voltage V input to the source of the input transistor 312_m, VSL The reference voltage V input to the gate of the input transistor 312_m RMPm The input transistor 312_m outputs a drain voltage corresponding to the input voltage.

[0239] Based on the input voltage V input to the source of the output transistor 315_m VSL The voltage difference between the drain voltage of the input transistor 312_m and the gate voltage of the output transistor 315_m is input, and the output transistor 315_m outputs the input voltage V from the drain. VSL With reference voltage V RMPm The comparison result COMPm is compared with each other.

[0240] The counter 263 calculates the voltage from the reference voltage V RMPm The period from the start of the slope of ADC1 to the inversion of the comparison result COMPm is counted, and the intermediate digital signal Dm is output. In this way, ADCm can output the intermediate digital signal Dm that has been AD-converted with an intermediate gain between the gain of ADC1 and the gain of ADC2.

[0241] When AD conversion is performed using only ADC1 with high gain and ADC2 with low gain, if the gain ratio (G1 / G2) of ADC1 to ADC2 is too large, distortion (hereinafter also referred to as artifact) may occur at the boundary of the image area corresponding to the first and second digital signals.

[0242] To solve this problem, the tenth embodiment further provides ADCm having an intermediate gain between the gain of ADC1 and the gain of ADC2. By using three comparators ADC1, ADCm and ADC2 having different gains, artifacts generated at the seams between image areas can be suppressed.

[0243] The selection unit 400 in the tenth embodiment selects a digital signal from three digital signals D1, D2 and Dm. For example, the register 402 stores multiple threshold values ​​different from each other. The digital comparator 401 compares at least one of the digital signals D1, D2 and Dm with multiple threshold values, and outputs identifications FLG1 and FLG2 (two-bit data) as comparison results. For example, when the digital signal is lower than all of the multiple threshold values, the digital comparator 401 sets FLG1 to "0" and sets FLG2 to "0". For example, when the digital signal is equal to or higher than the multiple threshold values, the digital comparator 401 sets FLG1 to "1" and sets FLG2 to "1". For example, when the digital signal is an intermediate value between multiple threshold values, the digital comparator 401 sets FLG1 to "0" and sets FLG2 to "1".

[0244] The multiplexer 403 is configured to receive the digital signals D1, D2, and Dm from ADC1, ADC2, and ADCm, and select one of the digital signals D1, D2, and Dm based on the identifiers FLG1 and FLG2. For example, when the identifiers FLG1 and FLG2 are both "0", the multiplexer 403 selects and outputs the digital signal D1 converted with a high gain. When the identifiers FLG1 and FLG2 are both "1", the multiplexer 403 selects and outputs the digital signal D2 converted with a low gain. When the identifiers FLG1 and FLG2 are "0" and "1" respectively, the multiplexer 403 selects and outputs the digital signal Dm converted with an intermediate gain. The multiplexer 403 also outputs two-bit data about the identifiers FLG1 and FLG2 together with the digital signals D1, D2, and Dm. In this way, the DSP circuit 120 is enabled to know the gain during AD conversion of the selected digital signal (D1, D2 or Dm). The DSP circuit 120 calculates the gain based on the reference voltage V RMP1 、V RMP2 and V RMPm The selected digital signal is converted according to the slope ratio (gain ratio of ADC1, ADC2 and ADCm) to synthesize image data.

[0245] Fig. 20 is the input voltage V of ADC1, ADC2, ADCm according to the tenth embodiment. VSLThe graph is a graph showing an example of the relationship between the input voltage V and the output value (digital signal D1, D2, Dm). The horizontal axis of the graph represents the input voltage V VSL The vertical axis represents the digital signals D1, D2, and Dm.

[0246] According to the tenth embodiment, the digital comparator 401 compares the digital signal D2 with the first threshold value Dt1 and the second threshold value Dt2 to determine the flags FLG1 and FLG2. However, the digital comparator 401 may determine the flags FLG1 and FLG2 by using any one of the digital signals D1, D2, and Dm. The digital comparator 401 may determine the flags FLG1 and FLG2 by using any two or all of the digital signals D1, D2, and Dm.

[0247] In a dark image, when the digital signal D2 is lower than the first threshold value Dt1, the digital comparator 401 outputs "0" and "0" as the flag FLG1 and the flag FLG2, respectively. In this case, the multiplexer 403 selects the digital signal D1 converted with a high gain. The DSP circuit 120 converts (compresses) the data on the digital signal D1 based on the gain ratio of ADC1 to ADC2 in such a manner that the gain of the digital signal D1 matches the gain of the digital signal D2. Fig.10 The conversion process is described.

[0248] In an image with intermediate brightness, when the digital signal D2 is between the first threshold value Dt1 and the second threshold value Dt2, the digital comparator 401 outputs "0" and "1" as the flag FLG1 and the flag FLG2, respectively. In this case, the multiplexer 403 selects the digital signal Dm converted with the intermediate gain. The DSP circuit 120 converts (compresses) the data on the digital signal Dm based on the gain ratio of ADCm to ADC2 in such a manner that the gain of the digital signal Dm matches the gain of the digital signal D2. Fig.10 The conversion process is described.

[0249] In a bright image, when the digital signal D2 is equal to or higher than the second threshold value Dt2, the digital comparator 401 outputs "1" and "1" as the flag FLG1 and the flag FLG2, respectively. In this case, the multiplexer 403 selects the digital signal D2 converted with a low gain. The DSP circuit 120 does not need to compress the digital signal D2.

[0250] Thereby, the gains of the digital signals D1, D2 and Dm are matched with each other, thereby enabling the DSP circuit 120 to form an image.

[0251] Note that the DSP circuit 120 performs gain ratio-based conversion on the digital signals D1 and Dm with the digital signal D2 as a reference. However, the DSP circuit 120 may convert the other two digital signals with the digital signal D1 or Dm as a reference. In addition, the correspondence between the flags FLG1 and FLG2 and the selected digital signals is not limited to the correspondence described in the above embodiment, and may be changed to a different setting as needed.

[0252] As described above, the tenth embodiment is also provided with ADCm having an intermediate gain between the gain of ADC1 and the gain of ADC2. Therefore, the artifact at the seam of the image area can be reduced. Other configurations of the tenth embodiment can be similar to the corresponding configurations of the first embodiment. Therefore, the tenth embodiment can provide a beneficial effect similar to that of the first embodiment. In addition, the tenth embodiment can be combined with any one of the second to the eighth embodiment. In this way, the tenth embodiment can provide a beneficial effect similar to that of any one of the second to the eighth embodiment.

[0253] (Eleventh Implementation Plan)

[0254] Fig.21 1 is a circuit diagram showing an example of the configuration of an ADC and its peripheral circuits according to the eleventh embodiment of the present invention. According to the eleventh embodiment, the multiplexer 501 selectively provides the reference signal RMP1 or the reference signal RMP2 to the ADC according to the flag FLG received from the comparator 506. The comparator 506 selects the reference signal RMP1 or the reference signal RMP2 based on the input voltage V VSL The voltage level of the (analog value) determines the flag FLG in advance. Therefore, the comparator 506 can determine the reference signal (ADC gain) immediately before the ADC performs AD conversion on the D phase of the pixel signal. Therefore, only one ADC is required in the eleventh embodiment.

[0255] However, when the P phase of the pixel signal is AD-converted, since the level of the D phase is unknown, the P phase is AD-converted using the reference signal RMP1 having a high gain. Note that the P phase is a pixel signal indicating a reset level, and the P phase digital signal is a digital signal obtained by AD conversion of the P phase. The D phase is a pixel signal indicating a signal level, and the D phase digital signal is a digital signal obtained by AD conversion of the D phase.

[0256] The solid-state imaging element 200 according to the eleventh embodiment includes one ADC, a multiplexer 501 , a P-phase latch 502 , a D-phase latch 503 , a calculation section 504 , a multiplexer 505 , a comparator 506 , a CDS circuit 507 , and a register 508 .

[0257] The multiplexer 501 receives the reference signal RMP1 from the DAC 231 , receives the reference signal RMP2 from the DAC 232 , and provides the reference signal RMP1 or the reference signal RMP2 to the ADC based on the flag FLG.

[0258] The ADC may have the same configuration as that of ADC1 or ADC2 of the first embodiment. As described above, at the time of AD conversion of the P phase, the ADC performs AD conversion using the reference signal RMP1 having a high gain. At the time of AD conversion of the D phase that is subsequently performed, the reference signal RMP1 has been converted based on the input voltage V VSL The signal level of the flag FLG determines the flag FLG. Therefore, the ADC performs AD conversion of the D phase by using the reference signal RMP1 or RMP2 determined based on the flag FLG.

[0259] The P-phase latch 502 latches a P-phase digital signal obtained by AD conversion by the ADC. The D-phase latch 503 latches a D-phase digital signal obtained by AD conversion by the ADC.

[0260] The calculation unit 504 receives the P-phase digital signal from the P-phase latch 502, and multiplies or divides the P-phase digital signal by a predetermined value stored in the register 508. The predetermined value stored in the register 508 is a value corresponding to the gain of the ADC. For example, as in the first embodiment, when the gain of the ADC using the reference signal RMP1 is eight times the gain of the ADC using the reference signal RMP2, the register 508 stores 8 or one-eighth as the predetermined value. In this case, the register 508 outputs 8 or one-eighth to the calculation unit 504. The calculation unit 504 multiplies the P-phase digital signal by one-eighth, or divides the P-phase digital signal by 8. Specifically, the calculation unit 504 converts (compresses) the P-phase digital signal according to the gain of the ADC.

[0261] The multiplexer 505 receives the converted P-phase digital signal from the calculation section 504 and receives the unconverted P-phase digital signal from the P-phase latch 502. Thereafter, the multiplexer 505 selects the converted P-phase digital signal or the unconverted P-phase digital signal based on the flag FLG and outputs the selected signal to the CDS circuit 507.

[0262] The CDS circuit 507 receives the P-phase digital signal Dp from the multiplexer 505 and receives the D-phase digital signal Dd, and performs CDS processing on the received signals. The CDS circuit 507 outputs the digital signal after the CDS processing together with the flag FLG.

[0263] Fig. 22 is a timing chart presenting an operation example of the ADC according to the eleventh embodiment. Fig. 22 Given an input voltage VVSL The voltage level of the reference signals RMP1 and RMP2 and the flag FLG. The flag FLG corresponds to each of the reference signals RMP1 and RMP2. Note that the voltage levels of the reference signals RMP1 and RMP2 are not shown in the figure.

[0264] For example, AD conversion of the P phase starts at time t1. At this time, the signal level (D phase level) is unknown. Therefore, the reference signal RMP1 with a high gain is selected. In other words, the comparator 506 sets the flag FLG to "0".

[0265] The P-phase digital signal after AD conversion is latched by the P-phase latch 502. The calculation unit 504 performs calculations and gain conversion on the P-phase digital signal. The multiplexer 505 receives the converted P-phase digital signal from the calculation unit 504 and receives the unconverted P-phase digital signal from the P-phase latch 502.

[0266] During the period from t2 to t4, the signal level (D phase) is transmitted to the vertical signal line VSL. During this period, the signal level is determined. For example, when the signal level is V VSL_1 In this case, the signal level becomes lower than the threshold value Dth at time t3. In this case, the comparator 506 compares the threshold value Dth with the signal level V VSL The comparison is performed and the flag FLG is set to "1". As a result, the image is judged to be a bright image, and the multiplexer 501 selects the reference signal RMP2 with a low gain. On the other hand, when the signal level is V VSL_2 In the case of , the signal level is higher than the threshold Dth during the period from t2 to t4. In this case, the comparator 506 compares the threshold Dth with the signal level V VSL A comparison is performed, and the flag FLG is set to “0.” As a result, the image is determined to be a dark image, and the multiplexer 501 selects the reference signal RMP1 having a high gain.

[0267] At time t4 and thereafter, the ADC performs AD conversion of the D phase by using the reference signal RMP1 or RMP2 selected by the multiplexer 501 .

[0268] On the other hand, after the flag FLG is determined, the multiplexer 505 outputs the converted P-phase digital signal or the unconverted P-phase digital signal according to the flag FLG. For example, when the flag FLG is "1", in order to match the gain of the P-phase with the gain of the D-phase (low gain), the multiplexer 505 outputs the converted (compressed) P-phase digital signal to the CDS circuit 507. When the flag FLG is "0", in order to match the gain of the P-phase with the gain of the D-phase (high gain), the multiplexer 505 outputs the unconverted P-phase digital signal to the CDS circuit 507. In this way, the CDS circuit 507 can appropriately perform CDS processing.

[0269] The digital signal after CDS processing can be converted to match the gain of other pixel data. In this way, the digital signal can be synthesized into an image.

[0270] As described above, according to the eleventh embodiment, the flag FLG is based on the input voltage V VSL The reference signal is determined in advance by the voltage level of the (analog value). In addition, the reference signal is determined immediately before the ADC performs AD conversion on the D phase of the pixel signal. In this way, the solid-state imaging element 200 can generate digital signals that are AD converted with different gains by using one ADC.

[0271] (Twelfth Implementation Plan)

[0272] Fig.23 1 is a circuit diagram showing an example of the construction of an ADC and its peripheral circuits according to a twelfth embodiment of the present invention. According to the twelfth embodiment, the comparator 506 is omitted and a latch 509 is provided. The latch 509 is provided between the output terminal of the comparator 304 and the multiplexers 501 and 505 and between the output terminal of the comparator 304 and the output terminal of the CDS circuit 507. Other constructions of the twelfth embodiment may be similar to the corresponding constructions of the eleventh embodiment.

[0273] The latch 509 latches the comparison result COMP4 of the comparator 304 during the level determination period, and outputs the latched comparison result COMP4 as a flag FLG to the multiplexers 501 and 505 and to the output terminal of the CDS circuit 507 .

[0274] Fig.24 1 is a timing diagram showing an example of operation of the ADC according to the twelfth embodiment. Fig.24 The reference signal RMP1 is superimposed on the input voltage V VSL In addition, Fig.24In addition to the flag FLG, the comparison result COMP4 and the latch timing signal Slt are also shown.

[0275] For example, AD conversion of the P phase starts at time t1. The AD conversion process of the P phase may be similar to the corresponding process of the eleventh embodiment.

[0276] During the period from t2 to t5, the signal level (D phase) is transmitted to the vertical signal line VSL. During this period, the signal level determination is performed. Here, according to the twelfth embodiment, the threshold value Dth is not set. The latch 509 sets the flag FLG by using the inversion of the comparison result COMP4 obtained by the comparator 304. In other words, according to the twelfth embodiment, the signal level is determined using the reference signal RMP1 as a threshold. For example, when the signal level is V VSL_1 In the case of VSL_1 At time t3, it becomes lower than the reference signal RMP1. As a result, the comparison result COMP4 obtained by the comparator 304 is inverted and becomes "1 (high level)". At time t4, the latch 509 latches the comparison result COMP4, whereby the flag FLG becomes "1". As a result, the image is judged as a bright image, and the multiplexer 501 selects the reference signal RMP2 with a low gain.

[0277] On the other hand, when the signal level is V VSL_2 In the case of VSL_2 During the period from t2 to t5, the reference signal RMP1 is higher than that. As a result, the comparison result COMP4 obtained by the comparator 304 is not inverted and is maintained at "0 (low level)". At time t4, the latch 509 latches the comparison result COMP4, whereby the flag FLG becomes "0". As a result, the image is judged to be a dark image, and the multiplexer 501 selects the reference signal RMP1 with a high gain.

[0278] As described above, the latch 509 may be provided instead of the comparator 506 , and the signal level may be determined by using the comparison result COMP4 obtained by the comparator 304 .

[0279] The other configurations and operations of the twelfth embodiment may be similar to the corresponding configurations and operations of the eleventh embodiment. In this way, the twelfth embodiment may provide the same advantageous effects as those of the eleventh embodiment.

[0280] (Variant 1)

[0281] Fig.251 is a circuit diagram showing a configuration example of ADC1, ADC2 and their peripheral circuits according to Modification 1 of the present invention. In this modification, ADC1 and ADC2 are provided corresponding to vertical signal lines VSL1 and VSL2, respectively. Switch SW1 is provided between vertical signal lines VSL1 and VSL2. Switching of switch SW1 is performed by timing control section 220.

[0282] In a state where the switch SW1 is turned on, the ADC1 and ADC2 are allowed to perform AD conversion on the pixel signal on either of the vertical signal lines VSL1 and VSL2 in the manner described in the above embodiment. In this case, the advantageous effects of the above embodiment can be produced.

[0283] On the other hand, in the state where the switch SW1 is turned off, ADC1 and ADC2 perform AD conversion on the pixel signals on the vertical signal lines VSL1 and VSL2, respectively. In this case, ADC1 and ADC2 each perform AD conversion using one gain, respectively. Therefore, the image quality is degraded in the dark image area, but simultaneous AD conversion of two pixels can be achieved.

[0284] (Variant 2)

[0285] Fig.26 is a circuit diagram showing a construction example of an ADC and its peripheral circuits according to variant example 2 of the present invention. In this variant example, ADC1_1 and ADC2_1 are provided corresponding to a vertical signal line VSL1. Similarly, ADC1_2 and ADC2_2 are provided corresponding to a vertical signal line VSL2. A switch SW1 is provided between the input end of ADC1_1 and the input end of ADC2_1. A switch SW1 is also provided between the input end of ADC1_2 and the input end of ADC2_2. In addition, a switch SW2 is provided between the input end of ADC2_1 and the adjacent vertical signal line VSL2. The switching of the switch SW1 and the switching of SW2 are performed by the timing control unit 220.

[0286] According to this variation, the adding circuit ADD1 is provided between the output terminal of ADC1_1 and the output terminal of ADC2_1. The adding circuit ADD1 can add the digital signal received from ADC1_1 and the digital signal received from ADC2_1 with a predetermined weight. The adding circuit ADD2 is provided between the output terminal of ADC1_2 and the output terminal of ADC2_2. The adding circuit ADD2 can add the digital signal received from ADC1_2 and the digital signal received from ADC2_2 with a predetermined weight.

[0287] In the state where the switch SW1 is turned on and the switch SW2 is turned off, ADC1_1 and ADC2_1 are allowed to perform AD conversion on the pixel signal on the vertical signal line VSL1 in the manner described in the above embodiment. ADC1_2 and ADC2_2 are allowed to perform AD conversion on the pixel signal on the vertical signal line VSL2 in the manner described in the above embodiment. In this case, the beneficial effects of the above embodiment can be obtained.

[0288] On the other hand, in the state where the switch SW1 is turned off and the switch SW2 is turned on, ADC1_1 and ADC2_1 are allowed to perform AD conversion on the pixel signals of the two pixels received from the vertical signal lines VSL1 and VSL2, respectively, and implement weighted addition. The setting of the weight can be performed using the slopes of the reference signals RMP1 and RMP2 (the gain of ADC1 and the gain of ADC2). By changing the gain of ADC1 and the gain of ADC2, any weight can be set for each of the first and second digital signals.

[0289] In addition, when ADC1_1 and ADC2_1 respectively perform AD conversion of pixel signals of two pixels received from the vertical signal lines VSL1 and VSL2 and implement weighted addition, ADC1_2 and ADC2_2 adjacent to ADC1_1 and ADC2_1 are in a disconnected state.

[0290] (Layout Arrangement)

[0291] FIG. 27A to FIG. 27C Each is a schematic diagram showing the layout arrangement of ADC1 and ADC2 of the present invention. FIG. 27A to FIG. 27C The various components of ADC1 and ADC2 in the embodiment can be interchangeable with each other.

[0292] Fig.27A ADC1 and ADC2 are arranged so that their respective components are concentrated for each gain. ADC1 and ADC2 are arranged along the extending direction D of the vertical signal line VSL. VSL In this way, the layout arrangement of ADC1 and ADC2 can be easily defined. In addition, because ADC1 and ADC2 are arranged along the extension direction D VSL Therefore, the interval (pitch) between adjacent pixel columns can be reduced.

[0293] Fig.27B The ADC1 and ADC2 in the embodiment have their respective components concentrated for each gain, which is different from Fig.27A are arranged similarly. However, Fig.27B ADC1 and ADC2 are in the extending direction D of the vertical signal line VSL. VSLIn this way, the layout of ADC1 and ADC2 can be easily defined. In the case where sufficient spacing between adjacent pixel columns is provided, Fig.27B The layout shown in .

[0294] Fig.27C ADC1 and ADC2 are arranged so that their respective components are arranged along the extending direction D of the vertical signal line VSL. VSL At this point in the longitudinal direction, Fig.27A are arranged similarly. However, Fig.27C ADC1 and ADC2 in the circuit are arranged so that: the same type of components of ADC1 and ADC2 are arranged alternately. For example, the input transistor 312_1 of ADC1 and the input transistor 312_2 of ADC2 are arranged adjacent to each other. The output transistor 315_1 of ADC1 and the output transistor 315_2 of ADC2 are arranged adjacent to each other. Other components are similarly arranged so that the same type of components are arranged adjacent to each other. By arranging the same type of components adjacent to each other as described above, the characteristic matching between the components (semiconductor elements) is improved, and it is beneficial to mask design, process, etc.

[0295] Fig.28A and Fig.28B Each is a schematic diagram showing the layout arrangement of the solid-state imaging element 200 of the present invention. Fig.28A In the embodiment, the peripheral circuits including ADC1 and ADC2 are arranged in the pixel array section 240 in the extending direction D of the vertical signal line VSL. VSL On both sides of the pixel column. In this case, a plurality of vertical signal lines VSL1 and VSL2 are provided for one pixel column. The pixels on the pixel column are connected to one of the plurality of vertical signal lines VSL1 and VSL2. The vertical signal line VSL1 is connected to ADC1 and ADC2 arranged at one side, while the vertical signal line VSL2 is connected to ADC1 and ADC2 arranged at the other side. In this arrangement, two pixel signals on the pixel column can be AD converted simultaneously.

[0296] exist Fig.28B In the embodiment, the peripheral circuits including ADC1 and ADC2 are arranged in the pixel array section 240 in the extending direction D of the vertical signal line VSL. VSL In this case, one vertical signal line VSL is provided for one pixel column. According to this arrangement, the pixel signals on the pixel column are AD-converted one pixel signal at a time. However, the layout area of ​​the peripheral circuit becomes smaller.

[0297] The above-described layout arrangements are presented only as examples, and the arrangement of the solid-state imaging element 200 of the present invention is not limited to these examples.

[0298] <Application example of mobile object>

[0299] The technology according to the present invention (the present technology) is applicable to various types of products. For example, the technology according to the present invention can be implemented as a device to be installed on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, an unmanned aerial vehicle, a ship, or a robot.

[0300] Fig.29 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0301] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.29 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: interface) 12053 are shown.

[0302] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 can function as a control device for the following various devices: a drive force generating device such as an internal combustion engine or a drive motor for generating the drive force of the vehicle; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0303] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 may function as a control device for various devices such as a keyless entry system; a smart key system; a power window device; or various lights such as a headlight, a reverse light, a brake light, a turn signal, or a fog light. In this case, a radio wave transmitted from a portable device or a signal from various switches instead of a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio wave or the signal, and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0304] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the camera section 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera section 12031 to capture an image of the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing for objects such as people, cars, obstacles, traffic signs, text on the road, and the like.

[0305] The imaging unit 12031 is an optical sensor that can receive light and output an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or can be non-visible light such as infrared rays.

[0306] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off.

[0307] Based on the information about the inside and outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), the functions of which include: collision avoidance or collision mitigation of the vehicle, following driving based on vehicle-to-vehicle distance, vehicle constant speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0308] In addition, based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, the microcomputer 12051 can perform coordinated control aimed at achieving automatic driving, for example, in which the vehicle can drive autonomously without relying on the driver's operational control, by controlling the driving force generating device, steering mechanism, braking device, etc.

[0309] In addition, based on the information about the outside of the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can control the headlights to perform coordinated control aimed at preventing glare, such as switching high beam to low beam.

[0310] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of the information. Fig.29 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0311] Fig.30 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0312] exist Fig.30 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0313] Camera units 12101, 12102, 12103, 12104 and 12105 are provided at various locations of the vehicle 12100, such as the front of the vehicle, the side mirrors, the rear bumper and the trunk door, and the upper portion of the windshield in the vehicle compartment. The camera unit 12101 provided at the front of the vehicle and the camera unit 12105 provided at the upper portion of the windshield in the vehicle compartment mainly obtain the front image of the vehicle 12100. The camera units 12102 and 12103 provided at the side mirrors mainly obtain the side image of the vehicle 12100. The camera unit 12104 provided at the rear bumper or the trunk door mainly obtains the rear image of the vehicle 12100. The camera unit 12105 provided at the upper portion of the windshield in the vehicle compartment is mainly used to detect the front vehicle, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0314] By the way, Fig.30Examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 disposed at the front of the vehicle. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 disposed at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 disposed at the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as seen from above can be obtained.

[0315] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0316] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can obtain the distance to each solid object within the camera range 12111 to 12114 and the change of the distance over time (relative speed relative to the vehicle 12100), thereby extracting the following solid object as the front vehicle: the solid object is particularly the closest solid object on the driving route of the vehicle 12100, and the solid object is traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can set the vehicle-to-vehicle distance that should be ensured in advance with the front vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, coordinated control such as automatic driving that enables the vehicle to travel autonomously without relying on the driver's operation can be performed.

[0317] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can extract the classified three-dimensional object data of other three-dimensional objects such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and electric poles, and automatically avoid obstacles using the extracted data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to visually identify. The microcomputer 12051 determines the collision risk used to indicate the degree of danger of collision with each obstacle, and when the collision risk is equal to or exceeds the set value and thus indicates the possibility of collision, the microcomputer 12051 can output a warning to the driver via the audio speaker 12061 or the display unit 12062, or implement forced deceleration or avoidance steering via the drive system control unit 12010. Thereby, the microcomputer 12051 can provide driving assistance for avoiding collisions.

[0318] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the image captured by the camera units 12101 to 12104. For example, such identification of a pedestrian is performed by the following steps: a step of extracting feature points from the image captured by the camera units 12101 to 12104 as infrared cameras; and a step of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the image captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a rectangular contour line for indicating emphasis in a superimposed manner on the identified pedestrian. In addition, the sound / image output unit 12052 may also control the display unit 12062 to display an icon or the like for representing a pedestrian at a desired position.

[0319] An example of a vehicle control system to which the technology according to the present invention is applicable has been described above. The technology according to the present invention can be applied to the camera unit 12031 in the configuration described above. Specifically, Figure 1 The camera device 100 in the embodiment can be applied to the camera unit 12031. By applying the technology of the present invention to the camera unit 12031, a more easily viewed captured image can be obtained. Therefore, the fatigue of the driver can be reduced.

[0320] Note that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the scope of the present invention. In addition, the beneficial effects that the present invention can bring are not limited to the beneficial effects that are only illustrated as examples in this specification. Other beneficial effects can also be provided.

[0321] The present technology may also have the following configurations.

[0322] (1) A solid-state imaging device comprising:

[0323] A first comparator comprising:

[0324] a first input transistor that outputs a first voltage corresponding to the input voltage from a first pixel input to a source of the first input transistor based on a first voltage difference between the input voltage from the first pixel input to a source of the first input transistor and a first reference voltage input to a gate of the first input transistor; and

[0325] a first output transistor that outputs a comparison result between the input voltage and the first reference voltage from a drain of the first output transistor based on a second voltage difference between the input voltage input to the source of the first output transistor and the first voltage input to the gate of the first output transistor, and

[0326] A second comparator comprising:

[0327] a second input transistor that outputs a second voltage corresponding to the input voltage from a drain of the second input transistor based on a third voltage difference between the input voltage input to a source of the second input transistor and a second reference voltage input to a gate of the second input transistor; and

[0328] a second output transistor which outputs a comparison result between the input voltage and the second reference voltage from a drain of the second output transistor based on a fourth voltage difference between the input voltage input to the source of the second output transistor and the second voltage input to the gate of the second output transistor.

[0329] (2) The solid-state imaging device according to (1), wherein:

[0330] The first comparator further comprises:

[0331] a first current source connected to the drain of the first input transistor;

[0332] a first clamping transistor disposed between a source and a drain of the first input transistor;

[0333] a second current source connected to the drain of the first output transistor; and

[0334] a second clamping transistor disposed between a source and a drain of the first output transistor,

[0335] The second comparator further comprises:

[0336] a third current source connected to the drain of the second input transistor;

[0337] a third clamping transistor disposed between the source and the drain of the second input transistor;

[0338] a fourth current source connected to the drain of the second output transistor; and

[0339] a fourth clamping transistor, disposed between a source and a drain of the second output transistor,

[0340] Also, in each of the first to fourth clamping transistors, a gate and a drain are short-circuited to each other.

[0341] (3) The solid-state imaging element according to (1) or (2), wherein:

[0342] The first comparator further comprises:

[0343] A first switch disposed between a gate and a drain of the first input transistor; and

[0344] a second switch, which is arranged between the gate and the drain of the first output transistor, and the second comparator further comprises:

[0345] A third switch provided between the gate and the drain of the second input transistor; and

[0346] A fourth switch is provided between the gate and the drain of the second output transistor.

[0347] (4) The solid-state imaging device according to any one of (1) to (3), wherein

[0348] The first reference voltage and the second reference voltage vary with time at slopes different from each other,

[0349] The solid-state imaging element further comprises:

[0350] a first counter that receives the comparison result from the first comparator, counts a first period from the start of the slope of the first reference voltage to the inversion of the comparison result received from the first comparator, and outputs a first digital signal based on the count value of the first period; and

[0351] a second counter receiving the comparison result from the second comparator, counting a second period from the start of the slope of the second reference voltage to the inversion of the comparison result received from the second comparator, and outputting a second digital signal based on the count value of the second period, and

[0352] The first counter and the second counter operate almost simultaneously.

[0353] (5) The solid-state imaging device according to (4), wherein:

[0354] The slope of the second reference voltage is steeper than the slope of the first reference voltage, and

[0355] The first counter and the second counter measure the first period and the second period, respectively, by using clock signals having substantially the same frequency.

[0356] (6) The solid-state imaging device according to (4) or (5), further comprising:

[0357] A selection unit selects the first digital signal or the second digital signal to synthesize an image.

[0358] (7) The solid-state imaging device according to (2), further comprising:

[0359] a pixel signal line connected between the first pixel and the first comparator and between the first pixel and the second comparator,

[0360] The current flowing through the pixel signal line is the sum of the currents flowing through the first current source to the fourth current source.

[0361] (8) The solid-state imaging device according to any one of (1) to (7), wherein

[0362] When the input voltage and the first reference voltage become substantially equal, the first input transistor outputs the first voltage from the drain of the first input transistor,

[0363] the first output transistor outputting a signal indicating whether a difference between the input voltage and the first voltage exceeds a threshold voltage of the first output transistor as a comparison result between the input voltage and the first reference voltage,

[0364] When the input voltage and the second reference voltage become substantially equal, the second input transistor outputs the second voltage from the drain of the second input transistor, and

[0365] The second output transistor outputs a signal indicating whether a difference between the input voltage and the second voltage exceeds a threshold voltage of the second output transistor as a comparison result between the input voltage and the second reference voltage.

[0366] (9) The solid-state imaging device according to any one of (1) to (8), further comprising:

[0367] a first reference voltage supply unit, which supplies the first reference voltage;

[0368] a first auto-zero capacitor provided between the gate of the first input transistor and the first reference voltage supply unit;

[0369] a first buffer provided between the first reference voltage supply unit and the first auto-zero capacitor;

[0370] a second reference voltage supply unit, which supplies the second reference voltage;

[0371] A second auto-zero capacitor provided between the gate of the second input transistor and the second reference voltage supply section; and

[0372] A second buffer is provided between the second reference voltage supply unit and the second auto-zero capacitor.

[0373] (10) The solid-state imaging device according to any one of (1) to (9), wherein

[0374] Each of the first input transistor, the second input transistor, the first output transistor and the second output transistor is a P-type transistor.

[0375] (11) The solid-state imaging device according to (2), wherein:

[0376] Each of the first to fourth clamping transistors is a P-type transistor having a gate and a drain short-circuited to each other, and

[0377] The solid-state imaging element further includes fifth to eighth clamp transistors which are connected in parallel to the first to fourth clamp transistors, respectively, and each of which is constituted by an N-type transistor.

[0378] (12) The solid-state imaging device according to (2), wherein:

[0379] The first current source to the fourth current source respectively include:

[0380] first to fourth current source transistors, which are respectively provided between the drains of the first input transistor, the first output transistor, the second input transistor, and the second output transistor and a predetermined reference terminal;

[0381] first to fourth capacitors connected between the gates of the first to fourth current source transistors and the reference terminal, respectively; and

[0382] The first to fourth sample-and-hold switches are connected to the gates of the first to fourth current source transistors, respectively.

[0383] (13) The solid-state imaging device according to any one of (1) to (12), further comprising:

[0384] a first logic gate connected to the drain of the first output transistor; and

[0385] A second logic gate is connected to the drain of the second output transistor.

[0386] (14) The solid-state imaging device according to any one of (1) to (13), further comprising:

[0387] a pixel signal line connected between the first pixel and the first comparator and between the first pixel and the second comparator; and

[0388] A fifth current source is connected to the pixel signal line.

[0389] (15) The solid-state imaging device according to any one of (1) to (14), further comprising:

[0390] a fifth capacitor provided between the drain of the first input transistor and the gate of the first output transistor;

[0391] a fifth switch, arranged between the gate and the drain of the first output transistor;

[0392] a sixth capacitor provided between the drain of the second input transistor and the gate of the second output transistor; and

[0393] A sixth switch is provided between the gate and the drain of the second output transistor.

[0394] (16) The solid-state imaging device according to any one of (1) to (15), further comprising:

[0395] a first buffer transistor connected between a power supply and a source of the first output transistor, a gate of the first buffer transistor connected to a source of the first input transistor; and

[0396] The second buffer transistor is connected between the power supply and the source of the second output transistor, and the gate of the second buffer transistor is connected to the source of the second input transistor.

[0397] (17) The solid-state imaging device according to any one of (1) to (16), further comprising:

[0398] a common reference voltage supply unit that supplies a common reference voltage;

[0399] a first auto-zero capacitor provided between the gate of the first input transistor and the common reference voltage supply unit;

[0400] a voltage dividing capacitor connected between the gate of the first input transistor and a predetermined reference terminal; and

[0401] a second auto-zero capacitor provided between the gate of the second input transistor and the common reference voltage supply section,

[0402] wherein the first auto-zero capacitor and the voltage-dividing capacitor divide the common reference voltage, and transmit the divided common reference voltage as the first reference voltage to the gate of the first input transistor, and

[0403] The second auto-zero capacitor transfers the common reference voltage as the second reference voltage to the gate of the second input transistor.

[0404] (18) The solid-state imaging device according to (6), wherein:

[0405] The selection unit includes:

[0406] a digital comparator that compares one or both of the first digital signal and the second digital signal with a threshold value;

[0407] a register storing the threshold value; and

[0408] a multiplexer that selects the first digital signal or the second digital signal based on the comparison result received from the digital comparator, and outputs the selected digital signal as a pixel signal of the first pixel together with the comparison result.

[0409] (19) The solid-state imaging device according to (18), wherein:

[0410] The slope of the second reference voltage is steeper than the slope of the first reference voltage,

[0411] In the event that one or both of the first digital signal and the second digital signal are below the threshold, the multiplexer selects the first digital signal,

[0412] In the event that one or both of the first digital signal and the second digital signal are above the threshold, the multiplexer selects the second digital signal, and

[0413] The solid-state imaging element further includes a calculation section that converts the first digital signal based on a ratio of a slope of the first reference voltage to a slope of the second reference voltage.

[0414] (20) The solid-state imaging device according to any one of (1) to (19), further comprising:

[0415] A third comparator comprising:

[0416] a third input transistor that outputs a third voltage corresponding to the input voltage from a drain of the third input transistor based on a fifth voltage difference between the input voltage input to a source of the third input transistor and a third reference voltage input to a gate of the third input transistor; and

[0417] a third output transistor which outputs a comparison result between the input voltage and the third reference voltage from a drain of the third output transistor based on a sixth voltage difference between the input voltage input to the source of the third output transistor and the third voltage input to the gate of the third output transistor.

Claims

1. A solid-state imaging element, comprising: A first comparator comprising: a first input transistor that outputs a first voltage corresponding to the input voltage from the first pixel input to the source of the first input transistor based on a first voltage difference between the input voltage from the first pixel input to the source of the first input transistor and a first reference voltage input to the gate of the first input transistor; and a first output transistor that outputs a comparison result between the input voltage and the first reference voltage from a drain of the first output transistor based on a second voltage difference between the input voltage input to the source of the first output transistor and the first voltage input to the gate of the first output transistor, and A second comparator comprising: a second input transistor that outputs a second voltage corresponding to the input voltage from a drain of the second input transistor based on a third voltage difference between the input voltage input to a source of the second input transistor and a second reference voltage input to a gate of the second input transistor; and a second output transistor which outputs a comparison result between the input voltage and the second reference voltage from a drain of the second output transistor based on a fourth voltage difference between the input voltage input to the source of the second output transistor and the second voltage input to the gate of the second output transistor.

2. The solid-state imaging element according to claim 1, wherein The first comparator further comprises: a first current source connected to the drain of the first input transistor; a first clamping transistor disposed between a source and a drain of the first input transistor; a second current source connected to the drain of the first output transistor; and a second clamping transistor disposed between a source and a drain of the first output transistor, The second comparator further comprises: a third current source connected to the drain of the second input transistor; a third clamping transistor disposed between the source and the drain of the second input transistor; a fourth current source connected to the drain of the second output transistor; and a fourth clamping transistor, disposed between a source and a drain of the second output transistor, Also, in each of the first to fourth clamping transistors, a gate and a drain are short-circuited to each other.

3. The solid-state imaging element according to claim 1, wherein The first comparator further comprises: A first switch disposed between a gate and a drain of the first input transistor; and a second switch, which is arranged between the gate and the drain of the first output transistor, and the second comparator further comprises: A third switch provided between the gate and the drain of the second input transistor; and A fourth switch is provided between the gate and the drain of the second output transistor.

4. The solid-state imaging element according to claim 1, wherein The first reference voltage and the second reference voltage vary with time at slopes different from each other, The solid-state imaging element further comprises: a first counter that receives the comparison result from the first comparator, counts a first period from the start of the slope of the first reference voltage to the inversion of the comparison result received from the first comparator, and outputs a first digital signal based on the count value of the first period; and a second counter receiving the comparison result from the second comparator, counting a second period from the start of the slope of the second reference voltage to the inversion of the comparison result received from the second comparator, and outputting a second digital signal based on the count value of the second period, and The first counter and the second counter operate almost simultaneously.

5. The solid-state imaging element according to claim 4, wherein: The slope of the second reference voltage is steeper than the slope of the first reference voltage, and The first counter and the second counter measure the first period and the second period, respectively, by using clock signals having substantially the same frequency.

6. The solid-state imaging element according to claim 4, further comprising: A selection unit selects the first digital signal or the second digital signal to synthesize an image.

7. The solid-state imaging element according to claim 2, further comprising: a pixel signal line connected between the first pixel and the first comparator and between the first pixel and the second comparator, The current flowing through the pixel signal line is the sum of the currents flowing through the first current source to the fourth current source.

8. The solid-state imaging element according to claim 1, wherein When the input voltage and the first reference voltage become substantially equal, the first input transistor outputs the first voltage from the drain of the first input transistor, the first output transistor outputting a signal indicating whether a difference between the input voltage and the first voltage exceeds a threshold voltage of the first output transistor as a comparison result between the input voltage and the first reference voltage, When the input voltage and the second reference voltage become substantially equal, the second input transistor outputs the second voltage from the drain of the second input transistor, and The second output transistor outputs a signal indicating whether a difference between the input voltage and the second voltage exceeds a threshold voltage of the second output transistor as a comparison result between the input voltage and the second reference voltage and each other.

9. The solid-state imaging element according to claim 1, further comprising: a first reference voltage supply unit, which supplies the first reference voltage; a first auto-zero capacitor provided between the gate of the first input transistor and the first reference voltage supply unit; a first buffer provided between the first reference voltage supply unit and the first auto-zero capacitor; a second reference voltage supply unit, which supplies the second reference voltage; a second auto-zero capacitor provided between the gate of the second input transistor and the second reference voltage supply section; and A second buffer is provided between the second reference voltage supply unit and the second auto-zero capacitor.

10. The solid-state imaging element according to claim 1, wherein Each of the first input transistor, the second input transistor, the first output transistor and the second output transistor is a P-type transistor.

11. The solid-state imaging element according to claim 2, wherein: Each of the first to fourth clamping transistors is a P-type transistor having a gate and a drain short-circuited to each other, and The solid-state imaging element further includes fifth to eighth clamp transistors which are connected in parallel to the first to fourth clamp transistors, respectively, and each of which is constituted by an N-type transistor.

12. The solid-state imaging element according to claim 2, wherein: The first current source to the fourth current source respectively include: first to fourth current source transistors, which are respectively provided between the drains of the first input transistor, the first output transistor, the second input transistor, and the second output transistor and a predetermined reference terminal; first to fourth capacitors connected between the gates of the first to fourth current source transistors and the reference terminal, respectively; and The first to fourth sample-and-hold switches are connected to the gates of the first to fourth current source transistors, respectively.

13. The solid-state imaging element according to claim 1, further comprising: a first logic gate connected to the drain of the first output transistor; and A second logic gate is connected to the drain of the second output transistor.

14. The solid-state imaging element according to claim 1, further comprising: a pixel signal line connected between the first pixel and the first comparator and between the first pixel and the second comparator; and A fifth current source is connected to the pixel signal line.

15. The solid-state imaging element according to claim 1, further comprising: a fifth capacitor disposed between the drain of the first input transistor and the gate of the first output transistor; a fifth switch, arranged between the gate and the drain of the first output transistor; a sixth capacitor provided between the drain of the second input transistor and the gate of the second output transistor; and A sixth switch is provided between the gate and the drain of the second output transistor.

16. The solid-state imaging element according to claim 1, further comprising: a first buffer transistor connected between a power supply and a source of the first output transistor, wherein a gate of the first buffer transistor is connected to a source of the first input transistor; and The second buffer transistor is connected between the power supply and the source of the second output transistor, and the gate of the second buffer transistor is connected to the source of the second input transistor.

17. The solid-state imaging element according to claim 1, further comprising: a common reference voltage supply unit that supplies a common reference voltage; a first auto-zero capacitor provided between the gate of the first input transistor and the common reference voltage supply unit; a voltage dividing capacitor connected between the gate of the first input transistor and a predetermined reference terminal; and a second auto-zero capacitor provided between the gate of the second input transistor and the common reference voltage supply section, wherein the first auto-zero capacitor and the voltage-dividing capacitor divide the common reference voltage, and transmit the divided common reference voltage as the first reference voltage to the gate of the first input transistor, and The second auto-zero capacitor transfers the common reference voltage as the second reference voltage to the gate of the second input transistor.

18. The solid-state imaging element according to claim 6, wherein: The selection unit includes: a digital comparator that compares one or both of the first digital signal and the second digital signal with a threshold value; a register storing the threshold value; and A multiplexer that selects the first digital signal or the second digital signal based on the comparison result received from the digital comparator, and outputs the selected digital signal as a pixel signal of the first pixel together with the comparison result.

19. The solid-state imaging element according to claim 18, wherein The slope of the second reference voltage is steeper than the slope of the first reference voltage, In the event that one or both of the first digital signal and the second digital signal are below the threshold, the multiplexer selects the first digital signal, In the event that one or both of the first digital signal and the second digital signal are above the threshold, the multiplexer selects the second digital signal, and The solid-state imaging element further includes a calculation section that converts the first digital signal based on a ratio of a slope of the first reference voltage to a slope of the second reference voltage.

20. The solid-state imaging element according to any one of claims 1 to 19, further comprising: A third comparator comprising: a third input transistor that outputs a third voltage corresponding to the input voltage from a drain of the third input transistor based on a fifth voltage difference between the input voltage input to a source of the third input transistor and a third reference voltage input to a gate of the third input transistor; and a third output transistor which outputs a comparison result between the input voltage and the third reference voltage from a drain of the third output transistor based on a sixth voltage difference between the input voltage input to the source of the third output transistor and the third voltage input to the gate of the third output transistor.

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