A method and system for switching chip test modes

Abstract

The embodiment of the present application relates to a method and system for switching chip test modes, which are applied to a monitoring unit in a chip. The method includes obtaining test mode data through a first functional pin and matching the test mode data with preset first data; after successful matching, receiving and parsing test mode selection data through a second functional pin to obtain test mode selection type data and guiding the chip to enter the corresponding test mode according to the test mode selection type data; after the chip enters the test mode, the monitoring unit changes from the on state to the off state, and after the test is completed, the monitoring unit changes from the off state to the on state. The first functional pin and the second functional pin can be multiplexed as test pins in the test mode. The chip test mode switching method and system provided by the embodiment of the present application can enable the chip to accurately enter the test mode and operate stably in the test mode without increasing the chip pins.

Description

Technical Field

[0001] This application relates to the field of testing technologies, and in particular, to a method and system for switching chip test modes. Background Art

[0002] A chip can enter the test mode using dedicated pins or functional pins. The advantage of dedicated pins is that they are independent of functional pins and do not introduce possible misoperations. The disadvantage is that dedicated pins need to be added, which increases the additional test cost. The advantage of the method of multiplexing pins is that it can reduce the number of pins. The disadvantage is that in the functional test mode, there may be a situation of accidentally entering the test mode, affecting the test process.

[0003] In a solution of the prior art, the chip logic generates an internal delay reset signal when powered on or under the action of external pins. Within the delay window, the monitoring logic is in the working state, and other logics are in the reset state. When the monitoring logic detects that the serial code stream matches the reserved test code stream KEY, the test mode is locked and the test mode continues to be maintained after the delay reset is withdrawn. When the monitoring logic detects that the serial code stream does not match the reserved test code stream KEY, the monitoring logic fails, and all logics enter the normal logic test mode after the delay reset is withdrawn. There are two problems with this solution: one is that the test mode can only be entered within the monitoring time window. Although the probability of mis-triggering is reduced, the difficulty of entering the test mode is also increased, and an extremely accurate matching window is required; the other is that the test mode cannot be switched between different test modes after entering the test mode.

[0004] In another prior art solution, the chip is determined whether to enter the test mode by judging the input voltage. After the voltage condition is satisfied, it is judged whether the data signal received by the data port is consistent with the preset signal password. Only during the reception of the first preset number of clock signals, when the data signal received by the data port is consistent with the preset signal password, the chip enters the test mode. In this way, by setting two test conditions, the possibility of the chip accidentally entering the test mode during normal use can be reduced. However, there are also two problems. One is that it is necessary to obtain the port input voltage through hardware as the first test condition, which requires additional costs; the other is that using the input point as the first test condition cannot greatly avoid the probability of accidentally entering the test mode in the functional test mode.

[0005] In addition, a method for entering a chip test mode disclosed in a Chinese patent with the publication number CN112595967A. The chip in its technical solution includes an SPIS module, a SCAN MODE LOGIC module, and a BUS MUX module. SPIS is a receiving command logic circuit that receives input commands conforming to the SPI protocol through four interfaces IO1 to IO4. The SPIS module contains test signal (TEST_EN) processing logic. In this patented technology, IO1, IO2, and IO3 respectively correspond to the three signals SCK, CSN, and MOSI in the SPI protocol. By multiplexing the SPIS interface, when a preset characteristic value is received, it is determined as an Enable command, and at the same time, the CPU is bypassed, and the test mode is officially entered. Then, the SPI is continued to be used to convert data commands into bus operations, using SPI protocol instructions, bypassing the CPU path, using the receiving command logic circuit as a command pass, and converting the commands from the receiving command logic circuit into bus read and write operations to enter the test mode of the chip and other technical means to make the chip enter the test mode. However, there are the following problems to be improved in this solution:

[0006] 1. Entering through multiplexing the SPIS interface requires 3 pins, while in the actual functional test process, the functional pins should be occupied as few as possible to test as many normal functions as possible.

[0007] 2. It only supports the functional test mode and the SCAN Mode logic, that is, bypasses the CPU and receives bus read and write commands through SPIS; in the SCAN mode, the 3 pins of SPIS cannot be multiplexed as scan pins.

[0008] 3. When used for ATE tests (such as SCAN tests), the SPIS module cannot be detected, resulting in a reduction in the test coverage rate of the entire chip.

[0009] 4. There is a problem of low reliability of the preset characteristic value. When SPIS is used as a normal interface, it cannot be guaranteed that the preset characteristic value will not be received, especially when an abnormality occurs. This will cause the chip to enter the test mode by mistake and bypass the CPU, resulting in system abnormalities and crashes. This method will affect the normal functions of the chip. Summary of the Invention

[0010] The embodiments of the present application provide a method and system for switching a chip test mode, which can enable the chip to accurately enter the test mode and operate stably in the test mode without increasing the chip pins.

[0011] The above object of the embodiments of the present application is achieved through the following technical solutions:

[0012] In a first aspect, an embodiment of the present application provides a method for switching chip test modes, which is applied to a monitoring unit in a chip and multiplexes two functional pins of the chip, including:

[0013] In response to a clock signal obtained through a first functional pin, obtain test mode data through the first functional pin and match the test mode data with preset first data;

[0014] After the test mode data successfully matches the preset first data, receive test mode selection data through a second functional pin;

[0015] Analyze the test mode selection data to obtain test mode selection type data;

[0016] Guide the chip to enter the corresponding test mode according to the test mode selection type data;

[0017] After the chip enters the test mode, it changes from the on state to the off state; and

[0018] After the test is completed, in response to the obtained reset instruction, change from the off state to the on state;

[0019] Wherein, after entering the test mode, the first functional pin and the second functional pin can be multiplexed as test pins in the test mode;

[0020] The reset instruction is different from the timing in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data.

[0021] In a possible implementation manner of the first aspect, the test mode includes a SCAN test mode, a BIST test mode, and an analog test mode.

[0022] In a possible implementation manner of the first aspect, both the test mode data and the test mode selection data are received through multiplexed functional pins.

[0023] In a second aspect, an embodiment of the present application provides a method for switching chip test modes, which is applied to a monitoring unit in a chip and multiplexes two functional pins of the chip, including:

[0024] In response to the test mode data obtained through the first functional pin, read the test mode data stored in the non-volatile storage unit, and the test mode data includes allowed-to-enter test mode data and prohibited-to-enter test mode data;

[0025] When the test mode data stored in the non-volatile storage unit is allowed-to-enter test mode data, match the test mode data with preset first data;

[0026] After the test mode data successfully matches the pre-set first data, receive the test mode selection data through the second function pin;

[0027] Analyze the test mode selection data to obtain the test mode selection type data;

[0028] Guide the chip to enter the corresponding test mode according to the test mode selection type data;

[0029] After the chip enters the test mode, it changes from the on state to the off state; and

[0030] After the test is completed, in response to the obtained reset instruction, change from the off state to the on state;

[0031] Among them, after entering the test mode, the first function pin and the second function pin can be multiplexed as test pins in the test mode;

[0032] The reset instruction is different from the timing in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data;

[0033] The test mode data stored in the non-volatile storage unit can be modified by burning, and the non-volatile storage unit stores data allowing entry into the test mode or data prohibiting entry into the test mode.

[0034] In a possible implementation manner of the second aspect, the test mode includes a SCAN test mode, a BIST test mode, and an analog test mode.

[0035] In a possible implementation manner of the second aspect, both the test mode data and the test mode selection data are received through the multiplexed function pins.

[0036] In a third aspect, an embodiment of the present application provides a chip test mode switching device, which is applied to a monitoring unit in the chip and multiplexes two function pins of the chip, including:

[0037] A first processing unit, in response to the clock signal obtained through the first function pin, obtains the test mode data through the first function pin and matches the test mode data with the pre-set first data;

[0038] A first communication unit, used to receive the test mode selection data through the second function pin after the test mode data successfully matches the pre-set first data;

[0039] A first parsing unit, used to parse the test mode selection data to obtain the test mode selection type data;

[0040] A second processing unit, used to guide the chip to enter the corresponding test mode according to the test mode selection type data;

[0041] A first state conversion unit, configured to convert the monitoring unit from an on state to an off state after the chip enters the test mode; and

[0042] A second state conversion unit, configured to convert the monitoring unit from an off state to an on state in response to an obtained reset instruction after the test is completed;

[0043] Wherein, after entering the test mode, the first functional pin and the second functional pin can be multiplexed as test pins in the test mode;

[0044] The reset instruction is different from the timing in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data.

[0045] In a fourth aspect, an embodiment of the present application provides a chip test mode switching device, which is applied to a monitoring unit in a chip and multiplexes two functional pins of the chip, including:

[0046] A third processing unit, configured to read test mode data stored in the non-volatile storage unit in response to a clock signal obtained through the first functional pin, where the test mode data includes test mode data allowing entry and test mode data prohibiting entry;

[0047] A fourth processing unit, configured to obtain test mode data through the first functional pin and match the test mode data with preset first data when the test mode data stored in the non-volatile storage unit is test mode data allowing entry;

[0048] A fifth processing unit, configured to match the test mode data with preset first data when the test mode data stored in the non-volatile storage unit is test mode data allowing entry;

[0049] A second communication unit, configured to receive test mode selection data through the second functional pin after the test mode data and the preset first data match successfully;

[0050] A second parsing unit, configured to parse the test mode selection data to obtain test mode selection type data;

[0051] A sixth processing unit, configured to guide the chip to enter a corresponding test mode according to the test mode selection type data;

[0052] A third state conversion unit, configured to convert the monitoring unit from an on state to an off state after the chip enters the test mode; and

[0053] A fourth state conversion unit, configured to convert the monitoring unit from an off state to an on state in response to an obtained reset instruction after the test is completed;

[0054] After entering the test mode, the first function pin and the second function pin can be multiplexed as test pins in the test mode;

[0055] The reset instruction is different from the timing sequence that appears in the normal test pin timing sequence, and the test mode selection data is generated at the clock edge of the test mode data;

[0056] The test mode data stored in the non-volatile storage unit can be modified by programming. The non-volatile storage unit stores data that allows or prohibits entering the test mode.

[0057] In a fifth aspect, an embodiment of the present application provides a chip test mode switching system, which is applied to a monitoring unit in a chip and multiplexes two function pins of the chip. The system includes:

[0058] One or more memories for storing instructions; and

[0059] One or more processors for calling and running the instructions from the memory and executing the chip test mode switching method as described in the first aspect and any possible implementation manners of the first aspect.

[0060] In a sixth aspect, an embodiment of the present application provides a chip test mode switching system, which is applied to a monitoring unit in a chip and multiplexes two function pins of the chip. The system includes:

[0061] One or more memories for storing instructions; and

[0062] One or more processors for calling and running the instructions from the memory and executing the chip test mode switching method as described in the second aspect and any possible implementation manners of the second aspect.

[0063] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, which includes:

[0064] A program, when the program is run by a processor, the chip test mode switching method as described in the first aspect and any possible implementation manners of the first aspect is executed.

[0065] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, which includes:

[0066] A program, when the program is run by a processor, the chip test mode switching method as described in the second aspect and any possible implementation manners of the second aspect is executed.

[0067] In a ninth aspect, an embodiment of the present application provides a computer program product, including program instructions, which, when run on a computing device, execute the chip test mode switching method as described in the first aspect and any possible implementation manners of the first aspect.

[0068] In a tenth aspect, an embodiment of the present application provides a computer program product, including program instructions, which, when run on a computing device, execute the chip test mode switching method as described in the second aspect and any possible implementation manners of the second aspect.

[0069] In an eleventh aspect, an embodiment of the present application provides a chip, which includes a processor, a monitoring unit, and a data interface. The monitoring unit receives data through the data interface to execute the chip test mode switching method as described in the first aspect and any possible implementation manners of the first aspect.

[0070] In a twelfth aspect, an embodiment of the present application provides a chip, which includes a processor, a monitoring unit, and a data interface. The monitoring unit receives data through the data interface to execute the chip test mode switching method as described in the second aspect and any possible implementation manners of the second aspect.

[0071] Overall, the chip test mode switching method provided by the embodiment of the present application is implemented by means of the monitoring unit in the chip. The data received by the detection unit is divided into three parts, namely a start signal, test mode data, and test mode selection data. After receiving the start signal, the test mode data and test mode selection data are obtained. The test mode data and test mode selection data must be successfully matched with the prefabricated data in the monitoring unit before the chip can enter the corresponding test mode. It can ensure that the test mode does not affect the normal function of the chip and greatly improves the reliability of the chip.

[0072] Since only TM_CLK and TM_DAT are used, only two pins are required. The reduction of pins means different costs and can also increase the number of chips that can be tested simultaneously during the ATE test of the chip (i.e., the number of chips that can be tested by the test machine at the same time). And after the TM_CLK and TM_DAT pins enter the test mode, these two pins can be reused as test mode pins, which can further improve the test coverage.

[0073] The dedicated mode detection circuit (TM_DET) module can be used for both ATE tests (such as SCAN / BIST / FLASH BIST / Function, etc.) and laboratory functional tests. It uses very few logic functions and will not reduce the test coverage rate of the entire chip due to the mode detection circuit. And it can support entering different test modes, support various tests of ATE, the test mode can be extended, and it can also support the switching between different test modes. Description of the Drawings

[0074] Figure 1 It is a corresponding relationship diagram of each signal in the time series provided by the embodiment of the present application.

[0075] Figure 2 It is a schematic block diagram of the steps of a chip test mode switching method provided by the embodiment of the present application.

[0076] Figure 3 It is a timing diagram provided by the embodiment of the present application.

[0077] Figure 4 It is a schematic block diagram of the steps of another chip test mode switching method provided by the embodiment of the present application.

[0078] Figure 5 It is a schematic diagram of the process of the chip entering the test mode when a non-volatile storage unit intervenes provided by the embodiment of the present application.

[0079] Figure 6 Based on Figure 5 It is a schematic diagram of the process of the chip not entering the test mode when a non-volatile storage unit intervenes given. Detailed Description of the Embodiment

[0080] The technical solutions in the present application will be further described in detail below with reference to the accompanying drawings.

[0081] The chip test mode switching method provided by the embodiment of the present application uses test mode data and test mode selection data to guide the chip into the test mode. The specific method is to add a monitoring unit in the chip. The test mode data sent by the tester is sent to the monitoring unit for judgment, and then the chip is guided into the corresponding test mode according to the test mode selection type data.

[0082] Please refer to Figure 1 and Figure 2 The embodiment of the present application provides a chip test mode switching method, which is applied to the monitoring unit in the chip and multiplexes two functional pins of the chip, including the following steps:

[0083] S101, in response to the clock signal obtained through the first functional pin, obtain the test mode data through the first functional pin and match the test mode data with the preset first data;

[0084] S102, after the test mode data matches the preset first data successfully, receive the test mode selection data through the second functional pin;

[0085] S103, analyze the test mode selection data to obtain the test mode selection type data;

[0086] S104. According to the type data of the test mode selection, guide the chip to enter the corresponding test mode.

[0087] S105. After the chip enters the test mode, change from the on state to the off state; and

[0088] S106. After the test is completed, in response to the obtained reset instruction, change from the off state to the on state;

[0089] Among them, after entering the test mode, the first function pin and the second function pin can be multiplexed as test pins in the test mode;

[0090] The reset instruction is different from the timing sequence that appears in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data.

[0091] Specifically, in step S101, the tester generates a test mode monitoring clock and sends the test mode monitoring clock to the monitoring unit inside the chip through a pin of the chip. There are rising edge signals and falling edge signals in the test mode monitoring clock. The monitoring unit can select one of the rising edge signals or falling edge signals as the start signal to start receiving the test mode data sent by the tester.

[0092] In some possible implementation manners, the clock signal is a rising edge signal.

[0093] In some other possible implementation manners, the clock signal is a falling edge signal.

[0094] The test mode data sent by the tester is transmitted to the monitoring unit inside the chip through the second pin of the chip. Then, the monitoring unit matches the test mode data with the pre-set first data. If the match is successful, the monitoring unit is ready to guide the chip into the test mode.

[0095] Specifically, the monitoring unit will output a mode control signal to the chip according to the matching result to guide the chip into the test mode. Otherwise, the chip remains in the original mode and does not change.

[0096] The pre-set first data is stored inside the monitoring unit. If the match with the test mode data obtained through the function pin is successful, enter step S102.

[0097] In step S102, the monitoring unit will receive the test mode selection data through the second function pin, and then parse the test mode selection data to obtain the test mode selection type data, which is the content in step S103. The role of the test mode selection type data is to determine which test mode the monitoring unit needs to guide the chip into.

[0098] It should be understood that on a chip with very few chip pins, if these two functional pins (tm_clk and tm_dat) are only used for mode monitoring, there may be a problem of insufficient test pins. Therefore, for the multiplexing of the two functional pins, it can also be the multiplexing of the test pins in the test mode. That is, for the multiplexed chip pins, after the function of mode monitoring is completed, they are converted into test pins to participate in the chip test process. This not only reduces the need for pins but also further increases the number of chips that can be tested simultaneously by ATE, that is, it reduces the test cost.

[0099] For example, there are four test mode selection data, which are 1, 2, 3, and 4 respectively. Similarly, there are also four test mode selection type data, which are 1, 2, 3, and 4 respectively. For the test mode selection type data obtained in step S103, if it is 3, then in step S104, the monitoring unit will guide the chip to enter the corresponding test mode according to the test mode selection type data.

[0100] In step S105, after the chip enters the test mode, the monitoring unit in the chip changes from the enabled state to the disabled state, which means that the monitoring unit no longer receives externally input data. This fundamentally solves the problem that the chip jumps out of the test mode or accidentally enters other test modes, and can make the chip run stably in the test mode until the test is completed. Moreover, when these two functional pins (the first functional pin and the second functional pin mentioned in step S101) are used as test functional pins, there will be no problem of jumping out of or accidentally entering other test modes due to pin switching.

[0101] After the test is completed, step S106 is executed. In this step, after the test is completed, in response to the obtained reset instruction, the monitoring unit in the chip changes from the disabled state to the enabled state. At this time, the monitoring unit can continue to receive the data transmitted by the first functional pin and the second functional pin, for example, enter other test modes or enter the normal user mode.

[0102] The functions of step S105 and step S106 are to ensure that the chip will not be affected by interference signals after entering the test mode, and can ensure the smooth progress of the test mode.

[0103] The reset instruction mentioned above is different from the timing that appears in the normal test pin timing, that is, the reset instruction is a special timing, and the purpose is to ensure that the monitoring unit in the chip will not accidentally change from the disabled state to the enabled state during the chip test process.

[0104] It should be understood that the timing can be passed through Figure 3To assist in understanding, the timings that can occur in the normal test pin timings can be the first to the third (from top to bottom), and the timing of the reset instruction is the fourth. Of course, this is only an exemplary illustration, meaning that the timing of the reset instruction and the timings that occur in the normal test pin timings are significantly different, with the aim of avoiding misidentification.

[0105] Regarding the test mode data and test mode selection data mentioned above, the test mode selection data is generated at the clock edge of the test mode data. Here, the clock edge can be the rising edge or the falling edge. Considering from the perspective of signal generation, the test mode data and test mode selection data are synchronous, that is, the two will appear simultaneously. If only one appears or two appear simultaneously but the timings in the time sequence are incorrect, the monitoring unit in the chip will not guide the chip into the test mode.

[0106] Considering from the perspective of safety, after imposing timing requirements on the test mode data and test mode selection data in the time sequence, higher safety can be obtained, significantly reducing the possibility of the chip accidentally entering the test mode.

[0107] Regarding the pin multiplexing, it can also be understood in this way. The number of data channels on the test machine platform is fixed. For example, there are one hundred and fifty data channels. If the SPI protocol or other similar protocols are used, more data channels will be occupied. For example, the SPI protocol requires three pins, so the number of chips that can be tested in a single test is fifty.

[0108] Using the chip test mode switching method disclosed in the embodiments of the present application, a single chip only needs to occupy two data channels, that is, the number of chips that can be tested in a single test is seventy-five. Obviously, the number of chips that can be tested in a single test is significantly increased. Additionally, considering that it is impossible to achieve the interlocking of two signals using a single data channel, therefore, the method of multiplexing two functional pins on the chip is more appropriate because it can reduce the cost of chip testing.

[0109] The chip test mode switching method disclosed in the embodiments of the present application uses TM_CLK and TM_DAT, and only requires two pins. The reduction in pins means different costs and can also increase the number of chips that can be tested simultaneously during the chip ATE test (i.e., the number of chips that the test machine platform can test simultaneously).

[0110] Overall, the chip test mode switching method provided by the embodiments of the present application is implemented with the help of the monitoring unit in the chip. The data received by the detection unit is divided into three parts, namely the start signal, test mode data, and test mode selection data. After receiving the start signal, it starts to obtain the test mode data and test mode selection data.

[0111] The test mode data and the test mode selection data must be successfully matched with the prefabricated data in the monitoring unit before the chip can enter the corresponding test mode.

[0112] From an implementation perspective, the test mode data can be sent to the monitoring unit at any time, which helps to reduce the difficulty for the chip to enter the detection test mode. Additionally, the test mode selection data is added as a supplement, that is, only when both the test mode data and the test mode selection data can be matched, the monitoring unit can guide the chip into the corresponding test mode.

[0113] In terms of the entry difficulty, after the test mode data and the test mode selection data are sent to the monitoring unit, the monitoring unit guides the chip. This method no longer requires a very accurate matching time window, which can reduce the difficulty for the chip to enter the corresponding test mode corresponding to the test mode selection data, and can also ensure that the test mode does not affect the normal function of the chip, greatly improving the chip reliability.

[0114] Moreover, the test mode data and the test mode selection data must meet the timing requirements in the time series before the monitoring unit in the chip can guide the chip into the test mode in the subsequent process.

[0115] For the test equipment, only two types of data, namely the test mode data and the test mode selection type data, need to be stored, and then sent to the monitoring unit inside the chip through the function pins according to the actual usage requirements, so that the chip can enter the corresponding test mode.

[0116] As a specific implementation of the chip test mode switching method provided by the application, the test modes include the SCAN test mode, the BIST test mode, and the analog test mode, which are introduced separately below.

[0117] SCAN test mode: As one of the important methods for testing digital integrated circuits, Scan Chain (scan chain test) can effectively screen out defective chips and improve product quality. In this mode, the SCAN TEST test probe extends to any corner of the chip, and the test target is the standard cells in the circuit, including combinational and sequential logic.

[0118] BIST test mode: The BIST mode is memory built-in self test, that is, memory built-in self-test.

[0119] Analog test mode: It is used to test the functions of analog modules.

[0120] In addition, the chip test mode switching method disclosed in the embodiments of the present application can be used for ATE tests (such as SCAN / BIST / FLASH BIST / Function, etc.) and also for laboratory function tests. Moreover, the dedicated mode detection circuit (TM_DET) module uses very few logic functions and will not reduce the test coverage of the entire chip due to the mode detection circuit. It also supports entering different test modes, supports various tests of ATE, and the test modes can be extended. And it supports switching between different test modes.

[0121] As a specific implementation of the chip test mode switching method provided by the application, both the test mode data and the test mode selection data are received through multiplexed function pins.

[0122] Please refer to Figure 4 , the embodiments of the present application also provide another chip test mode switching method, which is applied to the monitoring unit in the chip and multiplexes two function pins of the chip, and includes the following steps:

[0123] S201, in response to the clock signal obtained through the first function pin, read the test mode data stored in the non-volatile storage unit, where the test mode data includes the test mode data allowing entry and the test mode data prohibiting entry;

[0124] S202, when the test mode data stored in the non-volatile storage unit is the test mode data allowing entry, obtain the test mode data through the first function pin and match the test mode data with the preset first data;

[0125] S203, after the test mode data matches the preset first data successfully, receive the test mode selection data through the second function pin;

[0126] S204, analyze the test mode selection data to obtain the test mode selection type data;

[0127] S205, guide the chip to enter the corresponding test mode according to the test mode selection type data;

[0128] S206, after the chip enters the test mode, change from the on state to the off state; and

[0129] S207, after the test is completed, in response to the obtained reset instruction, change from the off state to the on state;

[0130] Among them, after entering the test mode, the first function pin and the second function pin can be multiplexed as test pins in the test mode;

[0131] The reset instruction is different from the timing sequence that appears in the normal test pin timing. The test mode selection data is generated at the clock edge of the test mode data.

[0132] The test mode data stored in the non-volatile storage unit can be modified by programming. The non-volatile storage unit stores data that allows entry into the test mode or prohibits entry into the test mode.

[0133] Specifically, the difference between the content in steps S201 to S205 and the content in steps S101 to S104 is that a step of reading the content stored in the non-volatile storage unit is added, which is the content in step S201.

[0134] Please refer to Figure 5 and Figure 6 There are two types of test mode data stored in the non-volatile storage unit. The first type is data that allows entry into the test mode, and the second type is data that prohibits entry into the test mode. Only one of these two types of test mode data can be stored in the non-volatile storage unit. If replacement is needed, the original stored test mode data needs to be erased first, and then new test mode data needs to be entered.

[0135] After the monitoring unit in the chip obtains the clock signal, it will first read the test mode data stored in the non-volatile storage unit. If the data stored in the non-volatile storage unit is data that allows entry into the test mode, then the subsequent steps will be continued. If the data stored in the non-volatile storage unit is data that prohibits entry into the test mode, then the subsequent steps will not be executed.

[0136] By adding a non-volatile storage unit, it is possible to completely avoid the chip accidentally entering the test mode during use. For example, after the test is completed, the data stored in the non-volatile storage unit is changed to data that prohibits entry into the test mode by programming. In this case, the chip will never enter the test mode. When testing is required again, the data stored in the non-volatile storage unit is changed to data that allows entry into the test mode by programming.

[0137] The embodiment of the present application also provides a chip test mode switching device, which is applied to the monitoring unit in the chip and multiplexes two functional pins of the chip, including:

[0138] The first processing unit, in response to the clock signal obtained through the first functional pin, obtains the test mode data through the first functional pin and matches the test mode data with the preset first data;

[0139] The first communication unit is used to receive the test mode selection data through the second functional pin after the test mode data matches the preset first data successfully;

[0140] The first parsing unit is configured to parse the test mode selection data to obtain test mode selection type data;

[0141] The second processing unit is configured to guide the chip into the corresponding test mode according to the test mode selection type data;

[0142] The first state conversion unit is configured to, after the chip enters the test mode, convert the monitoring unit from the enabled state to the disabled state; and

[0143] The second state conversion unit is configured to, after the test is completed, in response to the obtained reset instruction, convert the monitoring unit from the disabled state to the enabled state;

[0144] Wherein, after entering the test mode, the first functional pin and the second functional pin can be multiplexed as test pins in the test mode;

[0145] The reset instruction is different from the timing in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data.

[0146] Further, the test mode includes a SCAN test mode, a BIST test mode, and an analog test mode.

[0147] Further, both the test mode data and the test mode selection data are received through the multiplexed functional pins.

[0148] The embodiment of the present application further provides a chip test mode switching device, which is applied to the monitoring unit in the chip and multiplexes two functional pins of the chip, and includes:

[0149] The third processing unit is configured to, in response to the clock signal obtained through the first functional pin, read the test mode data stored in the non-volatile storage unit, and the test mode data includes allowed test mode data and prohibited test mode data;

[0150] The fourth processing unit is configured to, when the test mode data stored in the non-volatile storage unit is allowed test mode data, obtain the test mode data through the first functional pin and match the test mode data with the preset first data;

[0151] The fifth processing unit is configured to, when the test mode data stored in the non-volatile storage unit is allowed test mode data, match the test mode data with the preset first data;

[0152] The second communication unit is configured to, after the test mode data and the preset first data are successfully matched, receive the test mode selection data through the second functional pin;

[0153] A second parsing unit, configured to parse the test mode selection data to obtain test mode selection type data;

[0154] A sixth processing unit, configured to guide the chip into a corresponding test mode according to the test mode selection type data;

[0155] A third state conversion unit, configured to, after the chip enters the test mode, change the monitoring unit from the enabled state to the disabled state; and

[0156] A fourth state conversion unit, configured to, after the test is completed, in response to the obtained reset instruction, change the monitoring unit from the disabled state to the enabled state;

[0157] Wherein, after entering the test mode, the first functional pin and the second functional pin can be multiplexed as test pins in the test mode;

[0158] The reset instruction is different from the timing that appears in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data;

[0159] The test mode data stored in the non-volatile storage unit can be modified by means of programming. The non-volatile storage unit stores data allowing entry into the test mode or data prohibiting entry into the test mode.

[0160] Further, the test mode includes a SCAN test mode, a BIST test mode, and an analog test mode.

[0161] Further, both the test mode data and the test mode selection data are received through the multiplexed functional pins.

[0162] In one example, the units in any of the above devices may be one or more integrated circuits configured to implement the above methods. For example: one or more application specific integrated circuits (ASICs), or, one or more digital signal processors (DSPs), or, one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0163] Again, when the units in the device can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call programs. Again, these units may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0164] In this application, names are given to various objects such as various messages / information / devices / network elements / systems / devices / actions / operations / processes / concepts, etc. that may appear. It can be understood that these specific names do not constitute a limitation on the relevant objects, and the given names can be changed according to factors such as scenarios, contexts, or usage habits. The understanding of the technical meaning of the technical terms in this application should be mainly determined from the functions and technical effects reflected / executed in the technical solutions.

[0165] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0166] In several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0167] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0168] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraint conditions of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0169] It should also be understood that in each embodiment of this application, the first, second, etc. are only used to indicate that multiple objects are different. For example, the first time window and the second time window are only used to indicate different time windows. And it should not have any impact on the time window itself. The above first, second, etc. should not impose any restrictions on the embodiments of this application.

[0170] It should also be understood that in various embodiments of the present application, without special instructions and logical conflicts, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0171] If the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned computer-readable storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0172] The embodiment of the present application also provides a chip test mode switching system, which is applied to a monitoring unit in a chip and multiplexes two functional pins of the chip. The system includes:

[0173] One or more memories for storing instructions; and

[0174] One or more processors for calling and running the instructions from the memory to execute the chip test mode switching method as described above.

[0175] The embodiment of the present application also provides a computer program product. The computer program product includes instructions that, when executed, cause the terminal device and the network device to perform the operations of the terminal device and the network device corresponding to the above method.

[0176] The embodiment of the present application also provides a chip. The chip includes a processor, a monitoring unit, and a data interface. The monitoring unit receives data through the data interface to execute the chip test mode switching method as described above.

[0177] The processor mentioned anywhere above can be a CPU, a microprocessor, an ASIC, or an integrated circuit for executing one or more programs for guiding the above-mentioned method of feedback information transmission.

[0178] In a possible design, the chip system further includes a memory for storing necessary program instructions and data. The processor and the memory can be decoupled and separately disposed on different devices, and connected by wired or wireless means to support the chip system to implement various functions in the above embodiments. Alternatively, the processor and the memory can also be coupled on the same device.

[0179] Optionally, the computer instructions are stored in the memory.

[0180] Optionally, the memory is a storage unit within the chip, such as a register, a cache, etc. The memory can also be a storage unit outside the chip within the terminal, such as a ROM or other types of static storage devices that can store static information and instructions, a RAM, etc.

[0181] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both a volatile memory and a non-volatile memory.

[0182] The non-volatile memory can be a ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory.

[0183] The volatile memory can be a RAM, which is used as an external cache. There are various different types of RAM, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synch link DRAM (SLDRAM), and a direct memory bus random access memory.

[0184] The embodiments of the specific implementation manners are all preferred embodiments of the present application, and do not limit the protection scope of the present application accordingly. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application should be covered within the protection scope of the present application.

Claims

1. A method for switching chip test modes, which is applied to a monitoring unit in a chip and multiplexes two functional pins of the chip, characterized in that, it includes: In response to a clock signal obtained through a first functional pin, acquiring test mode data through the first functional pin and matching the test mode data with preset first data; After the test mode data successfully matches the preset first data, receiving test mode selection data through a second functional pin; Analyzing the test mode selection data to obtain test mode selection type data; Guiding the chip into a corresponding test mode according to the test mode selection type data; After the chip enters the test mode, the monitoring unit changes from the on state to the off state; and After the test is completed, in response to the acquired reset instruction, the monitoring unit changes from the off state to the on state; wherein, after entering the test mode, the first functional pin and the second functional pin can be multiplexed as test pins in the test mode; The reset instruction is different from the timing that appears in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data.

2. A method for switching chip test modes according to claim 1, characterized in that, The test modes include SCAN test mode, BIST test mode and analog test mode.

3. A method for switching chip test modes according to claim 1 or 2, characterized in that, Both the test mode data and the test mode selection data are received through multiplexed functional pins.

4. A method for switching chip test modes, which is applied to a monitoring unit in a chip and multiplexes two functional pins of the chip, characterized in that, it includes: In response to a clock signal obtained through a first functional pin, reading test mode data stored in a non-volatile storage unit, where the test mode data includes allowed test mode data and prohibited test mode data; When the test mode data stored in the non-volatile storage unit is allowed test mode data, acquiring test mode data through the first functional pin and matching the test mode data with preset first data; After the test mode data successfully matches the preset first data, receiving test mode selection data through a second functional pin; Analyzing the test mode selection data to obtain test mode selection type data; Guiding the chip into a corresponding test mode according to the test mode selection type data; After the chip enters the test mode, the monitoring unit changes from the on state to the off state; and After the test is completed, in response to the acquired reset instruction, the monitoring unit changes from the off state to the on state; wherein, after entering the test mode, the first functional pin and the second functional pin can be multiplexed as test pins in the test mode; The reset instruction is different from the timing that appears in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data; The test mode data stored in the non-volatile storage unit can be modified by burning, and the non-volatile storage unit stores allowed test mode data or prohibited test mode data.

5. A method for switching chip test modes according to claim 4, It is characterized in that the test modes include a SCAN test mode, a BIST test mode, and a simulation test mode.

6. A method for switching chip test modes according to claim 4 or 5, It is characterized in that both the test mode data and the test mode selection data are received through multiplexed function pins.

7. A chip test mode switching device, which is applied to a monitoring unit in a chip and multiplexes two function pins of the chip, It is characterized in that it includes: A first processing unit, in response to a clock signal obtained through a first function pin, acquires test mode data through the first function pin and matches the test mode data with preset first data; A first communication unit, after the test mode data and the preset first data match successfully, receives test mode selection data through a second function pin; A first parsing unit, used to parse the test mode selection data to obtain test mode selection type data; A second processing unit, used to guide the chip to enter the corresponding test mode according to the test mode selection type data; A first state conversion unit, after the chip enters the test mode, converts the monitoring unit from an on state to an off state; and A second state conversion unit, after the test is completed, in response to an acquired reset instruction, converts the monitoring unit from an off state to an on state; wherein, after entering the test mode, the first function pin and the second function pin can be multiplexed as test pins in the test mode; The reset instruction is different from the timing in the normal test pin timing, and the test mode selection data is generated at the clock edge of the test mode data.

8. A chip test mode switching device, which is applied to a monitoring unit in a chip and multiplexes two function pins of the chip, It is characterized in that it includes: A third processing unit, used to read the test mode data stored in the non-volatile storage unit in response to a clock signal obtained through the first function pin, and the test mode data includes data allowing entry into the test mode and data prohibiting entry into the test mode; A fourth processing unit, when the test mode data stored in the non-volatile storage unit is data allowing entry into the test mode, acquires the test mode data through the first function pin and matches the test mode data with preset first data; A fifth processing unit, when the test mode data stored in the non-volatile storage unit is data allowing entry into the test mode, matches the test mode data with preset first data; A second communication unit, after the test mode data and the preset first data match successfully, receives test mode selection data through a second function pin; A second parsing unit, used to parse the test mode selection data to obtain test mode selection type data; A sixth processing unit, used to guide the chip to enter the corresponding test mode according to the test mode selection type data; A third state conversion unit, after the chip enters the test mode, converts the monitoring unit from an on state to an off state; and A fourth state conversion unit, after the test is completed, in response to an acquired reset instruction, converts the monitoring unit from an off state to an on state; Among them, after entering the test mode, the first function pin and the second function pin can be multiplexed as test pins in the test mode; The reset instruction is different from the timing sequence that appears in the normal test pin timing sequence, and the test mode selection data is generated at the clock edge of the test mode data; The test mode data stored in the non-volatile storage unit can be modified by programming, and the non-volatile storage unit stores data that allows or prohibits entering the test mode.

9. A chip test mode switching system is applied to a monitoring unit in a chip and multiplexes two function pins of the chip. It is characterized in that The system includes: One or more memories for storing instructions; and One or more processors for calling and running the instructions from the memory and executing the chip test mode switching method according to any one of claims 1 to 3 or 4 to 6.

10. A chip It is characterized in that The chip includes a processor, a monitoring unit and a data interface. The monitoring unit receives data through the data interface to execute the chip test mode switching method according to any one of claims 1 to 3 or 4 to 6.

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