Chassis trigger signal control method and chassis control system

Abstract

The present invention discloses a chassis trigger signal control method and a chassis control system, the chassis trigger signal control method comprising: controlling the differential trigger signal of the sub-chassis to be input to the main chassis; according to the differential trigger signal, controlling the main fan-out module of the main chassis to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and simultaneously controlling the main trigger port of the main chassis to output a differential trigger signal to the sub-trigger port of the sub-chassis. The chassis trigger signal control method provided by the present invention uses the main chassis to aggregate the trigger signals of all sub-chassis, and transmits them separately and synchronously through independently set clock synchronization signal and trigger signal transmission channels, thereby ensuring that at least the sub-chassis can be triggered synchronously, and because no timing slot is used, the expansibility is stronger.

Description

Technical Field

[0001] The present invention relates to the field of automatic control technology, and in particular to a chassis trigger signal control method and a chassis control system. Background Art

[0002] IC (Integrated Circuit) test equipment is mostly configured as ATE (Automatic Test Equipment), which is usually composed of a large number of test machines or chassis, and various test functions are realized through the control of computers or other peripherals. Common chassis used to build ATE include PXIe (PCI extensions for Instrumentation Express, PCI extensions for instrumentation systems; PCI, Peripheral Component Interconnection) chassis, which specifically refers to a chassis that performs extended measurements through PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) communication method. The PXIe chassis includes multiple slots and a backplane, and the electrical connection between the slots is realized through the backplane. Since the transmission of data between multiple PXIe chassis relies on the timing consistency between the chassis, how to keep the timing of multiple PXIe chassis consistent and the corresponding control signal transmission is a key issue in this field.

[0003] In the prior art, the timing slot set on the backplane of the PXIe chassis is used to realize the control by connecting a PXI star trigger bus and a PXI trigger bus to the timing slot, which can realize the timing and data transmission at the same time. However, this implementation method has high requirements on the configuration of the PXIe chassis, resulting in a corresponding increase in cost, and it is impossible to complete the cross-chassis synchronous control of the trigger signal on the clock-free board. Summary of the invention

[0004] One of the purposes of the present invention is to provide a chassis trigger signal control method to solve the technical problems that the trigger signal control method in the prior art cannot achieve synchronous transmission between multiple chassis after receiving the trigger signal, and cannot be universally applicable to all types of chassis.

[0005] One of the objectives of the present invention is to provide a chassis control system.

[0006] To achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a chassis trigger signal control method, which is installed in a chassis control system. The chassis trigger signal control method includes: controlling the differential trigger signal of the sub-chassis to be input to the main chassis; according to the differential trigger signal, controlling the main fan-out module of the main chassis to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and simultaneously controlling the main trigger port of the main chassis to output a differential trigger signal to the sub-trigger port of the sub-chassis.

[0007] As a further improvement of an embodiment of the present invention, the method also includes: controlling the main chassis to extract the header byte of the differential trigger signal, and comparing whether the header byte is consistent with the preset standard byte; if they are consistent, determining that the differential trigger signal is a digital trigger signal, controlling the main chassis to perform parsing on the digital trigger signal, and according to the parsed digital trigger signal, controlling the main fan-out module of the main chassis to output a clock synchronization signal to the sub-fan-out module of the sub-chassis; if they are inconsistent, determining whether the differential trigger signal meets the preset width and is a single pulse signal, and if so, determining that the differential trigger signal is a pulse trigger signal, and controlling the main fan-out module of the main chassis to output a clock synchronization signal to the sub-fan-out module of the sub-chassis according to the pulse trigger signal.

[0008] As a further improvement of an embodiment of the present invention, the method also includes: controlling the main chassis to delete the header byte in the differential trigger signal and modifying the differential trigger signal; controlling the main trigger port of the main chassis to output the modified differential trigger signal to the sub-trigger port of the sub-chassis; wherein the modified differential trigger signal includes a preset port identifier.

[0009] As a further improvement of an embodiment of the present invention, the method also includes: when the sub-fan-out module receives a clock synchronization signal from the main fan-out module, controlling the sub-trigger port to receive the differential trigger signal from the main trigger port according to the clock synchronization signal.

[0010] As a further improvement of an embodiment of the present invention, the method also includes: controlling the sub-chassis to determine whether the differential trigger signal contains a preset port identifier; if contained, controlling the triggering of at least one corresponding slot in the sub-chassis according to the differential trigger signal and the clock synchronization signal.

[0011] As a further improvement of one embodiment of the present invention, the method also includes: according to the differential trigger signal, controlling the main fan-out module of the main chassis to output an intermediate synchronization signal to the slave fan-out module of the main chassis; according to the intermediate synchronization signal and the differential trigger signal, controlling the triggering of at least one corresponding slot of the main chassis.

[0012] As a further improvement of an embodiment of the present invention, the method also includes: controlling the main chassis to delay the clock synchronization signal according to a preset delay time to generate the intermediate synchronization signal; wherein the delay time is configured as the trigger signal transmission time from the main chassis to the sub-chassis.

[0013] To achieve one of the above-mentioned purposes of the invention, one embodiment of the present invention provides a chassis control system, comprising: a main chassis and at least one sub-chassis, the main chassis comprising a main fan-out module and a main trigger port, each of the sub-chassis comprising a sub-fan-out module and a sub-trigger port; the chassis control system is configured to execute the chassis trigger signal control method described in any of the above-mentioned technical solutions.

[0014] As a further improvement of an embodiment of the present invention, the main chassis also includes a slave fan-out module, and the main fan-out module and the slave fan-out module, as well as the main fan-out module and the sub-fan-out module are connected through equal-length coaxial cables; the main trigger port includes a main upstream input terminal and a main downstream output terminal, and the sub-trigger port includes a sub-upstream input terminal and a sub-downstream output terminal, the main upstream input terminal is connected to the sub-downstream output terminal, and the sub-downstream output terminal is connected to the main upstream input terminal.

[0015] As a further improvement of an embodiment of the present invention, the sub-fan-out module includes a high-speed sub-fan-out module and a low-speed sub-fan-out module, the slave fan-out module includes a high-speed slave fan-out module and a low-speed slave fan-out module, the high-speed sub-fan-out module and the high-speed slave fan-out module are respectively connected to the main fan-out module, and are both configured to output a 100MHz clock signal, the low-speed sub-fan-out module and the low-speed slave fan-out module are respectively connected to the main fan-out module, and are both configured to output a 10MHz clock signal; the chassis control system includes a constant temperature crystal oscillator, the constant temperature crystal oscillator is connected to the main fan-out module, and is configured to output a 10MHz clock signal.

[0016] Compared with the prior art, the chassis trigger signal control method provided by the present invention, after the sub-chassis receives the trigger signal, controls the main fan-out module in the main chassis to output a clock synchronization signal to reversely control the sub-chassis by capturing the differential trigger signal corresponding to the trigger signal, thereby maintaining the timing synchronization of all sub-chassis connected to the main chassis, and simultaneously outputs the differential trigger signal to the sub-chassis, forming a clock synchronization signal path and a differential trigger signal path that are separately set and act synchronously, without relying on the timing slot and peripheral structure, the overall synchronous triggering of the system can be controlled according to the trigger signal at any sub-chassis. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a structural principle diagram of a chassis control system in one embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the steps of a chassis trigger signal control method in one embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of the steps of a first embodiment of a chassis trigger signal control method in one embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of the steps of a second embodiment of a chassis trigger signal control method in one embodiment of the present invention;

[0021] Figure 5 It is a schematic diagram of the steps of the third embodiment of the chassis trigger signal control method in one embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0023] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0024] The PXIe chassis can be connected to expansion modules, especially boards, through the slots on the backplane, so as to integrate multiple functions in a single PXIe chassis. In a chassis control system composed of multiple PXIe chassis, multiple PXIe chassis can be connected to each other in a cascade manner, so as to achieve communication between PXIe chassis and further expansion of functions. In order to ensure the synchronization of signal transmission, the prior art usually uses the timing slots of the PXIe chassis backplane to connect the timing slots of different PXIe chassis to each other, so as to achieve synchronous triggering. However, in this process, the number of timing slots is limited, and it cannot be well applied to the working conditions where multiple signals need to be transmitted synchronously. On the other hand, in the working conditions where the control system includes a main chassis and multiple sub-chassis connected to the main chassis respectively, the number of slots of the main chassis is difficult to meet the timing synchronization of itself and multiple sub-chassis.

[0025] In order to solve the above technical problems, the present invention provides Figure 1The chassis control system shown, it is worth noting that the chassis, main chassis and sub-chassis involved in the present invention below can be the PXIe chassis mentioned above, or other chassis that establish communication connections with each other through slots, or other systems with the above-mentioned technical problems.

[0026] The chassis control system provided in one embodiment of the present invention includes a main chassis 100 and at least one sub-chassis, which may be, for example, Figure 1 The first sub-chassis 200 and / or the second sub-chassis 300 shown, the main chassis 100 includes a main fan-out module 11 and a main trigger port 12, each sub-chassis includes a sub-fan-out module and a sub-trigger port, specifically, the first sub-chassis 200 includes a first sub-fan-out module 21 and a first sub-trigger port 22, and the second sub-chassis 300 includes a second sub-fan-out module 31 and a second sub-trigger port 32. The chassis control system is configured to execute a chassis trigger signal control method to control the first sub-chassis 200 and / or the second sub-chassis 300 to be triggered synchronously, and the trigger signal can also be defined as a Trigger signal in one embodiment, and of course in other embodiments it can also be other signals carrying pulse information or data information.

[0027] It can be understood that the main chassis 100 can be configured to selectively connect to one of the first sub-chassis 200 and the second sub-chassis 300, or can be connected to the first sub-chassis 200 and the second sub-chassis 300 respectively. When configured as the latter embodiment, the main trigger port 12 can further include a first main trigger port 121 and a second main trigger port 122, and the first main trigger port 121 is connected to the first sub-trigger port 22, and the second main trigger port 122 is connected to the second sub-trigger port 32 to output a trigger signal. Of course, in the embodiment of multiple chassis cascade, the back end of the main chassis 100 can also be connected to multiple sub-chassis, so as to improve the performance of the chassis control system, and the connection method of the multiple sub-chassis can refer to one of the first sub-chassis 200 and the second sub-chassis 300.

[0028] Furthermore, the main fan-out module 11 of the main chassis 100 is connected to the sub-fan-out module of the sub-chassis through an equal-length coaxial line, so that in an embodiment where the chassis control system is configured with multiple sub-chassis and / or the sub-chassis is configured with multiple sub-fan-out modules, it can be ensured that the clock delay and loss of the main fan-out module 11 fanning out to each sub-chassis and / or each sub-fan-out module are equal, and the sub-chassis and / or sub-fan-out modules operate in a consistent manner. Figure 1 As shown, the main fan-out module 11 is connected to the first sub-fan-out module 21 and / or the second sub-fan-out module 31 through the same or different lead-out ports.

[0029] The sub-fan-out module is used to receive the clock signal from the main fan-out module 11, and fans out to at least one slot of the sub-chassis accordingly, so as to realize the control of the slot triggering of the sub-chassis. In one embodiment, the sub-fan-out module may include a high-speed sub-fan-out module and a low-speed sub-fan-out module to fan out clock signals of different frequency bands. Specifically, the first sub-fan-out module 21 may include a first high-speed sub-fan-out module 211 and a first low-speed sub-fan-out module 212. The lead-out port may include (multiple) high-speed lead-out ports and (multiple) low-speed lead-out ports. Thus, the main fan-out module 11 is connected to the first high-speed sub-fan-out module 211 through at least one high-speed lead-out port, and is connected to the first low-speed sub-fan-out module 212 through at least one low-speed lead-out port. In order to ensure the overall synchronization of the output clock of the main chassis 100 to the first sub-chassis 200, the above two connection processes both use equal-length coaxial lines.

[0030] Correspondingly, the second sub-fan-out module 31 may include a second high-speed sub-fan-out module 311 and a second low-speed sub-fan-out module 312, the main fan-out module 11 is connected to the second high-speed sub-fan-out module 311 through at least one high-speed lead-out port, and is connected to the second low-speed sub-fan-out module 312 through at least one low-speed lead-out port, and the above two connection processes use equal-length coaxial lines. Preferably, the connection between the two high-speed sub-fan-out modules and the main fan-out module 11 can be based on different high-speed lead-out ports, and the connection between the two low-speed sub-fan-out modules and the main fan-out module 11 can also be based on different low-speed lead-out ports. The above four connection relationships can be configured to use coaxial lines with the same length, so as to ensure that the clock signals output by the main fan-out module 11 to different sub-fan-out modules are always synchronized.

[0031] Preferably, the main chassis 100 also includes a slave fan-out module 13, which is used to receive the clock signal from the main fan-out module 11, and fan out to at least one slot of the main chassis 100 accordingly, so as to control the slot triggering control of the main chassis 100. The slave fan-out module 13 is also connected to the main fan-out module 11 through an equal-length coaxial line, and the length is consistent with the equal-length coaxial line between the main fan-out module 11 and the sub-fan-out module. In this way, the clock signal transmission process of the main chassis 100 itself is consistent with the clock signal transmission process between the main chassis and the sub-chassis, and after receiving the trigger signal at any one of them, the effect of synchronous triggering of all chassis can be achieved.

[0032] Furthermore, the slave fan-out module 13 may specifically include a high-speed slave fan-out module 131 and a low-speed slave fan-out module 132, which are used to fan out clock signals of different frequency bands. Similar to the sub-fan-out module, the main fan-out module 11 is connected to the high-speed slave fan-out module 131 through at least one high-speed lead-out port, and is connected to the low-speed slave fan-out module 132 through at least one low-speed lead-out port. Preferably, both of the above two connection processes use equal-length coaxial cables.

[0033] Based on this, Figure 1 As shown, the above six connection processes between the fan-out modules are all implemented using coaxial cables of equal length, ensuring that the chassis are at least synchronized in terms of clock signal transmission, avoiding overall timing confusion of the chassis control system caused by transmission loss.

[0034] Further, in one embodiment, the first sub-fan-out module 21, the second sub-fan-out module 31 and the sub-fan-out module 13 can be configured to have the same structure and / or selection. Specifically, the high-speed sub-fan-out module (the first high-speed sub-fan-out module 211, the second high-speed sub-fan-out module 311) and the high-speed sub-fan-out module 131 can be configured to output a 100MHz clock signal, and the low-speed sub-fan-out module (the first low-speed sub-fan-out module 212, the second low-speed sub-fan-out module 312) and the low-speed sub-fan-out module 132 can be configured to output a 10MHz clock signal. In this way, the requirements of different slots on the main chassis 100 and the sub-chassis can be met. Preferably, the sub-fan-out module and the sub-fan-out module 13 can be configured as TI fan-out chip LMK04808.

[0035] Correspondingly, the output port portion connected to the main fan-out module 11 may include two four-channel output modules, one of which is used to output a high-speed clock signal, and the other is used to output a low-speed clock signal. In one embodiment, the main fan-out module 11 may be configured as a TI fan-out chip LMK03318.

[0036] The trigger signal is configured to be transmitted in the form of a differential signal, so as to have better anti-interference ability. Based on this, the main trigger port 12 includes a main uplink input terminal (a first main uplink input terminal 1211 of the first main trigger port 121, a second main uplink input terminal 1221 of the second main trigger port 122) and a main downlink output terminal (a first main downlink output terminal 1212 of the first main trigger port 121, a second main downlink output terminal 1222 of the second main trigger port 122), and the sub-trigger port includes a sub-uplink input terminal (a first sub-uplink input terminal 221 of the first sub-trigger port 22, a second sub-uplink input terminal 321 of the second sub-trigger port 32) and a sub-downlink output terminal (a first sub-downlink output terminal 222 of the first sub-trigger port 22, a second sub-downlink output terminal 322 of the second sub-trigger port 32).

[0037] The main uplink input terminal is connected to the sub-downlink output terminal, and the sub-downlink output terminal is connected to the main uplink input terminal, so as to realize the mutual transmission of differential trigger signals. Specifically, the first main uplink input terminal 1211 is connected to the first sub-downlink output terminal 222, the first main downlink output terminal 1212 is connected to the first sub-uplink input terminal 221, the second main downlink output terminal 1222 is connected to the second sub-uplink input terminal 321, and the second main uplink input terminal 1221 is connected to the second sub-downlink output terminal 322.

[0038] In this way, the main chassis 100 can receive the trigger signal from the sub-chassis through the corresponding input terminal, perform unified deployment, and synchronously output the trigger signal to the corresponding input terminal of the sub-chassis through the corresponding output terminal to achieve synchronous triggering. Of course, the trigger signal of the main chassis 100 does not necessarily come from the sub-chassis, and the trigger signal can also be directly added to the main chassis 100 through user operation, external devices, etc., such as from the PXI star trigger bus, from the PXI trigger bus, from the PXIe differential star trigger bus, or from the software digital trigger signal of the host computer. In this way, the main chassis 100 can also be uniformly deployed, unify the clock through equal-length coaxial lines, and input and output through corresponding trigger ports.

[0039] The clock signal at the main chassis 100 may also come from outside the main chassis 100. In one embodiment, the chassis control system may also include a constant temperature crystal oscillator 400, which is connected to the main fan-out module 11 and configured to output a 10 MHz clock signal to the main fan-out module 11.

[0040] Preferably, the sub-chassis (first sub-chassis 200, second sub-chassis 300) can be configured to have the same structure as the main chassis 100, and the type switching can be achieved through the DIP switch set on the chassis. Specifically, the sub-fan-out module of the sub-chassis and the slave fan-out module 13 of the main chassis 100 can be configured to have the same structure, selection and function, and further a switching fan-out module that is the same as the main fan-out module 11 of the main chassis 100 can be configured in the sub-chassis. For example, the first switching fan-out module 23 configured in the first sub-chassis 200 and the second switching fan-out module 33 configured in the second sub-chassis 300. In this way, when the DIP switch is in the first state, the switching fan-out module of the sub-chassis is shielded, and the sub-chassis is controlled by the clock signal of the main chassis 100. When the DIP switch is in the second state, the switching fan-out module of the sub-chassis is started, and the sub-chassis acts as a new main chassis to output clock signals to other chassis in the chassis control system.

[0041] Preferably, a transit processing stage for determining the source of the trigger signal, the type of the trigger signal and forwarding the trigger signal to the fan-out module can be provided between the fan-out module for clock signal control and the trigger port for trigger signal transmission in the main chassis 100. Furthermore, the master fan-out module 11 and the slave fan-out module 13 cooperate with each other and can be configured to perform synchronous / asynchronous processing, reverse processing and dynamic selection of the clock frequency band or clock source on the trigger signal. After selecting and determining the clock frequency band, the fan-out module can be further configured to output a feedback adjustment signal to the transit processing stage, thereby regulating the transit processing stage to keep the same clock as the fan-out module.

[0042] The present invention further provides a chassis trigger signal control method, which is installed in a chassis control system, and the chassis control system can be the chassis control system provided in any of the above-mentioned embodiments. Figure 1 The chassis control method provided in one embodiment of the present invention is as follows: Figure 2 As shown, including:

[0043] Step 51, controlling the differential trigger signal of the sub-chassis to be input to the main chassis 100;

[0044] Step 52, according to the differential trigger signal, control the main fan-out module 11 of the main chassis 100 to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and simultaneously control the main trigger port 12 of the main chassis 100 to output a differential trigger signal to the sub-trigger port of the sub-chassis.

[0045] It is difficult to ensure the consistency of timing control between sub-chassis, so the technical solution provided by the present invention is that after the sub-chassis receives the trigger signal, the sub-chassis is controlled to input the trigger signal into the main chassis in a differential form, and then the main chassis distributes it uniformly. Different from the simple simultaneous transmission of the trigger signal and the synchronization signal through the timing slot connection, it can be applied to the chassis control system of multiple sub-chassis and multi-cascade.

[0046] It is worth noting that in one embodiment, the trigger signal can be specifically configured to carry: target card type information (Card Type), subsystem type information (Subsystem Type), multi-segment index information (MultiSegment Index), trigger data information (Trigger Data), and multi-segment trigger enable information (Multi segment trigger enable). Among them, the target card type information is used to distinguish the final target of the trigger signal, and the target card type information can be determined by the device card information (Instrument Card). The subsystem type information can specifically include a system architecture judgment byte (bit22) and a multi-segment index judgment byte (bit21). Specifically, when bit22 is 1, it is determined that the chassis control system is a multi-chassis cascade architecture, and the transit processing level is controlled to output a multi-segment index query operation, and a trigger signal is output to other sub-chassis; when bit22 is 0, it is determined that the chassis does not belong to the cascade architecture, and the index query operation is not performed.

[0047] In one embodiment, the target board type information is set at bit31-bit24, the subsystem type information is set at bit23-bit20, the multi-segment index information is set at bit19-bit12, and the trigger data information is set at bit11-bit0, so as to encapsulate and form a set of trigger signals. Furthermore, each multi-segment index information corresponds to a set of multi-segment trigger enable information, so as to form a lookup table. In one embodiment, the multi-segment trigger enable information is configured as 36 bits, corresponding to 36 bytes respectively.

[0048] Furthermore, the transit processing stage can also be configured to perform the following steps: receiving the trigger signal, judging the source of the trigger signal and the chassis type of the transit processing stage according to the subsystem type information and the trigger data information carried in the trigger signal; and processing the trigger signal according to the previous judgment step, and forwarding it to the corresponding channel in the fan-out module. The source of the trigger signal can be further defined as: the trigger signal can be:

[0049] (1) a trigger signal from at least one slot of the chassis;

[0050] (2) a first downstream trigger signal from the downstream output terminal of the sub-chassis;

[0051] (3) a second downstream trigger signal from the downstream output terminal of the main chassis;

[0052] (4) Trigger signal from the host computer.

[0053] For the above types (1) and (4), the transit processing stage may be located in the main chassis 100 and / or the sub-chassis; and for the above types (2) and (3), they are located in the main chassis 100 and at least one of the sub-chassis, respectively.

[0054] The present invention further provides a first embodiment based at least in part on the above-mentioned embodiments, such as Figure 3 As shown, including:

[0055] Step 51, controlling the differential trigger signal of the sub-chassis to be input to the main chassis 100;

[0056] Step 521, controlling the main chassis 100 to extract the header byte of the differential trigger signal, and comparing the header byte with a preset standard byte to see whether they are consistent;

[0057] Step 522A, if they are consistent, the differential trigger signal is determined to be a digital trigger signal, the main chassis 100 is controlled to parse the digital trigger signal, and according to the parsed digital trigger signal, the main fan-out module 11 of the main chassis 100 is controlled to output a clock synchronization signal to the sub-fan-out module of the sub-chassis;

[0058] Step 522B, if not consistent, determine whether the differential trigger signal meets the preset width and is a single pulse signal, if so, determine that the differential trigger signal is a pulse trigger signal, and control the main fan-out module 11 of the main chassis 100 to output a clock synchronization signal to the sub-fan-out module of the sub-chassis according to the pulse trigger signal;

[0059] It can be understood that the clock synchronization signal can be interpreted as equivalent to the clock signal mentioned above, or can be interpreted separately. For the latter, the clock signal can be defined as a continuous signal with a fixed frequency band and containing content, and the clock synchronization signal can be a part of the clock signal used to trigger the action of the connected object. The clock synchronization signal can be one or more of a high or low level, a pulse, and data information.

[0060] Based on the foregoing description, the encapsulated trigger signal usually only contains 32 bytes, namely the above-mentioned bit31-bit0, but the number of bytes will be encapsulated to varying degrees depending on the type of trigger signal. In this embodiment, the host computer or other peripherals, the main chassis 100 and the sub-chassis will add a header byte as a detection flag before outputting the digital trigger signal. In one embodiment, the header byte occupies 4 bytes and can be 0101.

[0061] As for the pulse trigger signal, it can also include other header bytes that are distinguished from the above-mentioned 4-byte header bytes. In one embodiment, 1 byte of data bits can also be added as a mark of the pulse trigger signal. Of course, the pulse trigger signal can also include only 32 bytes without adding header bytes for re-packaging.

[0062] In addition, the header byte is not limited to the implementation method of adding one or more bytes to the original 32-byte trigger signal and repackaging it. In other implementation methods, some bits in the trigger signal can also be modified and used as flag bits, which can also achieve the technical effect of identification and distinction.

[0063] The process of the control main box 100 parsing the digital trigger signal can be implemented using the relay processing stage, that is, the relay processing stage, in one embodiment, can be configured to parse and forward the digital trigger signal, and directly forward the pulse trigger signal.

[0064] Based on the above-mentioned header byte extraction and analysis process, before the trigger signal is output, a corresponding header byte adding process can be performed. This process can be executed in the host computer or peripheral device, the main chassis 100 and any device in the sub-chassis that can output the trigger signal, including: selectively adding and / or modifying the header byte and / or the flag bit according to the type of trigger signal; if the trigger signal is a digital trigger signal, adding and / or modifying the first header byte and / or the first flag bit; if the trigger signal is a pulse trigger signal, adding and / or modifying the second header byte and / or the second flag bit.

[0065] At the same time, considering that the external interference signal may also be configured to have the above-mentioned header byte that meets the preset standard byte, it is also possible to further determine whether the differential trigger signal (pulse) with the header byte meets the preset width and is a single pulse signal, so as to exclude interference signals whose width and pulse form do not meet the chassis working requirements. Based on this, step 522B may also include: if inconsistent, determining whether the differential trigger signal meets the preset width and is a single pulse signal, if not, determining that the differential trigger signal is an interference signal, and discarding the differential trigger signal.

[0066] Based on the above, the first embodiment of the implementation mode of the present invention may further include the following steps:

[0067] Step 523, controlling the main chassis 100 to delete the header byte in the differential trigger signal, and modifying the differential trigger signal;

[0068] Step 524 , controlling the main trigger port 12 of the main chassis 100 to output the modified differential trigger signal to the sub-trigger port of the sub-chassis.

[0069] Step 523 may be performed by the transit processing stage, which deletes the added header byte after determining that the trigger signal is a digital trigger signal, generates a standard 32-bit differential trigger signal, and then edits it.

[0070] The modified differential trigger signal includes a preset port identifier. In one implementation, the modification and editing process can be performed on the system architecture judgment byte bit 22, that is, the system architecture judgment byte is reused as the preset port identifier. Of course, it can also be implemented through other implementations such as port value, transmission loop mark, etc.

[0071] Since when the system architecture judgment byte bit22 is 1, it indicates that the system is a multi-cascade chassis architecture, and when bit22 is 0, it indicates that the system is a multi-cascade chassis architecture. Therefore, the chassis control system corresponds to the above process, and for the main chassis 100, it can also be configured to perform the following steps accordingly: control the main chassis 100 to receive the trigger signal, and extract the system architecture judgment byte therein; judge the chassis control system architecture according to the system architecture judgment byte, if it is a multi-cascade architecture (bit22 can be 1), then modify the system architecture judgment byte (bit22 can be modified to 0), and control the main chassis 100 to output the modified trigger signal to the sub-chassis (this process belongs to a preferred implementation of the above steps 522 and 523); if it is not a multi-cascade architecture (bit22 can be 0), then forward it to at least one slot in the main chassis 100.

[0072] The present invention further provides a second embodiment based at least in part on the above-mentioned embodiment, such as Figure 4 As shown, including:

[0073] Step 51, controlling the differential trigger signal of the sub-chassis to be input to the main chassis 100;

[0074] Step 52, according to the differential trigger signal, control the main fan-out module 11 of the main chassis 100 to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and simultaneously control the main trigger port 12 of the main chassis 100 to output a differential trigger signal to the sub-trigger port of the sub-chassis;

[0075] Step 53, when the sub-fan-out module receives the clock synchronization signal from the main fan-out module 11, the sub-trigger port is controlled to receive the differential trigger signal from the main trigger port 12 according to the clock synchronization signal;

[0076] Step 53 is the corresponding step of step 52, and can be applied to step 52 and the detailed steps of step 52 in any embodiment of the present invention. It describes the corresponding action process of the sub-chassis after the main chassis 100 outputs a trigger signal to the sub-chassis. By executing the above steps, the reception of the differential trigger signal and the subsequent forwarding process can be completely dependent on the regulation of the clock synchronization signal, so that at least multiple sub-chassis connected to the main chassis 100 and controlled by it can act and trigger synchronously.

[0077] Based on the above, the second embodiment of the implementation mode of the present invention may further include the following steps:

[0078] Step 541, controlling the sub-chassis to determine whether the differential trigger signal contains a preset port identifier;

[0079] Step 542: If included, control triggering at least one corresponding slot in the sub-chassis according to the differential trigger signal and the clock synchronization signal.

[0080] Corresponding to the technical solution provided in the first embodiment, the chassis control system can be configured to perform the following steps for the sub-chassis: control the sub-chassis to receive the trigger signal and extract the system architecture judgment byte therein; judge the chassis control system architecture according to the system architecture judgment byte, if it is a multi-cascade architecture (bit22 can be 1), then output it to the main chassis 100 for aggregation and synchronous distribution; if it is not a multi-cascade architecture (bit22 can be 0), then forward it to at least one slot in the sub-chassis. Combined with the corresponding operation process of the above-mentioned main chassis 100, it can be understood that in this preferred embodiment, the present invention reuses the system architecture judgment byte as a judgment standard for chassis forwarding output or forwarding locally. When bit22 is 1, it indicates that the chassis needs to forward the trigger signal, and when bit22 is 0, it indicates that the chassis needs to forward the trigger signal to at least one local slot or bus pin, thereby triggering the slot or board.

[0081] Furthermore, when the sub-chassis is configured to include a first sub-chassis 200 and a second sub-chassis 300, the trigger signals output by the main chassis 100 to the two chassis may trigger the slots or bus pins on the sub-chassis that are the same or different. In a specific embodiment, the first sub-chassis 200 may be configured to: receive a trigger signal, determine that the trigger signal has been modified (or is not a multi-cascade architecture, or bit22 is 0), and then forward it to at least one pin of its differential star trigger line; the second sub-chassis 300 may be configured to: receive a trigger signal, determine that the trigger signal has been modified, and then forward it to at least one pin of its differential star trigger line.

[0082] The triggering process of the corresponding slot can be realized by a slot switch register set in the chassis, or by other components independently set or integrated in the existing device. For the former, the above steps can be further preferably: if included, the corresponding slot in the sub-chassis is triggered by controlling the slot switch register according to the differential trigger signal and the clock synchronization signal.

[0083] Meanwhile, the above steps may further include: if not, discarding the differential trigger signal, and controlling the sub-chassis to continue to determine whether the next differential trigger signal contains the preset port identifier.

[0084] The present invention further provides a third embodiment based at least in part on the above-mentioned embodiments, such as Figure 5 As shown, including:

[0085] Step 51, controlling the differential trigger signal of the sub-chassis to be input to the main chassis 100;

[0086] Step 52, according to the differential trigger signal, control the main fan-out module 11 of the main chassis 100 to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and simultaneously control the main trigger port 12 of the main chassis 100 to output a differential trigger signal to the sub-trigger port of the sub-chassis;

[0087] Step 551, according to the differential trigger signal, control the master fan-out module 11 of the main chassis 100 to output the intermediate synchronization signal to the slave fan-out module 13 of the main chassis 100;

[0088] Step 552, controlling and triggering at least one corresponding slot of the main chassis 100 according to the intermediate synchronization signal and the differential trigger signal.

[0089] After receiving the differential trigger signal that needs to be forwarded to the slot of the main chassis 100 itself (the detection process can apply other port detection, loop marking and other implementation methods, and can also apply the above-mentioned multiplexing system architecture judgment byte bit22 implementation method for detection and judgment. The differential trigger signal that meets the local forwarding conditions can be that its system architecture judgment byte bit22 itself is 0 value, or it is modified to a differential trigger signal of 0 value after the transit processing stage), the main fan-out module 11 of the main chassis 100 will use the fan-out module 13 to perform synchronous triggering of the slot.

[0090] The triggering process of the corresponding slot can be realized by a slot switch register set in the chassis, or by other components independently set or integrated in the existing device. For the former, the above steps can be further preferably: if included, the corresponding slot in the sub-chassis is triggered by controlling the slot switch register according to the differential trigger signal and the clock synchronization signal.

[0091] Since the transmission speed from the main fan-out module 11, the sub-fan-out module 13, and the main trigger port 12 is respectively collected at the transit processing stage of the main chassis 100, and then processed and forwarded to the slot of the main chassis 100, it is often faster than the transmission speed from the main fan-out module 11, the sub-fan-out module, the main trigger port 12, and the sub-trigger port respectively collected at the transit processing stage of the sub-chassis, and then processed and forwarded to the slot of the sub-chassis. Therefore, the clock synchronization signal used to regulate the triggering of the sub-chassis and the intermediate synchronization signal used to regulate the triggering of the main chassis 100 should be distinguished. According to the time difference, the length of any transmission line or the internal routing of the FPGA (Field Programmable Gate Array) can be changed to achieve time difference compensation. Of course, the delay can also be set.

[0092] For the latter solution, the third embodiment of the implementation mode of the present invention may further include the following steps between step 52 and step 551:

[0093] Step 550, controlling the main chassis 100 to perform delay processing on the clock synchronization signal according to a preset delay time to generate an intermediate synchronization signal;

[0094] The delay time is configured as the transmission time of the trigger signal from the main chassis 100 to the sub-chassis. This is because in one embodiment, after receiving the trigger signal, the main chassis 100 itself can directly trigger the corresponding slot in the main chassis 100 through the internally set FPGA without going through a complicated form conversion and transmission process.

[0095] However, the trigger signal control system provided in this embodiment is configured such that the main chassis 100 uniformly distributes trigger signals to the sub-chassis. Therefore, the triggering of the sub-chassis must go through the differential form conversion of the trigger signal and the transmission of the differential trigger signal between the main chassis 100 and the sub-chassis. After the above process, the sub-chassis can use its own FPGA to trigger the corresponding slot in the sub-chassis. Therefore, in order to compensate for the trigger delay that may be caused to the sub-chassis by the above path transmission, the above delay time configuration is performed in this embodiment to achieve the technical effect of compensating for the transmission time difference.

[0096] Specifically, different delay times can be set for different trigger signal types. In the implementation where the trigger signal is the digital trigger signal, the delay time can be set to 60 clock cycles, and the frequency corresponding to the clock cycle can be 100 MHz. The corresponding steps may include: controlling the main chassis 100 to extract the header byte of the differential trigger signal, and comparing whether the header byte is consistent with the preset standard byte; if they are consistent, determining that the differential trigger signal is a digital trigger signal, controlling the main chassis 100 to perform analysis on the digital trigger signal, controlling the main fan-out module 11 of the main chassis 100 to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and controlling the main fan-out module 11 of the main chassis 100 to output the first intermediate synchronization signal after the clock synchronization signal is delayed by the first clock cycle to the slave fan-out module 13.

[0097] In the implementation mode where the trigger signal is the pulse trigger signal, the delay time can be set to 7 clock cycles, and the frequency corresponding to the clock cycle can be 100 MHz. The corresponding steps can include: controlling the main chassis 100 to extract the header byte of the differential trigger signal, and comparing whether the header byte is consistent with the preset standard byte; if not, determining that the differential trigger signal is a pulse signal, and controlling the main fan-out module 11 of the main chassis 100 to output a clock synchronization signal to the sub-fan-out module of the sub-chassis according to the pulse trigger signal, and controlling the main fan-out module 11 of the main chassis 100 to output a second intermediate synchronization signal to the slave fan-out module 13 after delaying the clock synchronization signal by the second clock cycle.

[0098] Of course, the above clock cycle and the corresponding first clock cycle, second clock cycle, first intermediate synchronization signal and second intermediate synchronization signal are only described as providing a preferred implementation mode, and do not mean that the present invention is limited to the clock cycle and frequency of the fixed value. The above delay is performed between the master fan-out module 11 and the slave fan-out module 13, and in other implementation modes, it can also be performed between the slave fan-out module 13 and the slot. Under the enlightenment of the present invention, those skilled in the art can derive a variety of implementation modes.

[0099] In summary, the chassis trigger signal control method provided by the present invention, after the sub-chassis receives the trigger signal, captures the differential trigger signal corresponding to the trigger signal, thereby controlling the main fan-out module 11 in the main chassis 100 to output a clock synchronization signal to reversely control the sub-chassis, maintain the timing synchronization of all sub-chassis connected to the main chassis 100, and simultaneously outputs the differential trigger signal to the sub-chassis, forming a clock synchronization signal path and a differential trigger signal path that are separately set and act synchronously, without relying on the timing slot and peripheral structure, the overall synchronous triggering of the system can be controlled according to the trigger signal at any sub-chassis.

[0100] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0101] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chassis trigger signal control method, mounted in a chassis control system, characterized in that: The chassis trigger signal control method comprises: Control the differential trigger signal of the sub-chassis to be input to the main chassis; According to the differential trigger signal, the main fan-out module of the main chassis is controlled to output a clock synchronization signal to the sub-fan-out module of the sub-chassis, and at the same time The main trigger port of the main chassis is controlled to output a differential trigger signal to the sub-trigger port of the sub-chassis.

2. The chassis trigger signal control method according to claim 1, characterized in that: The method further comprises: Controlling the main chassis to extract the header byte of the differential trigger signal, and comparing whether the header byte is consistent with a preset standard byte; If they are consistent, it is determined that the differential trigger signal is a digital trigger signal, the main chassis is controlled to parse the digital trigger signal, and according to the parsed digital trigger signal, the main fan-out module of the main chassis is controlled to output a clock synchronization signal to the sub-fan-out module of the sub-chassis; If they are inconsistent, determine whether the differential trigger signal meets the preset width and is a single pulse signal. If so, determine that the differential trigger signal is a pulse trigger signal, and control the main fan-out module of the main chassis to output a clock synchronization signal to the sub-fan-out module of the sub-chassis according to the pulse trigger signal.

3. The chassis trigger signal control method according to claim 2, characterized in that: The method further comprises: Controlling the host chassis to delete the header byte in the differential trigger signal and modify the differential trigger signal; The main trigger port of the main chassis is controlled to output a modified differential trigger signal to the sub-trigger port of the sub-chassis; wherein the modified differential trigger signal includes a preset port identifier.

4. The chassis trigger signal control method according to claim 1, characterized in that: The method further comprises: When the sub-fan-out module receives the clock synchronization signal from the main fan-out module, the sub-trigger port is controlled to receive the differential trigger signal from the main trigger port according to the clock synchronization signal.

5. The chassis trigger signal control method according to claim 4, characterized in that: The method further comprises: Controlling the sub-chassis to determine whether the differential trigger signal includes a preset port identifier; If included, at least one corresponding slot in the sub-chassis is controlled to be triggered according to the differential trigger signal and the clock synchronization signal.

6. The chassis trigger signal control method according to claim 1, characterized in that: The method further comprises: According to the differential trigger signal, control the master fan-out module of the host chassis to output an intermediate synchronization signal to the slave fan-out module of the host chassis; At least one corresponding slot of the main chassis is controlled and triggered according to the intermediate synchronization signal and the differential trigger signal.

7. The chassis trigger signal control method according to claim 6, characterized in that: The method further comprises: The main chassis is controlled to perform delay processing on the clock synchronization signal according to a preset delay time to generate the intermediate synchronization signal; wherein the delay time is configured as the trigger signal transmission time from the main chassis to the sub-chassis.

8. A chassis control system, characterized in that: include: A main chassis and at least one sub-chassis, wherein the main chassis includes a main fan-out module and a main trigger port, and each of the sub-chassis includes a sub-fan-out module and a sub-trigger port; The chassis control system is configured to execute the chassis trigger signal control method according to any one of claims 1 to 7.

9. The chassis control system according to claim 8, characterized in that: The main chassis also includes a slave fan-out module, and the main fan-out module and the slave fan-out module, and the main fan-out module and the sub-fan-out module are connected through equal-length coaxial lines; The main trigger port includes a main uplink input terminal and a main downlink output terminal, and the sub-trigger port includes a sub-uplink input terminal and a sub-downlink output terminal. The main uplink input terminal is connected to the sub-downlink output terminal, and the sub-downlink output terminal is connected to the main uplink input terminal.

10. The chassis control system according to claim 9, characterized in that: The sub-fan-out module includes a high-speed sub-fan-out module and a low-speed sub-fan-out module, the slave fan-out module includes a high-speed slave fan-out module and a low-speed slave fan-out module, the high-speed sub-fan-out module and the high-speed slave fan-out module are respectively connected to the main fan-out module, and are both configured to output a 100MHz clock signal, the low-speed sub-fan-out module and the low-speed slave fan-out module are respectively connected to the main fan-out module, and are both configured to output a 10MHz clock signal; The chassis control system includes a constant temperature crystal oscillator, which is connected to the main fan-out module and is configured to output a 10 MHz clock signal.

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