A method and device for reset processing of an SOC chip, an SOC chip, and a medium

Abstract

The present application discloses a method, device, SOC chip and medium for reset processing of an SOC chip, including: starting from the starting address of the on-chip RAM, writing a reset processing program into the on-chip RAM; mapping the starting address of the on-chip RAM to the CPU reset vector address; when the SOC chip undergoes a non-cold reset, reading and executing the reset processing program from the starting address of the on-chip RAM to perform corresponding reset processing. In this way, when the SOC chip undergoes a non-cold reset, the CPU will start reading and executing the reset processing program from the starting address of the on-chip RAM to perform reset processing. After the chip is taped out and returned, according to the chip debugging needs, different reset processing programs can be repeatedly written into the RAM for debugging, improving the flexibility of chip reset processing. The non-cold reset does not require the BootROM to execute again, saving the time for the chip to process the non-cold reset.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a SOC chip reset processing method, device, SOC chip and medium. Background Art

[0002] With the rapid development of chip technology, the functions of chips are becoming more and more powerful, and thus their complexity is also increasing, and they need to support more and more reset types. The chip reset types mainly include: cold reset, debug reset, software reset, watchdog reset, PCIe (peripheral component interconnect express reset, a high-speed serial computer expansion bus standard) reset, etc.

[0003] At present, in most chip designs, a piece of on-chip ROM (Read Only Memory) is placed in the address space of the CPU reset vector (i.e., the CPU (i.e., Central Processing Unit) reset vector), and its content is the BootROM program (i.e., the first code executed by the processor when it is powered on or reset). After the chip is reset, the CPU will read and execute instructions from the reset vector address, and the BootROM will start to execute. The reset processing is completed in the BootROM program. The BootROM program will first determine the type of reset that has occurred, and enter the corresponding reset processing branch, and then perform corresponding processing for this reset type. Since the BootROM program is solidified in the on-chip ROM, it cannot be modified after the chip is taped out, which means that the reset processing code cannot be modified after the chip is taped out, and it is not flexible. In addition, after the chip is reset, the BootROM program needs to be re-executed, and the execution of the BootROM program takes time, especially the execution of the encryption and decryption algorithm in the BootROM program takes a lot of time, which results in the need to spend precious time to process the chip reset. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a SOC chip reset processing method, device, SOC chip and medium, which can improve the flexibility of chip reset processing and save the time of chip processing non-cold reset. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a SOC chip reset processing method, comprising:

[0006] Starting from the starting address of the on-chip RAM, write the reset handler to the on-chip RAM;

[0007] Map the starting address of the on-chip RAM to the CPU reset vector address;

[0008] When the SOC chip undergoes a non-cold reset, read and execute the reset handler starting from the starting address of the on-chip RAM to perform corresponding reset processing.

[0009] Optionally, executing the reset handler to perform corresponding reset processing includes:

[0010] Execute the reset handler, and during the execution, read the register value of the reset status register, determine the reset type of the current reset based on the register value, and execute the reset processing subroutine corresponding to the reset type according to the reset type to perform corresponding reset processing.

[0011] Optionally, the mapping of the starting address of the on-chip RAM to the CPU reset vector address includes:

[0012] Operate a preset on-chip RAM mapping register to map the starting address of the on-chip RAM to the CPU reset vector address.

[0013] Optionally, the preset on-chip RAM mapping register is reset to the default value when the SOC chip undergoes a cold reset;

[0014] Wherein, if the starting address of the on-chip ROM of the SOC chip is the same as the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip RAM is not mapped; if the starting address of the on-chip ROM is different from the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip ROM is mapped to the CPU reset vector address.

[0015] Optionally, it further includes:

[0016] When the SOC chip undergoes a cold reset, read and execute the BootROM program starting from the starting address of the on-chip ROM;

[0017] After the execution of the BootROM program is completed, execute the Bootloader program, and during the execution of the Bootloader program, starting from the starting address of the on-chip RAM, write the reset handler to the on-chip RAM, and map the starting address of the on-chip RAM to the CPU reset vector address.

[0018] Optionally, after mapping the starting address of the on-chip RAM to the CPU reset vector address, the method further includes:

[0019] Operating a preset on-chip ROM control register to turn off the power supply and clock of the on-chip ROM.

[0020] Optionally, the preset on-chip ROM control register is reset to a default value when a cold reset occurs in the SOC chip, and the default value indicates enabling the power supply and clock of the on-chip ROM.

[0021] In a second aspect, the present application discloses a reset processing device for an SOC chip, including:

[0022] A reset processing program writing module, configured to write a reset processing program into the on-chip RAM starting from the starting address of the on-chip RAM;

[0023] A RAM address mapping module, configured to map the starting address of the on-chip RAM to the CPU reset vector address;

[0024] An SOC chip reset processing module, configured to, when a non-cold reset occurs in the SOC chip, read and execute the reset processing program starting from the starting address of the on-chip RAM to perform corresponding reset processing.

[0025] In a third aspect, the present application discloses an SOC chip, including:

[0026] A memory, configured to store a computer program;

[0027] A processor, configured to execute the computer program to implement the foregoing SOC chip reset processing method.

[0028] In a fourth aspect, the present application discloses a computer-readable storage medium, configured to store a computer program, and when the computer program is executed by a processor, the foregoing SOC chip reset processing method is implemented.

[0029] It can be seen that in this application, starting from the starting address of the on-chip RAM, the reset handler is written into the on-chip RAM, and the starting address of the on-chip RAM is mapped to the CPU reset vector address. When the SOC chip undergoes a non-cold reset, the reset handler is read and executed starting from the starting address of the on-chip RAM to perform the corresponding reset processing. That is to say, in the embodiments of this application, the on-chip RAM address space is mapped to the CPU reset vector address space, and starting from the starting position of the on-chip RAM, the reset handler is written. When the SOC chip undergoes a non-cold reset, the CPU will read and execute the reset handler starting from the starting address of the on-chip RAM to perform the reset processing. Since the content in the RAM can be modified, after the chip is fabricated and returned, according to the debugging needs of the chip, different reset handlers can be repeatedly written in the RAM for debugging to find the final deliverable program. In this way, the flexibility of the chip reset processing is improved. Moreover, for non-cold resets, there is no need for the BootROM to execute again, but directly execute through the reset handler, saving the time for the chip to process non-cold resets. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0031] Figure 1 Flowchart of a method for reset processing of an SOC chip disclosed in this application;

[0032] Figure 2 Schematic diagram of a specific address mapping disclosed in this application;

[0033] Figure 3 Another specific schematic diagram of address mapping disclosed in this application;

[0034] Figure 4 Schematic diagram of a specific reset processing flow of an SOC chip disclosed in this application;

[0035] Figure 5 Schematic diagram of the structure of a device for reset processing of an SOC chip disclosed in this application;

[0036] Figure 6 Schematic diagram of an SOC chip structure disclosed in this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] At present, in most chip designs, a piece of on-chip ROM (i.e., Read Only Memory) is placed in the CPU reset vector address space, and its content is the BootROM program. After the chip is reset, the CPU will read and execute instructions from the reset vector address, and the BootROM will start to execute. The reset processing is completed in the BootROM program. The BootROM program will first determine the type of reset that is currently occurring, and enter the corresponding reset processing branch, and then perform corresponding processing for this reset type. Since the BootROM program is solidified in the on-chip ROM, it cannot be modified after the chip is taped out, which means that the reset processing code cannot be modified after the chip is taped out, and it does not have flexibility. In addition, after the chip reset occurs, the BootROM program needs to be re-executed, and the execution of the BootROM program takes time, especially the execution of the encryption and decryption algorithm in the BootROM program takes a lot of time, which results in the need to spend precious time to process the reset of the chip. To this end, the present application provides a SOC (i.e., System On Chip, system on chip) chip reset solution, which can improve the flexibility of chip reset processing and save the time of chip processing non-cold reset.

[0039] See also Figure 1 As shown, the embodiment of the present application discloses a SOC chip reset processing method, including:

[0040] Step S11: starting from the start address of the on-chip RAM (ie, Random Access Memory), write the reset processing program into the on-chip RAM.

[0041] That is, in the embodiment of the present application, the reset processing program is written into the on-chip RAM, and the writing starts from the starting address of the on-chip RAM.

[0042] Step S12: Map the starting address of the on-chip RAM to the CPU reset vector address.

[0043] It should be noted that the CPU reset vector address is the address where the first instruction is read after the CPU is reset. The starting address of the on-chip RAM is mapped to the CPU reset vector address. After the CPU is reset, the address where the first instruction is read is the starting address of the on-chip RAM.

[0044] In a specific implementation, operate a preset on-chip RAM mapping register to map the starting address of the on-chip RAM to the CPU reset vector address.

[0045] Among them, the preset on-chip RAM mapping register is reset to the default value when the SOC chip undergoes a cold reset; and, if the starting address of the on-chip ROM of the SOC chip is the same as the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip RAM is not mapped; if the starting address of the on-chip ROM is different from the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip ROM is mapped to the CPU reset vector address.

[0046] It should be noted that when designing the SOC chip architecture, determine the address allocated to the CPU reset vector on the address space bus according to the type of CPU selected. Taking the CPU of ARM Company as an example, generally its CPU reset vector address is set to 0x00000000, but other addresses can also be used according to the actual situation. And allocate the address space on the address bus for the on-chip ROM. The starting address of this address space can be the same as the CPU reset vector address or different from the CPU reset vector address. The specific choice depends on the chip design requirements. According to the chip's requirements for the on-chip RAM, configure one or more on-chip RAMs for the chip and allocate address space for the on-chip RAM. If there are multiple on-chip RAMs, select one of them as the main RAM for use when using the address mapping function. When allocating address space for the on-chip ROM and the on-chip RAM, it is also necessary to combine the type of CPU selected, because current CPUs generally adopt a relaxed memory model, and some CPUs defaultly divide their bus address space into regions and configure corresponding Memory access types for these regions.

[0047] Further, the present application designs an on-chip RAM mapping register for mapping the on-chip RAM address space to the CPU reset vector address. In chip design, when the starting address of the on-chip ROM is the same as the CPU reset vector address, the default value of this mapping register indicates that the on-chip RAM mapping function is not enabled. After operating this register to enable the RAM mapping function, the starting address of the on-chip RAM will be mapped to the CPU reset vector address. When accessing the CPU reset vector address and the subsequent on-chip RAM size space addresses, the accessed content is the content of the on-chip RAM, rather than the content of the on-chip ROM. In chip design, when the starting address of the on-chip ROM is different from the CPU reset vector address, the default value of the on-chip RAM mapping register indicates that the starting address of the on-chip ROM is mapped to the CPU reset vector address. After operating this register to enable the RAM mapping function, the starting address of the on-chip RAM will be mapped to the CPU reset vector address, and the function of mapping the starting address of the previous on-chip ROM to the CPU reset vector address will be cancelled.

[0048] For example, refer to Figure 2 as shown Figure 2 which is a specific address mapping schematic diagram disclosed in an embodiment of the present application. Figure 2 In it, the starting address of the ROM is the same as the CPU reset vector address. Refer to Figure 3 as shown Figure 3 which is another specific address mapping schematic diagram disclosed in an embodiment of the present application. Figure 3 In it, the starting address of the ROM is different from the CPU reset vector address.

[0049] In addition, after mapping the starting address of the on-chip RAM to the CPU reset vector address, the present application operates a preset on-chip ROM control register to turn off the power supply and clock of the on-chip ROM.

[0050] Among them, the preset on-chip ROM control register is reset to the default value when a cold reset occurs in the SOC chip, and this default value indicates enabling the power supply and clock of the on-chip ROM.

[0051] That is, the present application designs an on-chip ROM control register for controlling the power (i.e., power supply) and clock of the on-chip ROM, and its default value indicates enabling the power and clock. This register has two functions. First, when the power and clock are not enabled, the on-chip ROM cannot be accessed, protecting its content from being read because the on-chip ROM stores the chip's BootROM program, which is the root of trust of the entire chip and the cornerstone of chip security. Second, when the power and clock are not enabled, the on-chip ROM does not consume power, reducing the power consumption of the entire chip, which is particularly important in low-power chip design.

[0052] It can be understood that when the present application designs the chip reset function, for different reset type designs, the effects on the on-chip RAM mapping function register and the on-chip ROM control register are different. After a cold reset occurs, the on-chip RAM mapping register and the on-chip ROM control register will be reset to their default values, and the functions they control will also be reset to the default state. After a non-cold reset occurs, the values set in the on-chip RAM mapping register and the on-chip ROM control register will be saved and not reset to the default values, and the functions they control will also maintain their current state and not be reset to the default state.

[0053] Step S13: When a non-cold reset occurs in the SOC chip, read and execute the reset processing program starting from the starting address of the on-chip RAM to perform corresponding reset processing.

[0054] In a specific implementation, execute the reset processing program, and during the execution, read the register value of the reset status register, determine the reset type of the current reset based on the register value, and execute the reset processing subroutine corresponding to the reset type according to the reset type to perform corresponding reset processing.

[0055] Moreover, in the embodiment of the present application, when a cold reset occurs in the SOC chip, read and execute the BootROM program starting from the starting address of the on-chip ROM; after completing the execution of the BootROM program, execute the Bootloader program, and during the execution of the Bootloader program, starting from the starting address of the on-chip RAM, write the reset processing program into the on-chip RAM, and map the starting address of the on-chip RAM to the CPU reset vector address.

[0056] It can be understood that, according to all reset types supported in chip design that are not cold reset, the present application writes a reset handling program. In the reset handling program, the type of reset currently occurring is judged by reading the chip reset status register, and then it jumps to the branch handling code of this reset type for processing. The reset handling program of the embodiment of the present application starts to be placed at the starting address of the on-chip RAM, ensuring that the entry address of the reset handling program is consistent with the CPU reset vector address. Moreover, in the Bootloader program, during its chip initialization phase, the embodiment of the present application copies the reset handling program code to the starting address and subsequent address spaces of the on-chip RAM. After the copying is completed, the on-chip RAM address space is mapped to the CPU reset vector address by operating the on-chip RAM mapping function register. Then, by operating the on-chip ROM control register, the power and clock of the on-chip ROM are turned off.

[0057] For example, referring to Figure 4 As shown, the embodiment of the present application discloses a schematic diagram of the processing flow after the chip Boot, that is, after the reset occurs. In the SOC chip design, a mechanism for mapping the on-chip RAM address space to the CPU's reset vector address space is designed, and this mechanism is controlled by registers. After this mapping mechanism takes effect, it can only be reset by cold reset and cannot be reset by other types of reset. In addition, a register is set for the on-chip ROM to control its power and clock. The default value of this register enables the power and clock of the ROM. Similarly, when this register turns off the power and clock of the ROM, it can only be reset by cold reset and cannot be reset by other types of reset. When the chip undergoes a cold reset, the CPU starts to read and execute instructions from the reset vector, and the BootROM program starts to execute. After the execution is completed, it jumps to the next-level Bootloader program for execution. In the Bootloader program, the corresponding reset handling program is written at the starting address of the RAM, and then the RAM address space mapping mechanism is enabled by operating the mapping register. At the same time, the power and clock of the ROM are turned off through the ROM register. When the chip generates a reset other than cold reset, the CPU will start to read and execute instructions from the starting address of the RAM, that is, execute the reset handling program written before the starting address of the RAM. When the chip generates a cold reset, the CPU will start to read and execute instructions from the starting address of the ROM, that is, start to execute the BootROM program.

[0058] It can be seen that in the embodiment of the present application, starting from the starting address of the on-chip RAM, the reset handler is written into the on-chip RAM, and the starting address of the on-chip RAM is mapped to the CPU reset vector address. When the SOC chip undergoes a non-cold reset, the reset handler is read and executed starting from the starting address of the on-chip RAM to perform corresponding reset processing. That is to say, in the embodiment of the present application, the on-chip RAM address space is mapped to the CPU reset vector address space, and starting from the starting position of the on-chip RAM, the reset handler is written. When the SOC chip undergoes a non-cold reset, the CPU will read and execute the reset handler starting from the starting address of the on-chip RAM to perform reset processing. Since the content in the RAM can be modified, after the chip is taped out and returned, according to the chip debugging needs, different reset handlers can be repeatedly written in the RAM for debugging to find the final deliverable program. In this way, the flexibility of chip reset processing is improved, and for non-cold reset, it is not necessary for the BootROM to execute again, but directly execute through the reset handler, saving the time for the chip to process non-cold reset.

[0059] Moreover, after the on-chip RAM is mapped, the power and clock of the on-chip ROM can be turned off, saving the power consumption of the chip and ensuring the security of the content in the ROM.

[0060] See Figure 5 As shown, the embodiment of the present application discloses a reset processing device for an SOC chip, including:

[0061] A reset handler writing module 11, configured to write the reset handler into the on-chip RAM starting from the starting address of the on-chip RAM;

[0062] A RAM address mapping module 12, configured to map the starting address of the on-chip RAM to the CPU reset vector address;

[0063] An SOC chip reset processing module 13, configured to when the SOC chip undergoes a non-cold reset, read and execute the reset handler starting from the starting address of the on-chip RAM to perform corresponding reset processing.

[0064] It can be seen that in the embodiment of the present application, starting from the starting address of the on-chip RAM, the reset handler is written into the on-chip RAM, and the starting address of the on-chip RAM is mapped to the CPU reset vector address. When the SOC chip undergoes a non-cold reset, the reset handler is read and executed starting from the starting address of the on-chip RAM to perform corresponding reset processing. That is to say, in the embodiment of the present application, the on-chip RAM address space is mapped to the CPU reset vector address space, and starting from the starting position of the on-chip RAM, the reset handler is written. When the SOC chip undergoes a non-cold reset, the CPU will read and execute the reset handler starting from the starting address of the on-chip RAM to perform reset processing. Since the content in the RAM can be modified, after the chip is taped out and returned, according to the chip debugging needs, different reset handlers can be repeatedly written in the RAM for debugging to find the final deliverable program. In this way, the flexibility of chip reset processing is improved, and for non-cold resets, there is no need for the BootROM to execute again, but directly through the reset handler, saving the time for the chip to process non-cold resets.

[0065] The SOC chip reset processing module 13 is specifically configured to execute the reset handler, and read the register value of the reset status register during the execution process, determine the reset type of the current reset based on the register value, and execute the reset processing subroutine corresponding to the reset type according to the reset type to perform corresponding reset processing.

[0066] The RAM address mapping module 12 is specifically configured to operate a preset on-chip RAM mapping register to map the starting address of the on-chip RAM to the CPU reset vector address.

[0067] Among them, the preset on-chip RAM mapping register is reset to the default value when the SOC chip undergoes a cold reset; if the starting address of the on-chip ROM of the SOC chip is the same as the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip RAM is not mapped; if the starting address of the on-chip ROM is different from the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip ROM is mapped to the CPU reset vector address.

[0068] Furthermore, the device is further configured to: when the SOC chip undergoes a cold reset, read and execute the BootROM program starting from the starting address of the on-chip ROM; after executing the BootROM program, execute the Bootloader program, and during the execution of the Bootloader program, starting from the starting address of the on-chip RAM, write the reset handler into the on-chip RAM, and map the starting address of the on-chip RAM to the CPU reset vector address.

[0069] Further, the device further includes a power supply and clock control module for the ROM, which is used to operate a preset on-chip ROM control register to turn off the power supply and clock of the on-chip ROM.

[0070] Wherein, the preset on-chip ROM control register is reset to a default value when a cold reset occurs in the SOC chip, and this default value indicates enabling the power supply and clock of the on-chip ROM.

[0071] See Figure 6 As shown, an embodiment of the present application discloses an SOC chip, including a processor 21 and a memory 22; wherein, the memory 22 is used to store a computer program; the processor 21 is used to execute the computer program, which is the SOC chip reset processing method disclosed in the foregoing embodiment.

[0072] For the specific process of the above SOC chip reset processing method, reference can be made to the corresponding content disclosed in the foregoing embodiment, and details will not be repeated here.

[0073] Further, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the SOC chip reset processing method disclosed in the foregoing embodiment.

[0074] For the specific process of the above SOC chip reset processing method, reference can be made to the corresponding content disclosed in the foregoing embodiment, and details will not be repeated here.

[0075] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and reference can be made to the method part for the relevant parts.

[0076] The above has introduced in detail a method, device, SOC chip and medium for reset processing of an SOC chip provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, based on the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A method for resetting an SOC chip, characterized in that, Including: Starting from the starting address of the on-chip RAM, write the reset handler into the on-chip RAM; Map the starting address of the on-chip RAM to the CPU reset vector address; When the SOC chip undergoes a non-cold reset, read and execute the reset handler starting from the starting address of the on-chip RAM to perform corresponding reset processing; Among them, the mapping of the starting address of the on-chip RAM to the CPU reset vector address includes: Operate a preset on-chip RAM mapping register to map the starting address of the on-chip RAM to the CPU reset vector address; Among them, the preset on-chip RAM mapping register is reset to the default value when the SOC chip undergoes a cold reset; Among them, if the starting address of the on-chip ROM of the SOC chip is the same as the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip RAM is not mapped; if the starting address of the on-chip ROM is different from the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip ROM is mapped to the CPU reset vector address; Among them, the SOC chip reset processing method further includes: When the SOC chip undergoes a cold reset, read and execute the BootROM program starting from the starting address of the on-chip ROM; After the execution of the BootROM program is completed, execute the Bootloader program, and during the execution of the Bootloader program, starting from the starting address of the on-chip RAM, write the reset handler into the on-chip RAM, and map the starting address of the on-chip RAM to the CPU reset vector address.

2. The SOC chip reset processing method according to claim 1, characterized in that, Executing the reset handler to perform corresponding reset processing includes: Execute the reset handler, and during the execution, read the register value of the reset status register, judge the reset type of the current reset based on the register value, and execute the reset processing subroutine corresponding to the reset type according to the reset type to perform corresponding reset processing.

3. The SOC chip reset processing method according to claim 1, characterized in that, After the mapping of the starting address of the on-chip RAM to the CPU reset vector address, it further includes: Operate a preset on-chip ROM control register to turn off the power and clock of the on-chip ROM.

4. The SOC chip reset processing method according to claim 3, wherein The preset on-chip ROM control register is reset to the default value when the SOC chip undergoes a cold reset, and this default value indicates enabling the power and clock of the on-chip ROM.

5. A reset processing device for an SOC chip, characterized in that, Including: A reset handler writing module, used to write the reset handler into the on-chip RAM starting from the starting address of the on-chip RAM; A RAM address mapping module, used to map the starting address of the on-chip RAM to the CPU reset vector address; An SOC chip reset processing module, used to when the SOC chip undergoes a non-cold reset, read and execute the reset handler starting from the starting address of the on-chip RAM to perform corresponding reset processing; Among them, the mapping of the starting address of the on-chip RAM to the CPU reset vector address includes: Operate the preset on-chip RAM mapping register to map the starting address of the on-chip RAM to the CPU reset vector address; Wherein, the preset on-chip RAM mapping register is reset to the default value when a cold reset occurs in the SOC chip; Wherein, if the starting address of the on-chip ROM of the SOC chip is the same as the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip RAM is not mapped; if the starting address of the on-chip ROM is different from the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the starting address of the on-chip ROM is mapped to the CPU reset vector address; Wherein, the SOC chip reset processing method further includes: When a cold reset occurs in the SOC chip, read and execute the BootROM program starting from the starting address of the on-chip ROM; After the BootROM program is executed, execute the Bootloader program, and during the execution of the Bootloader program, starting from the starting address of the on-chip RAM, write the reset processing program into the on-chip RAM, and map the starting address of the on-chip RAM to the CPU reset vector address.

6. An SOC chip, characterized in that, Comprising: A memory for storing a computer program; A processor for executing the computer program to implement the SOC chip reset processing method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, For storing a computer program, and the computer program when executed by a processor implements the SOC chip reset processing method according to any one of claims 1 to 4.

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