Chip circuit layout method, circuit design method, device, equipment and medium

Abstract

Embodiments of the present application disclose a chip circuit layout method, a circuit design method, a device, equipment and a medium. The method comprises: obtaining an initial layout result of a to-be-designed circuit, the to-be-designed circuit comprising at least two macro modules, and a layout halo being arranged around the macro modules; determining layout halo graphic coordinate information corresponding to the at least two macro modules; performing coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combining the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons; calculating a coordinate difference value of each adjacent two points in the one or more polygons; and determining whether layout violations exist in the at least two macro modules based on the coordinate difference value of each adjacent two points in the one or more polygons. In this way, the number of layout iterations caused by design rule checking due to macro module placement can be reduced, and the time of the entire chip design can be saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and in particular to a chip circuit layout method, a circuit design method, a device, equipment and a medium. BACKGROUND

[0002] With the reduction of process size, the integration of chips is enhanced, and the design scale and difficulty are also increased. Usually, the scale of a module in a chip is several million standard cells, and several hundred macro modules, and the time of one round of automatic layout and routing (APR) is as high as tens of hours. With the gradual evolution of process from 12nm to 7nm or even 5nm, the types of design rule check (DRC) of chips are more and more, and the types are more and more complex. The project is often delayed for a long time due to the subtle problems of macro module placement that are not found. How to reduce the DRC caused by improper layout to cause a new round of layout iteration to shorten the project process becomes particularly important.

[0003] The DRC is more and more strict in the 7nm layout. For the DRC problems such as incorrect physical cell type or too small polysilicon width caused by the non-complete alignment of macro module placement, these problems often exist and cannot be easily solved in the APR tool. Although there are some solutions at present, these solutions are either cumbersome and time-consuming or need to increase the layout blockage, but will waste the area of two blockage sizes and change the timing, need a new round of timing optimization to repair, and even cause a new layout and routing, which has certain limitations. SUMMARY

[0004] The present application provides a chip circuit layout method, a circuit design method, a device, equipment and a medium, which can reduce the number of layout iterations caused by DRC due to macro module placement, save the workload of macro module placement in chip design, and also avoid the area waste caused by the simultaneous increase of layout blockage on both sides of the macro module.

[0005] The technical solution of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a chip circuit layout method, which comprises:

[0007] obtaining an initial layout result of a to-be-designed circuit, wherein the to-be-designed circuit comprises at least two macro modules, and a layout halo is arranged around the macro module;

[0008] determining layout halo pattern coordinate information corresponding to the at least two macro modules;

[0009] perform coordinate operation on the layout halo pattern coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons;

[0010] calculate a coordinate difference value of each adjacent two points in the one or more polygons; and

[0011] determine whether there is a layout violation of the at least two macro modules based on the coordinate difference value of each adjacent two points in the one or more polygons.

[0012] In a second aspect, an embodiment of the present application provides a circuit design method based on an electronic design automation (EDA) tool, which comprises:

[0013] receiving at least two macro modules of a circuit to be designed, and a layout halo being arranged around each macro module;

[0014] generating an initial layout result of the circuit to be designed;

[0015] determining layout halo pattern coordinate information corresponding to the at least two macro modules;

[0016] according to the determined layout halo pattern coordinate information, when it is determined that there is a layout violation of the at least two macro modules, repairing the layout violation according to a preset repair strategy, updating the initial layout result based on the obtained layout repair result, and returning to the step of determining the layout halo pattern coordinate information corresponding to the at least two macro modules until there is no layout violation of the at least two macro modules, so as to determine a target layout result of the circuit to be designed;

[0017] performing a wiring operation on the circuit to be designed based on the target layout result to obtain a wiring result of the circuit to be designed.

[0018] In a third aspect, an embodiment of the present application provides a layout device of a chip circuit, which comprises an obtaining unit, a determining unit and an operation unit; wherein,

[0019] the obtaining unit is configured to obtain an initial layout result of a circuit to be designed, wherein the circuit to be designed comprises at least two macro modules, and a layout halo is arranged around each macro module;

[0020] the determining unit is configured to determine layout halo pattern coordinate information corresponding to the at least two macro modules;

[0021] The operation unit is configured to perform coordinate operation on the layout halo pattern coordinate information corresponding to the at least two macro modules, combine the at least two macro modules into one or more polygons, obtain coordinate information of the one or more polygons, and calculate a coordinate difference value of each adjacent two points in the one or more polygons.

[0022] The determination unit is further configured to determine whether the at least two macro modules exist layout violations based on the coordinate difference value of each adjacent two points in the one or more polygons.

[0023] In a fourth aspect, an embodiment of the present application provides a circuit design device, which comprises a receiving unit, a layout unit and a wiring unit; wherein,

[0024] The receiving unit is configured to receive at least two macro modules of a circuit to be designed, and a layout halo is arranged around the macro modules.

[0025] The layout unit is configured to generate an initial layout result of the circuit to be designed, determine layout halo pattern coordinate information corresponding to the at least two macro modules, when it is determined that the at least two macro modules exist layout violations, repair the layout violations according to a preset repair strategy, update the initial layout result based on the obtained layout repair result, return to the step of determining the layout halo pattern coordinate information corresponding to the at least two macro modules, until the at least two macro modules do not exist layout violations, to determine a target layout result of the circuit to be designed.

[0026] The wiring unit is configured to perform a wiring operation on the circuit to be designed according to the target layout result, to obtain a wiring result of the circuit to be designed.

[0027] In a fifth aspect, an embodiment of the present application provides a chip circuit layout device, which comprises a memory and a processor; wherein,

[0028] The memory is configured to store executable instructions capable of running on the processor.

[0029] The processor is configured to execute the method according to the first aspect when running the executable instructions.

[0030] In a sixth aspect, an embodiment of the present application provides an EDA device, which comprises a memory and a processor; wherein,

[0031] The memory is configured to store executable instructions capable of running on the processor.

[0032] The processor is configured to execute the executable instructions to perform the method of the second aspect.

[0033] In a seventh aspect, an embodiment of the present application provides a computer storage medium, which stores a computer program, and the computer program is executed by a layout device of a chip circuit to implement the method of the first aspect, or is executed by an EDA device to implement the method of the second aspect.

[0034] The layout method, the circuit design method, the device, the equipment and the medium provided by the embodiment of the present application are used for obtaining an initial layout result of a to-be-designed circuit, the to-be-designed circuit comprises at least two macro modules, and a layout halo is arranged around the macro module; determining layout halo graphic coordinate information corresponding to the at least two macro modules; performing coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combining the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons; calculating a coordinate difference value of each adjacent two points in the one or more polygons; and determining whether there is a layout violation of the at least two macro modules based on the coordinate difference value of each adjacent two points in the one or more polygons. In this way, the coordinate difference value of each adjacent two points in the one or more polygons is used to determine whether there is a layout violation of the at least two macro modules, so that the number of layout iterations caused by DRC due to macro module placement can be reduced, the workload of macro module placement in chip design can be saved, and the time of the entire chip design can be saved. In addition, in the case where it is determined that there is a layout violation, the layout violation repair of the present application can also avoid the area waste caused by the simultaneous increase of layout blockage on both sides of the macro module. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A common problem diagram of macro module placement provided by the related art;

[0036] Figure 2 A flowchart of a design rule check provided by the related art;

[0037] Figure 3 A flowchart of a layout method of a chip circuit provided by an embodiment of the present application;

[0038] Figure 4 An application scenario diagram of a preset repair strategy provided by an embodiment of the present application;

[0039] Figure 5 Another application scenario diagram of a preset repair strategy provided by an embodiment of the present application;

[0040] Figure 6Another flowchart of a chip circuit layout method provided by the embodiment of the present application is shown in FIG. 6;

[0041] Figure 7 A detailed flowchart of a chip circuit layout method provided by the embodiment of the present application is shown in FIG. 7;

[0042] Figure 8 A flowchart of a circuit design method based on EDA tools provided by the embodiment of the present application is shown in FIG. 8;

[0043] Figure 9 A component structure diagram of a chip circuit layout device provided by the embodiment of the present application is shown in FIG. 9;

[0044] Figure 10 A hardware structure diagram of a chip circuit layout device provided by the embodiment of the present application is shown in FIG. 10;

[0045] Figure 11 A component structure diagram of a circuit design device provided by the embodiment of the present application is shown in FIG. 11;

[0046] Figure 12 A hardware structure diagram of an EDA device provided by the embodiment of the present application is shown in FIG. 12. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, but not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings.

[0048] With the rapid development of integrated circuit design technology, an electronic system or sub-system can be completely integrated on a chip, i.e. system on chip (SoC) integration. Moreover, with the increase of design scale, the improvement of circuit performance and the great increase of design complexity, higher requirements are put forward for the design of the chip.

[0049] It should be understood that as the process size is reduced, the integration is enhanced, the design scale and difficulty are also increased, the module scale in the chip is several million standard cells, hundreds of macro modules, and the time of one round of layout and wiring (Auto Place and Route, APR) is also greatly increased, up to tens of hours. With the evolution of process from 12nm, 7nm to 5nm, the types of design rule check (DRC) are more and more, the types are more and more complex, and the project is often delayed for a long time due to the subtle problems of macro module placement that are not found, which will be a very tricky problem in the later stage of the project. At this time, how to reduce the DRC caused by improper layout to reduce the iteration of one round of layout to shorten the project process becomes particularly important.

[0050] The design rule check is more and more strict in the layout of 7nm. Referring to Figure 1 , a common problem of macro module placement provided by the related art is shown. As Figure 1 shown, in the current page 10, the rectangular area filled with the grid represents the macro module, the black filled area represents the layout halo (Placement Halo), and the small rectangular area filled with white represents the physical cell. In Figure 1 , it can be clearly seen that the placement of two macro modules is in an incomplete alignment state.

[0051] For the incomplete alignment of the macro module placement, the physical cell type is incorrect when the edge distance (represented by Δd) is less than the first preset characteristic value (which can be represented by w1) required by the design rule, or the polysilicon width is too small when the edge distance (represented by Δd) is less than the second preset characteristic value (which can be represented by w2) required by the design rule, and other DRC problems. Such DRC problems often exist and cannot be easily solved in the APR tool. For the above problems, the existing technical solutions include the following two kinds: one is to insert a logic-independent filler after each layout is completed, extract the layout, such as graphic design system (GDS), insert dummy oxide and polysilicon (Dummy Oxide and Poly, Dummy ODPO), and use a preset tool (such as Calibre tool) to check the iteration process of DRC; the other is to move the physical cell and the standard cell near it in the design after the layout and wiring are completed, and increase the layout blockage for the above problem area.

[0052] However, the two technical solutions have their respective disadvantages. For the first technical solution, Figure 2 a flowchart of a design rule check provided by the related art is shown. As Figure 2As shown, the flow can include:

[0053] S201: initializing a database system (DBS);

[0054] S202: inserting a filter (Filter);

[0055] S203: extracting a layout;

[0056] S204: inserting dummy oxide and polysilicon;

[0057] S205: checking a design rule problem of a base layer (Base Layer) by using a preset tool;

[0058] S206: determining whether the Base Layer has the design rule problem;

[0059] S207: if the determination result is no, adjusting a layout and reiteratively checking;

[0060] S208: if the determination result is yes, placing a standard cell.

[0061] It should be noted that after initializing the DBS, the Filter is inserted, and then the layout is extracted, specifically, the layout can be extracted by extracting GDS; then, based on the layout, the dummy oxide and polysilicon (Dummy ODPO) are inserted, and the design rule problem (DRC problem) of the Base Layer is checked by using a preset tool (Calibre tool); if the Base Layer has the DRC problem, the layout will be continuously adjusted, and the reiterative checking will be performed until the Base Layer does not have the DRC problem, at which time the placement of the standard cell can be performed.

[0062] It should be further noted that in the technical solution, one round of iteration time is several hours, and S204 and S205 are executed by a sign-off tool, and the remaining steps are executed by an automatic layout and routing (APR) tool. Here, the APR tool only provides data for the sign-off tool to determine that the Base Layer has the DRC problem.

[0063] That is, for the flow of Figure 2 , a flow example of quickly checking the design rule by using the sign-off tool on the data of the layout of millions of standard cell modules is shown, and one round of quick checking needs to consume several hours, and the above steps need to be repeated after each layout, which is very tedious and time-consuming.

[0064] For the second technical solution, if the DRC problem is found after the layout and routing is completed and the timing is optimized, the layout and routing is performed again, but a lot of time is spent. Another solution is to manually move the physical cells and the standard cells near the physical cells in the specific location where the design rule violation exists, and add layout blocks to prevent the standard cells from being placed in the subsequent steps to generate the violation. This solution wastes two block sizes of area and changes the timing, which needs a new round of timing optimization to fix, and if there is no space near the standard cells to move the standard cells, the solution cannot be implemented, and the layout and routing need to be performed again, which has certain limitations.

[0065] Therefore, an embodiment of the present application provides a layout method of a chip circuit. The basic idea of the method is as follows: obtaining an initial layout result of a to-be-designed circuit, the to-be-designed circuit comprising at least two macro modules, and a layout halo being arranged around the macro modules; determining layout halo graphic coordinate information corresponding to the at least two macro modules; performing coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combining the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons; calculating a coordinate difference value of each two adjacent points in the one or more polygons; and determining whether the at least two macro modules have a layout violation based on the coordinate difference value of each two adjacent points in the one or more polygons. In this way, the coordinate difference value of each two adjacent points in the one or more polygons is used to determine whether the at least two macro modules have a layout violation, so that the number of layout iterations caused by the DRC due to the placement of the macro modules can be reduced, the workload of the placement of the macro modules in the chip design can be saved, and the time of the entire chip design can be saved. In addition, in the case where it is determined that there is a layout violation, the layout violation repair of the present application can also avoid the waste of area caused by the layout blocks being added on both sides of the macro modules.

[0066] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0067] In an embodiment of the present application, referring to Figure 3 which shows a flowchart of a layout method of a chip circuit provided by an embodiment of the present application. As Figure 3 shown, the method can comprise:

[0068] S301: obtaining an initial layout result of a to-be-designed circuit, wherein the to-be-designed circuit comprises at least two macro modules, and a layout halo is arranged around the macro modules.

[0069] It should be noted that the chip circuit layout method is applied to a chip circuit layout device, or a chip circuit layout apparatus or an Electronics Design Automation (EDA) apparatus integrated with the device.

[0070] It should be further noted that the to-be-designed circuit of the chip can be subdivided into a plurality of macro modules according to function blocks. Here, the macro module can be a memory, an array, a function module, and the like, and the embodiments of the present application do not make any limitation.

[0071] In addition, the method of the embodiments of the present application is performed after an initial layout design in which macro module placement has been preliminarily completed. In the initial layout result, in order to prevent wire DRC, such as preventing the connection line interface of the macro module from being connected to the connection line interface of the surrounding standard cell, a layout halo (i.e., Halo) is set around each macro module.

[0072] S302: Determine layout halo graphic coordinate information corresponding to the at least two macro modules.

[0073] It should be noted that, for the initial layout result of the to-be-designed circuit, the graphic coordinates of the halo around each macro module can be captured, that is, the layout halo graphic coordinate information corresponding to each macro module of the at least two macro modules is determined.

[0074] Here, for the macro module, the layout halo graphic can be determined by two points, and then the layout halo graphic coordinate information can also be composed of the coordinate information of the two points. In general, the two points can include a lower left corner point (coordinates (x lli ,y lli )) and an upper right corner point (coordinates (x uri ,y uri )). That is, the layout halo graphic coordinate information corresponding to the i-th macro module can be (x lli ,y lli ,x uri ,y uri ), i is an integer greater than zero.

[0075] It should be further noted that the method can further include: setting a first list. The first list is used to store the layout halo graphic coordinate information corresponding to the at least two macro modules. In other words, after the layout halo graphic coordinate information corresponding to the at least two macro modules is obtained, it can be placed in the first list.

[0076] S303: Perform coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons.

[0077] It should be noted that after obtaining the layout halo graphic coordinate information corresponding to the at least two macro modules, coordinate operation can be performed on the layout halo graphic coordinate information corresponding to the at least two macro modules, the at least two macro modules can be combined into one or more polygons, and coordinate information of the one or more polygons can be obtained. Specifically, in some embodiments, for S303, the coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, and the combination of the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons can include:

[0078] Perform coordinate extension on the layout halo graphic coordinate information corresponding to the at least two macro modules to obtain a plurality of new graphic coordinate information; and

[0079] Perform AND operation on the layout halo graphic coordinate information corresponding to the at least two macro modules and the plurality of new graphic coordinate information, and combine the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons.

[0080] Here, the coordinate extension can include coordinate upward extension and / or coordinate downward extension. The extension distance value is a preset value, that is, an arbitrary value set by a designer, or the preset value can also be half of the minimum macro module height, and the embodiments of the present application do not make any limitation on this.

[0081] It should also be noted that the method can further include setting a second list. The second list is used to store the obtained plurality of new graphic coordinate information. In other words, after performing coordinate extension on the layout halo graphic coordinate information corresponding to the at least two macro modules, the plurality of new graphic coordinate information obtained can be placed in the second list.

[0082] In this way, in some embodiments, the AND operation on the layout halo graphic coordinate information corresponding to the at least two macro modules and the plurality of new graphic coordinate information, and the combination of the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons can include: performing AND operation on the layout halo graphic coordinate information placed in the first list and the new graphic coordinate information placed in the second list, combining the at least two macro modules into one or more polygons, and obtaining the coordinate information of the one or more polygons.

[0083] Specifically, on one hand, the layout halo figure coordinate information corresponding to the obtained at least two macro modules is placed in a first list; on the other hand, the layout halo figure coordinate information can also be each extended downward and upward by a preset value (for example, half of the minimum macro module height h, that is, h / 2), at this time, a plurality of new figure coordinate information (x lli , y lli -h / 2, x uri , y uri +h / 2) can be obtained, and the new figure coordinate information is placed in a second list. The figure coordinates in the two lists are respectively subjected to an AND operation, and one or more polygon coordinate information can be obtained, and the one or more polygons can be an area capable of covering the macro module and the halo. The equation of the specific process is shown in the following formula (1).

[0084] (x ll1 , y ll1 , x ur1 , y ur1 ) && (x ll2 , y ll2 , x ur2 , y ur2 ) &&......&&(x lln , y lln , x urn , y urn )→(x 11 , y 11 .....x 1i , y 1i ),......, (x j1 , y j1 .....x ji , y ji ) (1)

[0085] Wherein, “&&” represents an AND operator, and “→” represents an implication operator.

[0086] As can be seen from formula (1), after the figure coordinates in the two lists are subjected to an AND operation, one or more polygon coordinate information can be obtained. For example, (x 11 , y 11 .....x 1i , y 1i ) represents the first polygon coordinate information, (x j1 , y j1 .....x ji , y ji) represents coordinate information of the jth polygon, j being an integer greater than zero. In addition, for each polygon, taking the jth polygon as an example, the coordinate information of the polygon can include coordinate information of a plurality of points, such as (x j1 , y j1 ),..., (x ji , y ji ), and so on, i being an integer greater than zero.

[0087] S304: calculating coordinate difference values of each adjacent two points in the one or more polygons.

[0088] It should be noted that after obtaining the coordinate information of the one or more polygons, the image obtained at this time is one or more polygons. By traversing the coordinate information of each point in each polygon, the coordinate difference values of each adjacent two points in the one or more polygons can be calculated.

[0089] It should be further noted that the coordinate information (x, y) can include horizontal coordinate information (denoted by x) and vertical coordinate information (denoted by y). In some embodiments, for S304, the calculation of the coordinate difference values of each adjacent two points in the one or more polygons can include:

[0090] traversing the horizontal coordinate information of each point in the one or more polygons, calculating the horizontal coordinate difference values of each adjacent two points by means of difference calculation on the horizontal coordinate information of each adjacent two points; traversing the vertical coordinate information of each point in the one or more polygons, calculating the vertical coordinate difference values of each adjacent two points by means of difference calculation on the vertical coordinate information of each adjacent two points; and

[0091]

[0092] obtaining the coordinate difference values of each adjacent two points in the one or more polygons according to the horizontal coordinate difference values and the vertical coordinate difference values of each adjacent two points in the one or more polygons.

[0093] It should be noted that traversing the coordinate information of each point in the one or more polygons, for the calculation of the horizontal coordinate difference values, the horizontal coordinate difference values of each adjacent two points in the one or more polygons can be obtained by traversing the horizontal coordinate information of each point in the one or more polygons and calculating the difference of the horizontal coordinate information of each adjacent two points; for the calculation of the vertical coordinate difference values, the vertical coordinate difference values of each adjacent two points in the one or more polygons can be obtained by traversing the vertical coordinate information of each point in the one or more polygons and calculating the difference of the vertical coordinate information of each adjacent two points.

[0094] ​Thus, after obtaining the horizontal coordinate difference and the vertical coordinate difference of each two adjacent points in the one or more polygons, the coordinate difference of each two adjacent points in the one or more polygons can be determined, so as to subsequently determine whether the at least two macro modules exist layout violation.

[0095] S305: determining whether the at least two macro modules exist layout violation based on the coordinate difference of each two adjacent points in the one or more polygons.

[0096] It should be noted that for S305, the determination of whether the at least two macro modules exist layout violation based on the coordinate difference of each two adjacent points in the one or more polygons can include:

[0097] comparing the coordinate difference of each two adjacent points with a first preset characteristic value, wherein the coordinate difference includes a horizontal coordinate difference and a vertical coordinate difference;

[0098] if the horizontal coordinate difference of the two adjacent points is greater than 0 and less than the first preset characteristic value, or the vertical coordinate difference of the two adjacent points is greater than 0 and less than the first preset characteristic value, it is determined that the at least two macro modules exist layout violation; and

[0099] if the horizontal coordinate difference of the two adjacent points is greater than or equal to the first preset characteristic value and the vertical coordinate difference of the two adjacent points is greater than or equal to the first preset characteristic value, it is determined that the at least two macro modules do not exist layout violation.

[0100] Here, the first preset characteristic value is a preset characteristic value, which can be denoted as w1. The value of w1 can be the minimum distance that meets the DRC check requirement of the design rule. If the horizontal coordinate difference or the vertical coordinate difference (i.e. the edge distance, which can be denoted as Δd) of each two adjacent points is less than w1, layout violation exists. On the contrary, if the horizontal coordinate difference and the vertical coordinate difference of each two adjacent points are both greater than or equal to w1, it is indicated that the at least two macro modules do not exist layout violation. The specific process is shown in the following equation (2).

[0101] 0 < x n -x n-1 < w1 || 0 < y n -y n-1 < w1 (2)

[0102] That is, if the above formula (2) is satisfied, it indicates that there is a layout violation in the at least two macro modules. Further, in some embodiments, the method can further include: setting a third list. Here, the third list is used to store the coordinate information of the adjacent two points satisfying the above formula (2) and the corresponding horizontal coordinate difference value or vertical coordinate difference value.

[0103] In other words, for S305, after obtaining the coordinate difference value of each adjacent two points in one or more polygons, the method can further include:

[0104] setting a preset list, wherein if the horizontal coordinate difference value of the adjacent two points is greater than 0 and less than a first preset characteristic value, or the vertical coordinate difference value of the adjacent two points is greater than 0 and less than the first preset characteristic value, the coordinate information of the adjacent two points and the corresponding horizontal coordinate difference value or vertical coordinate difference value are placed in the preset list.

[0105] It should be noted that the preset list here is the third list mentioned in the embodiments of the present application. After setting the preset list (or the third list), if the horizontal coordinate difference value of the adjacent two points is greater than 0 and less than the first preset characteristic value, the coordinate information of the adjacent two points and the corresponding horizontal coordinate difference value can be placed in the preset list; or if the vertical coordinate difference value of the adjacent two points is greater than 0 and less than the first preset characteristic value, the coordinate information of the adjacent two points and the corresponding vertical coordinate difference value can be placed in the preset list.

[0106] It should be further noted that after setting the preset list, the method can further include: emptying the preset list. In this way, in some embodiments, after placing the coordinate information of the adjacent two points and the corresponding horizontal coordinate difference value or vertical coordinate difference value in the preset list, the method can further include:

[0107] determining whether the preset list is empty;

[0108] if the preset list is not empty, determining that the at least two macro modules have layout violations;

[0109] if the preset list is empty, determining that the at least two macro modules do not have layout violations.

[0110] It should be noted that if the preset list is empty, it indicates that there is no case where the horizontal coordinate difference value or the vertical coordinate difference value is less than the first preset characteristic value (w1), and there is no layout violation in the initial layout result; if the preset list is not empty, it indicates that there is a case where the horizontal coordinate difference value or the vertical coordinate difference value is less than the first preset characteristic value (w1), and there is a layout violation in the initial layout result.

[0111] In some embodiments, after determining whether the at least two macro modules exist layout violations, the method can further include:

[0112] When it is determined that the at least two macro modules exist layout violations, repairing the layout violations according to a preset repair strategy.

[0113] It should be noted that in some embodiments, the method can further include: when the at least two macro modules do not exist layout violations, determining a target layout result of the to-be-designed circuit.

[0114] That is, after obtaining the coordinate difference value of each adjacent two points in one or more polygons, specifically, after obtaining the horizontal coordinate difference value and the vertical coordinate difference value of each adjacent two points in one or more polygons, the first preset feature value (w1) is compared with the horizontal coordinate difference value and the vertical coordinate difference value, and according to the comparison result, it is determined whether the at least two macro modules exist layout violations. Specifically, if it is determined that the at least two macro modules exist layout violations, the layout violations can be repaired according to a preset repair strategy; if it is determined that the at least two macro modules do not exist layout violations, a target layout result of the to-be-designed circuit can be determined.

[0115] In the embodiments of the present application, when it is determined that the at least two macro modules exist layout violations, after repairing the layout violations according to the preset repair strategy, it is necessary to return to step S302 until the at least two macro modules do not exist layout violations. In some embodiments, the method can further include:

[0116] Obtaining a layout repair result of the to-be-designed circuit;

[0117] Updating the initial layout result based on the layout repair result, returning to execute the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules until the at least two macro modules do not exist layout violations.

[0118] That is, after repairing the layout violations according to the preset repair strategy, a layout repair result of the to-be-designed circuit can be obtained; then the initial layout result is updated based on the layout repair result, and the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules is returned to execute until the at least two macro modules do not exist layout violations.

[0119] It should be noted that when it is determined that the at least two macro modules exist layout violation, at this time, the layout violation can be repaired according to a preset repair strategy. Here, the preset repair strategy is to set a corresponding repair strategy according to different violation conditions, such as adjusting the positions of the two macro modules to be aligned, or adding a layout block in the region corresponding to the layout violation, etc. The following will be described in detail in combination with three layout violation conditions.

[0120] In a possible implementation, the repairing the layout violation according to the preset repair strategy when it is determined that the at least two macro modules exist layout violation can include:

[0121] If there are two coordinate difference values of the same size in the preset list and the coordinate difference values are less than a second preset characteristic value, the coordinate information of four points corresponding to the two coordinate difference values of the same size is obtained from the preset list.

[0122] According to the obtained coordinate information of the four points, two macro modules contained in the four points are determined, and the positions of the two macro modules are adjusted to be aligned, so as to repair the layout violation.

[0123] It should be noted that the second preset characteristic value can be represented by w2. Here, the value of w2 can be ten times the minimum standard cell width that meets the design rule requirement.

[0124] Specifically, if there are two horizontal coordinate difference values of the same size in the preset list and the horizontal coordinate difference values are less than w2, the coordinate information of four points corresponding to the two horizontal coordinate difference values of the same size is obtained from the preset list; then according to the obtained coordinate information of the four points, two macro modules contained in the four points are determined, and the positions of the two macro modules are adjusted to be aligned along the horizontal direction, so as to repair the layout violation. Or, if there are two vertical coordinate difference values of the same size in the preset list and the vertical coordinate difference values are less than w2, the coordinate information of four points corresponding to the two vertical coordinate difference values of the same size is obtained from the preset list; then according to the obtained coordinate information of the four points, two macro modules contained in the four points are determined, and the positions of the two macro modules are adjusted to be aligned along the vertical direction, so as to repair the layout violation.

[0125] Exemplarily, as Figure 4As shown, for the two macro modules shown in (a), it can be seen from the positions marked by the circles that the two macro modules can have layout violations. At this time, the layout halo graphic coordinate information corresponding to the two macro modules is extended in coordinates to obtain four new graphic coordinate information; by performing an AND operation on the layout halo graphic coordinate information corresponding to the two macro modules and the four new graphic coordinate information, a polygon as shown in (b) can be obtained. By traversing each point in the polygon, the coordinate difference of each adjacent two points is calculated, and if the horizontal coordinate difference or the vertical coordinate difference of the adjacent two points is greater than 0 and less than w1, that is, it meets the above formula (2), then the coordinate information of the adjacent two points and the corresponding horizontal coordinate difference or vertical coordinate difference are placed in a preset list, and it is indicated that the two macro modules have layout violations. At this time, it can be further judged whether there are two coordinate differences of the same size in the preset list and the coordinate difference is less than a second preset characteristic value (w2). If there are two horizontal coordinate differences of the same size in the preset list and the coordinate difference is less than w2, specifically as shown in Figure 4 (b) of FIG. 8, the horizontal coordinate difference (denoted by Δd) of the two marked positions is of the same size and Δd < w2; then the coordinate information of the four points can be obtained, and then the two macro modules covered by the four points are determined according to the coordinate information of the four points, and then the two macro modules are aligned in position, specifically as shown in Figure 4 (c) of FIG. 8, at this time, the two macro modules are in an aligned state, that is, the repair of the layout violation is realized.

[0126] In another possible implementation, when it is determined that the at least two macro modules have layout violations, the layout violations can be repaired according to a preset repair strategy, which can include:

[0127] If the horizontal coordinate information or the vertical coordinate information of the four points in the preset list is the same, it is determined that the two macro modules contained by the four points, and the two macro modules are adjusted to be aligned in position to realize the repair of the layout violation.

[0128] In another possible implementation, when it is determined that the at least two macro modules have layout violations, the layout violations can be repaired according to a preset repair strategy, which can include:

[0129] If the horizontal coordinate information or the vertical coordinate information of the four points in the preset list is not the same, it is determined that the two macro modules contained by the four points, and a layout block is added in the area corresponding to the layout violation to realize the repair of the layout violation.

[0130] It should be noted that after obtaining the preset list, if there are four points with the same horizontal coordinate information or the same vertical coordinate information in the preset list, at this time, the corresponding two macro modules can be first positionally aligned to achieve repair of the layout violation, and obtain the layout repair result of the to-be-designed circuit. If there are no four points with the same horizontal coordinate information or the same vertical coordinate information in the preset list, then the macro module with a coordinate difference value less than w1 on the side of the layout violation can be added with a layout block (such as halo) with a coordinate difference value, so as to not only achieve repair of the layout violation and obtain the layout repair result of the to-be-designed circuit, but also avoid area waste caused by adding layout blocks on the left and right sides of the macro module.

[0131] It should also be noted that for the layout repair result of the to-be-designed circuit, the initial layout result can also be updated by using the layout repair result, and then S302-S305 are repeatedly executed until the coordinate difference value of each adjacent two points in one or more polygons is not less than the first preset value (w1), so that there is no layout violation caused by macro module placement in the to-be-designed circuit.

[0132] Exemplarily, as shown in Figure 5 , after the AND operation, for the two macro modules shown in (a), it can be seen from the positions marked by the circles that since the horizontal coordinate difference value Δd < w1, it indicates that there is a layout violation between the two macro modules. At this time, the two macro modules need to be moved to be positionally aligned, and specifically as shown in Figure 5 (b), the left side of the two macro modules is already in an aligned state, and the layout repair result of the to-be-designed circuit is obtained. At this time, the layout repair result obtained at this time is taken as the initial layout result, and S302-S304 are re-executed, and a new coordinate difference value can be obtained, as shown in the positions marked by the circles in Figure 5 (b). Then S305 is continued to be executed according to the new coordinate difference value, at this time, two situations can be obtained: if the new coordinate difference value Δd > w1, it indicates that there is no layout violation between the two macro modules at this time, and no processing is needed, that is, Figure 5 (c) shows; if the new coordinate difference value Δd < w1, it indicates that there is a layout violation between the two macro modules at this time, and at this time, a layout block can be added in the region corresponding to the layout violation to achieve repair of the layout violation, that is, Figure 5 (d) shows.

[0133] The embodiment provides a chip circuit layout method. The method comprises the following steps: obtaining an initial layout result of a to-be-designed circuit, wherein the to-be-designed circuit comprises at least two macro modules, and a layout halo is arranged around each macro module; determining layout halo graphic coordinate information corresponding to the at least two macro modules; performing coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, combining the at least two macro modules into one or more polygons, and obtaining coordinate information of the one or more polygons; calculating a coordinate difference value of each two adjacent points in the one or more polygons; and determining whether layout violation exists in the at least two macro modules based on the coordinate difference value of each two adjacent points in the one or more polygons. In this way, the coordinate difference value of each two adjacent points is used to determine whether layout violation exists in the at least two macro modules, and the layout violation is repaired according to a preset repair strategy, so that the number of layout iterations caused by DRC due to macro module placement can be reduced, the workload of macro module placement in chip design can be saved, and the time of the entire chip design can be saved. In addition, when the layout violation is repaired, area waste caused by simultaneous increase of layout blockage on both sides of the macro module can be avoided.

[0134] In another embodiment of the present application, referring to Figure 6 which shows a flowchart of another chip circuit layout method provided by the embodiment of the present application. As shown in Figure 6 , the method can comprise the following steps:

[0135] S601: obtaining an initial layout result of a to-be-designed circuit; wherein the to-be-designed circuit comprises at least two macro modules, and a layout halo is arranged around each macro module;

[0136] S602: determining layout halo graphic coordinate information corresponding to the at least two macro modules;

[0137] S603: performing coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, combining the at least two macro modules into one or more polygons, and obtaining coordinate information of the one or more polygons;

[0138] S604: calculating a coordinate difference value of each two adjacent points in the one or more polygons;

[0139] It should be noted that, for the to-be-designed circuit of the chip, according to the function block subdivision, a plurality of macro modules can be included. In addition, the method of the embodiment of the present application is performed after the initial layout design of the macro module placement is preliminarily completed. In the initial layout result, in order to prevent wire DRC, a Halo is arranged around each macro module.

[0140] It should be noted that the execution steps of S601-S604 are the same as the execution steps of S301-S304 in the foregoing embodiment, and the specific execution operations can be seen from the foregoing content. In this way, after the coordinate difference of each two adjacent points in one or more polygons is calculated, it can be determined whether there is a layout violation in at least two macro modules in the circuit to be designed according to the coordinate difference.

[0141] S605: judging whether there is a layout violation in the at least two macro modules based on the coordinate difference of each two adjacent points in the one or more polygons;

[0142] S606: if the judgment result is yes, repairing the layout violation according to a preset repair strategy, and returning to execute S602;

[0143] S607: if the judgment result is no, determining the current layout result as the target layout result of the circuit to be designed.

[0144] It should be noted that for S605, for judging whether there is a layout violation in the at least two macro modules, if the judgment result is yes, that is, it is determined that there is a layout violation in the at least two macro modules, then S606 can be executed, that is, the layout violation is repaired according to the preset repair strategy to obtain the layout repair result of the circuit to be designed, and then the layout repair result can be taken as the initial layout result, and the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules is continued to be executed until it is determined that there is no layout violation in the at least two macro modules. That is, if the judgment result is no, that is, it is determined that there is no layout violation in the at least two macro modules, then S607 can be executed, at this time the current obtained layout result is the target layout result of the circuit to be designed, and other operations such as wiring operation, timing analysis operation, etc. can be continued to be executed.

[0145] In other words, after obtaining the initial layout result of the circuit to be designed, the layout halo graphic coordinate information corresponding to the at least two macro modules can be obtained; then the layout halo graphic coordinate information of the macro modules is extended downward and upward to obtain new graphic coordinate information; and the and / or not operation of the graphic coordinate information is used to automatically check and correct the DRC problem that is prone to occur when the macro module is placed and cannot be solved by the back-end tool, thereby reducing the repeated layout iteration caused by the DRC problem.

[0146] The embodiment provides a chip circuit layout method, and the specific implementation of the foregoing embodiment is described in detail through the foregoing embodiment.

[0147] In another embodiment of the present application, referring to Figure 7 which shows a detailed flowchart of a chip circuit layout method provided by the embodiment of the present application. As shown in Figure 7 , the method can include:

[0148] S701: initializing a database system;

[0149] S702: acquiring layout halo graphic coordinate information corresponding to at least two macro modules;

[0150] It should be noted that after the DBS is initialized, the halo graphic coordinate information corresponding to each macro module in the at least two macro modules can be acquired according to an initial layout result in which the macro module placement has been preliminarily completed. Here, a halo is arranged around each macro module.

[0151] S703: performing downward and upward extension on the layout halo graphic coordinate information to obtain a plurality of new graphic coordinate information;

[0152] S704: performing a coordinate intersection operation on the layout halo graphic coordinate information and the plurality of new graphic coordinate information to obtain coordinate information of one or more polygons;

[0153] S705: calculating a coordinate difference Δd of each adjacent two points in the one or more polygons;

[0154] S706: judging whether Δd is less than w1;

[0155] S707: if the judgment result is no, ending the flow;

[0156] S708: if the judgment result is yes, judging whether there are two Δd of the same size and less than w2;

[0157] S709: if the judgment result is yes, aligning the two macro modules and returning to execute S702;

[0158] S710: if the judgment result is no, judging whether Δd is less than w1 and the horizontal coordinate information of the four points is the same or the vertical coordinate information of the four points is the same;

[0159] S711: If the judgment result is yes, then move and align the corresponding macro module, and return to execute S702;

[0160] S712: If the judgment result is negative, add layout blocking in the area of ​​layout violation and return to execute S702.

[0161] In other words, this application's embodiment is for designs where the macro module placement has been initially completed. At this stage, halo elements are added around the macro modules to prevent DRC (Dual Routing Control) issues. The technical solution of this application's embodiment is to capture the halo graphic coordinates (x, y, x) around each macro module. lli y lli x uri y uri The first list is placed, and the halo graphic coordinates are expanded upwards and downwards by half the height of the minimum macromodule, resulting in multiple new graphic coordinates (x). lli y lli -h / 2,x uri y uri +h / 2) is placed in the second list, and the graphic coordinates in the two lists are ANDed to obtain the graphic coordinate information of at least one polygon covered by the macro module and halo, as shown in the above formula (1).

[0162] Furthermore, since the obtained graphic is one or more polygons, each point in these polygons is traversed, and the difference between the horizontal coordinates (x) and vertical coordinates (y) of two adjacent points is calculated, as shown in equation (2) above. If there is a difference between the x or y coordinates of two adjacent points that is greater than 0 and less than w1, then the coordinate information of these two adjacent points and the corresponding coordinate difference are placed in the third list respectively; if there is no case where the difference between the x / y coordinates of two adjacent points is greater than 0 and less than w1, then it indicates that the above-mentioned violation has not occurred in the initial layout.

[0163] Furthermore, for the third list, if there are two coordinate differences of the same size that are less than w2, then extract the two macro modules contained in these four points and align them, specifically as follows: Figure 4 As shown. If four points in the third list have the same x or y coordinates, then the corresponding macro modules need to be aligned on one side first, and then the above steps are repeated; if no four points have the same x or y coordinates, then the macro modules with coordinate differences less than w1 need to have their coordinate difference incremented by the size of the halo on the violating side, and then the above steps are repeated until no two adjacent points of this polygon have coordinate differences less than w1. Specifically, as shown... Figure 5It is noted that, in the embodiment of the present application, the checking and repairing of the layout violation can be completed in several minutes, thereby saving the time of the whole chip design.

[0164] In addition, the technical solution of the embodiment of the present application is based on the advanced process of 7nm, and the same DRC rule requirement of other processes (such as 12nm, 5nm, etc.) can also be applied to reduce the iteration times of the layout.

[0165] The embodiment provides a layout method of a chip circuit. The specific implementation of the foregoing embodiment is described in detail through the foregoing embodiment, and it can be seen that, through the technical solution of the foregoing embodiment, the graphic coordinates of the macro module are used for AND operation or NOT operation, the DRC problem that is prone to occur when the macro module is placed and cannot be solved by the backend tool is automatically checked and corrected, the multiple layout iterations caused by the DRC of the macro module placement can be reduced, the workload of the macro module placement in the backend design can be saved, the timing deterioration caused by manually solving the problem in the late project can be avoided, and the area waste caused by the left and right blocking of the macro module can be avoided.

[0166] In still another embodiment of the present application, referring to Figure 8 which shows a flowchart of a circuit design method based on an EDA tool provided by the embodiment of the present application. As shown in Figure 8 , the method can include the following steps.

[0167] S801: receiving at least two macro modules of a to-be-designed circuit, and a layout halo being arranged around the macro modules;

[0168] S802: generating an initial layout result of the to-be-designed circuit;

[0169] S803: determining the layout halo graphic coordinate information corresponding to the at least two macro modules;

[0170] S804: according to the determined layout halo graphic coordinate information, when it is determined that the at least two macro modules have a layout violation, repairing the layout violation according to a preset repair strategy, updating the initial layout result based on the obtained layout repair result, returning to the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules, until the at least two macro modules do not have a layout violation, to determine a target layout result of the to-be-designed circuit;

[0171] S805: performing a wiring operation on the to-be-designed circuit according to the target layout result, to obtain a wiring result of the to-be-designed circuit.

[0172] It should be noted that the circuit design method is applied to a circuit design device or an EDA device integrated with the circuit design device. Here, the circuit design device can not only implement the layout function, but also implement the layout violation repair function, and perform the wiring operation on the target layout result repaired according to the layout violation.

[0173] In some embodiments, the repairing the layout violation according to the preset repair strategy when it is determined that the at least two macro modules have the layout violation according to the determined layout halo graphic coordinate information can include:

[0174] performing coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combining the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons;

[0175] traversing the coordinate information of each point in the one or more polygons, and determining a coordinate difference value of each adjacent two points in the one or more polygons; and

[0176] repairing the layout violation according to the preset repair strategy when it is determined that the at least two macro modules have the layout violation based on the coordinate difference value of each adjacent two points in the one or more polygons.

[0177] Further, in some embodiments, after obtaining the wiring result of the circuit to be designed, the method can further include:

[0178] performing timing analysis on the wiring result, and outputting a timing analysis report of the circuit to be designed.

[0179] That is, the circuit design device can also have a timing analysis function. In this way, after the wiring result, the timing analysis can also be performed on the wiring result to obtain the timing analysis report of the circuit to be designed.

[0180] It should be further explained that the circuit design method of the embodiments of the present application is realized based on an EDA tool, and the execution subject can be a circuit design device or an EDA device integrated with the circuit design device. Specifically, EDA can refer to a general-purpose software package of computer-aided design (CAD) developed by integrating application electronic technology, computer technology and intelligent technology on a computer platform. With the expansion of the scale of integrated circuits (IC) and the development of semiconductor technology, the importance of EDA has increased dramatically. Specifically, using EDA tools, electronic engineers can automatically process the entire process of electronic product design, performance analysis, IC design or printed circuit board (PCB) design on a computer, thereby completing the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large scale integrated circuit (VLSI) chips, i.e. through EDA equipment to realize the layout, layout violation repair, wiring and timing analysis of the circuit to be designed in the chip.

[0181] The embodiments provide a circuit design method based on an EDA tool. The method includes receiving at least two macro modules of a circuit to be designed, and setting a layout halo around the periphery of the macro modules; generating an initial layout result of the circuit to be designed; determining layout halo graphic coordinate information corresponding to the at least two macro modules; when it is determined that the at least two macro modules have layout violations, repairing the layout violations according to a preset repair strategy, updating the initial layout result based on the obtained layout repair result, and returning to the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules until there are no layout violations in the at least two macro modules, to determine a target layout result of the circuit to be designed; and performing a wiring operation on the circuit to be designed based on the target layout result, to obtain a wiring result of the circuit to be designed. In this way, not only the circuit design can be realized, but also the layout violation repair function is provided, which can reduce the multiple layout iterations caused by the DRC due to the macro module placement, save the workload of the macro module placement in the back-end design, avoid the timing deterioration caused by manually solving the problem in the late project, and avoid the area waste caused by the left and right macro modules being blocked at the same time.

[0182] In another embodiment of the present application, based on the same inventive concept as the foregoing embodiments, referring to Figure 9 which shows a schematic diagram of the composition structure of a layout device 90 of a chip circuit according to an embodiment of the present application. As shown in Figure 9As shown, the chip circuit layout device 90 can include an obtaining unit 901, a determining unit 902 and an operation unit 903.

[0183] The obtaining unit 901 is configured to obtain an initial layout result of a to-be-designed circuit, wherein the to-be-designed circuit includes at least two macro modules, and a layout halo is arranged around each macro module.

[0184] The determining unit 902 is configured to determine layout halo graphic coordinate information corresponding to the at least two macro modules.

[0185] The operation unit 903 is configured to perform coordinate operation on the layout halo graphic coordinate information corresponding to the at least two macro modules, combine the at least two macro modules into one or more polygons, obtain coordinate information of the one or more polygons, and calculate a coordinate difference value of each adjacent two points in the one or more polygons.

[0186] The determining unit 902 is further configured to determine whether there is a layout violation in the at least two macro modules based on the coordinate difference value of each adjacent two points in the one or more polygons.

[0187] In some embodiments, referring to Figure 9 The chip circuit layout device 90 can further include a repairing unit 904 configured to repair the layout violation according to a preset repair strategy when it is determined that there is a layout violation in the at least two macro modules.

[0188] In some embodiments, the obtaining unit 901 is further configured to obtain a layout repair result of the to-be-designed circuit.

[0189] The determining unit 902 is further configured to update the initial layout result based on the layout repair result, return to perform the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules, and continue until there is no layout violation in the at least two macro modules.

[0190] In some embodiments, the determining unit 902 is further configured to determine a target layout result of the to-be-designed circuit when there is no layout violation in the at least two macro modules.

[0191] In some embodiments, the determining unit 902 is further configured to compare the coordinate difference value of each two adjacent points with a first preset characteristic value, wherein the coordinate difference value includes a horizontal coordinate difference value and a vertical coordinate difference value; if the horizontal coordinate difference value of the two adjacent points is greater than 0 and less than the first preset characteristic value, or the vertical coordinate difference value of the two adjacent points is greater than 0 and less than the first preset characteristic value, it is determined that the at least two macro modules exist layout violations; and if the horizontal coordinate difference value of the two adjacent points is greater than or equal to the first preset characteristic value and the vertical coordinate difference value of the two adjacent points is greater than or equal to the first preset characteristic value, it is determined that the at least two macro modules do not exist layout violations.

[0192] In some embodiments, the determining unit 902 is further configured to perform coordinate expansion on the layout halo graphic coordinate information corresponding to the at least two macro modules to obtain a plurality of new graphic coordinate information; and perform an AND operation on the layout halo graphic coordinate information corresponding to the at least two macro modules and the plurality of new graphic coordinate information, and combine the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons.

[0193] In some embodiments, the coordinate information includes horizontal coordinate information and vertical coordinate information.

[0194] The calculating unit 903 is specifically configured to traverse the horizontal coordinate information of each point in the one or more polygons, perform difference calculation on the horizontal coordinate information of each two adjacent points to obtain a horizontal coordinate difference value of each two adjacent points in the one or more polygons; traverse the vertical coordinate information of each point in the one or more polygons, perform difference calculation on the vertical coordinate information of each two adjacent points to obtain a vertical coordinate difference value of each two adjacent points in the one or more polygons; and obtain a coordinate difference value of each two adjacent points in the one or more polygons according to the horizontal coordinate difference value and the vertical coordinate difference value of each two adjacent points in the one or more polygons.

[0195] In some embodiments, referring to Figure 9 The layout device 90 of the chip circuit can further include a setting unit 905 configured to set a preset list, wherein if the horizontal coordinate difference value of the two adjacent points is greater than 0 and less than a first preset characteristic value, or the vertical coordinate difference value of the two adjacent points is greater than 0 and less than a first preset characteristic value, the coordinate information of the two adjacent points and the corresponding horizontal coordinate difference value or vertical coordinate difference value are placed in the preset list.

[0196] In some embodiments, the determining unit 902 is further configured to determine whether the preset list is empty; if the preset list is not empty, determine that the at least two macro modules exist layout violations; and if the preset list is empty, determine that the at least two macro modules do not exist layout violations.

[0197] In some embodiments, the repairing unit 904 is specifically configured to, if there are two coordinate difference values of the same size in the preset list and the coordinate difference values are less than a second preset characteristic value, obtain coordinate information of four points corresponding to the two coordinate difference values of the same size from the preset list; and determine two macro modules contained by the four points according to the obtained coordinate information of the four points, and adjust the two macro modules to be position-aligned, so as to repair the layout violations.

[0198] In some embodiments, the repairing unit 904 is specifically configured to, if there are four points with the same horizontal coordinate information or the same vertical coordinate information in the preset list, determine two macro modules contained by the four points, and adjust the two macro modules to be position-aligned, so as to repair the layout violations.

[0199] In some embodiments, the repairing unit 904 is specifically configured to, if there are no four points with the same horizontal coordinate information or the same vertical coordinate information in the preset list, determine two macro modules contained by the four points, and add a layout block in a region corresponding to the layout violations, so as to repair the layout violations.

[0200] It can be understood that, in the present embodiment, the "unit" can be a part of circuit, a part of processor, a part of program or software, etc., and of course can be a module, and can also be non-modular. Moreover, each component in the present embodiment can be integrated in a processing unit, or each unit can exist physically independently, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function module.

[0201] The integrated unit, if implemented in the form of a software function module and not sold or used as an independent product, can be stored in a computer readable storage medium based on such understanding. The technical solutions of the embodiments essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in the embodiments. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0202] Therefore, the embodiments provide a computer storage medium storing a computer program, which, when executed by at least one processor, implements the steps of the method of any one of the preceding embodiments.

[0203] Based on the composition of the chip circuit layout device 90 and the computer storage medium, see Figure 10 , which shows a hardware structure schematic diagram of the chip circuit layout device 100 provided by the embodiments of the present application. As Figure 10 indicated, it can include a first communication interface 1001, a first memory 1002 and a first processor 1003; each component is coupled together through a first bus system 1004. It can be understood that the first bus system 1004 is used to realize the connection communication between the components. The first bus system 1004 includes not only a data bus, but also a power bus, a control bus and a state signal bus. However, in order to clearly illustrate, all kinds of buses are marked as the first bus system 1004 in Figure 10 . Among them,

[0204] The first communication interface 1001 is used for receiving and sending signals in the process of transceiving information with other external network elements;

[0205] The first memory 1002 is used for storing a computer program capable of running on the first processor 1003;

[0206] The first processor 1003 is used for executing the following when running the computer program:

[0207] Obtaining an initial layout result of a to-be-designed circuit, wherein the to-be-designed circuit includes at least two macro modules, and a layout halo is arranged around the macro modules;

[0208] determine layout halo pattern coordinate information corresponding to the at least two macro modules;

[0209] perform coordinate operation on the layout halo pattern coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons;

[0210] calculate a coordinate difference value of each adjacent two points in the one or more polygons; and

[0211] determine, based on the coordinate difference value of each adjacent two points in the one or more polygons, whether there is a layout violation in the at least two macro modules.

[0212] It can be understood that the first memory 1002 in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically erasable programmable read-only memory (Electrically EPROM, EEPROM) or a flash memory. The volatile memory can be a random access memory (Random Access Memory, RAM) used as an external cache. By way of example, but not by way of limitation, many forms of RAM are available, such as static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synchlink DRAM, SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DRRAM). The first memory 1002 of the system and method described in the present application is intended to include but not limited to these and any other suitable types of memory.

[0213] The first processor 1003 can be an integrated circuit chip having a processing capability of signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware or the instruction in the form of software in the first processor 1003. The first processor 1003 described above can be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. Each method, step and logic block disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiment of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the first storage 1002, and the first processor 1003 reads the information in the first storage 1002, and combines the hardware to complete the steps of the above method.

[0214] It can be understood that the embodiments described in the present application can be realized by hardware, software, firmware, middleware, microcode or a combination thereof. For hardware implementation, the processing unit can be realized in one or more application specific integrated circuits (Application Specific Integrated Circuits, ASIC), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP Device, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general processors, controllers, microcontrollers, microprocessors, other electronic units for executing functions described in the present application or a combination thereof. For software implementation, the technology described in the present application can be realized by modules (such as processes, functions, etc.) for executing functions described in the present application. The software code can be stored in the memory and executed by the processor. The memory can be implemented in the processor or outside the processor.

[0215] Optionally, as another embodiment, the first processor 1003 is further configured to execute the method of any one of the preceding embodiments when running the computer program.

[0216] The embodiment provides a layout device of a chip circuit, which can be applied to a layout device of the chip circuit. The device can include an acquisition unit, a determination unit and an operation unit. In this way, the coordinate difference of each two adjacent points is used to determine whether at least two macro modules exist layout violations, and the layout violations are repaired according to a preset repair strategy, so that the number of layout iterations caused by DRC due to macro module placement can be reduced, the workload of macro module placement in chip design can be saved, and the time of the entire chip design can be saved. In addition, when repairing the layout violations, the area waste caused by simultaneously increasing the layout blockage on both sides of the macro module can be avoided.

[0217] In still another embodiment of the present application, based on the same inventive concept as the preceding embodiments, refer to Figure 11 which shows a component structure schematic diagram of a circuit design device 110 provided by an embodiment of the present application. As Figure 11 shown, the circuit design device 110 can include a receiving unit 1101, a layout unit 1102 and a wiring unit 1103; wherein

[0218] The receiving unit 1101 is configured to receive at least two macro modules of a circuit to be designed, and a layout halo is arranged around the macro module;

[0219] The layout unit 1102 is configured to generate an initial layout result of the circuit to be designed; and determine layout halo graphic coordinate information corresponding to the at least two macro modules; when it is determined that the at least two macro modules exist layout violations, according to the determined layout halo graphic coordinate information, the layout violations are repaired according to a preset repair strategy, and the initial layout result is updated based on the obtained layout repair result, the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules is executed until the at least two macro modules do not exist layout violations, to determine a target layout result of the circuit to be designed;

[0220] The wiring unit 1103 is configured to perform a wiring operation on the circuit to be designed according to the target layout result, to obtain a wiring result of the circuit to be designed.

[0221] In some embodiments, the layout unit 1102 is specifically configured to perform coordinate operation on layout halo graph coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain coordinate information of the one or more polygons; traverse coordinate information of each point in the one or more polygons, determine coordinate difference values of each adjacent two points in the one or more polygons; and based on the coordinate difference values of each adjacent two points in the one or more polygons, when it is determined that there is a layout violation in the at least two macro modules, repair the layout violation according to a preset repair strategy.

[0222] In some embodiments, referring to Figure 11 , the circuit design device 110 can further include a timing analysis unit 1104 configured to perform timing analysis on the wiring result and output a timing analysis report of the circuit to be designed.

[0223] It can be understood that in the present embodiment, the "unit" can be a partial circuit, a partial processor, a partial program or software, etc., and of course can also be a module, and can also be non-modular. Moreover, the components in the present embodiment can be integrated in one processing unit, or can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function module.

[0224] The integrated unit, if realized in the form of a software function module and not sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present embodiment provides a computer storage medium storing a computer program, which is executed by a second processor to implement the method of any one of the preceding embodiments.

[0225] Based on the components of the circuit design device 110 and the computer storage medium, referring to Figure 12 , a hardware structure schematic diagram of an EDA device 120 provided by the present embodiment is shown. As Figure 12 indicated, it can include a second communication interface 1201, a second memory 1202 and a second processor 1203; each component is coupled together through a second bus system 1204. It can be understood that the second bus system 1204 is used to realize the connection communication between the components. The second bus system 1204 includes a data bus, a power bus, a control bus and a state signal bus. However, for the purpose of clear illustration, all kinds of buses are marked as the second bus system 1204 in Figure 12 . Among them,

[0226] The second communication interface 1201 is configured to receive and send signals in the process of transmitting and receiving information with other external network elements.

[0227] The second memory 1202 is configured to store a computer program capable of running on the second processor 1203.

[0228] The second processor 1203 is configured to perform the following when running the computer program:

[0229] At least two macro modules of a circuit to be designed are received, and a layout halo is arranged around the macro modules;

[0230] An initial layout result of the circuit to be designed is generated;

[0231] Layout halo graphic coordinate information corresponding to the at least two macro modules is determined;

[0232] According to the determined layout halo graphic coordinate information, when it is determined that there is a layout violation in the at least two macro modules, the layout violation is repaired according to a preset repair strategy, and the initial layout result is updated based on the obtained layout repair result, and the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules is returned to be executed until there is no layout violation in the at least two macro modules, so as to determine a target layout result of the circuit to be designed;

[0233] Based on the target layout result, a wiring operation is performed on the circuit to be designed to obtain a wiring result of the circuit to be designed.

[0234] Optionally, as another embodiment, the second processor 1203 is further configured to perform the method of any one of the preceding embodiments when running the computer program.

[0235] It can be understood that the hardware functions of the second memory 1202 and the first memory 1002 are similar, and the hardware functions of the second processor 1203 and the first processor 1003 are similar; hereinafter, the details are not described.

[0236] The embodiment provides a circuit design device, which is applied to an EDA device. The device can include a receiving unit, a layout unit and a wiring unit. In this way, not only the circuit design can be realized, but also the layout violation repair function is provided, the multiple layout iterations caused by the macro module placement due to the DRC can be reduced, the workload of the macro module placement in the back-end design can be saved, the timing deterioration caused by the manual solution of the problem in the project later stage can be avoided, and the area waste caused by the left and right macro modules simultaneously adding the block can be avoided.

[0237] It should be noted that, in the present application, the terms "comprising", "including", or any other variant thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed, or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0238] The above-mentioned sequence numbers of embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0239] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0240] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0241] The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0242] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A layout method for a chip circuit, characterized in that, The method includes: Obtain the initial layout result of the circuit to be designed, wherein the circuit to be designed includes at least two macro modules, and layout halos are provided around the macro modules; Determine the layout halo graphic coordinate information corresponding to the at least two macro modules; Perform coordinate calculations on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons; Calculate the coordinate difference between every two adjacent points in the one or more polygons; and Based on the coordinate difference between every two adjacent points in the one or more polygons, determine whether the at least two macro modules have layout violations; The step of determining whether the at least two macro modules have layout violations based on the coordinate difference between every two adjacent points in the one or more polygons includes: The coordinate difference between each pair of adjacent points is compared with a first preset feature value, wherein the coordinate difference includes a horizontal coordinate difference and a vertical coordinate difference; If the difference in the horizontal coordinates of two adjacent points is greater than 0 and less than the first preset feature value, or the difference in the vertical coordinates of two adjacent points is greater than 0 and less than the first preset feature value, then it is determined that at least two macro modules have layout violations; and If the difference in the horizontal coordinates of two adjacent points is greater than or equal to the first preset feature value and the difference in the vertical coordinates of two adjacent points is greater than or equal to the first preset feature value, then it is determined that neither of the at least two macro modules has a layout violation.

2. The method according to claim 1, characterized in that, The method further includes: When it is determined that at least two macro modules have layout violations, the layout violations are repaired according to a preset repair strategy.

3. The method according to claim 2, characterized in that, After repairing the layout violation according to the preset repair strategy, the method further includes: Obtain the layout repair results of the circuit to be designed; The initial layout result is updated based on the layout repair result, and the process returns to the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules until there are no layout violations in the at least two macro modules.

4. The method according to claim 3, characterized in that, The method further includes: When there are no layout violations in at least two macro modules, the target layout result of the circuit to be designed is determined.

5. The method according to claim 1, characterized in that, The step of performing coordinate calculations on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combining the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons, includes: The coordinates of the layout halo graphic coordinates corresponding to the at least two macro modules are extended to obtain multiple new graphic coordinate information; and Perform an AND operation on the layout halo graphic coordinate information corresponding to the at least two macro modules and the multiple new graphic coordinate information, and combine the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons.

6. The method according to claim 1, characterized in that, The coordinate information includes horizontal coordinate information and vertical coordinate information. Calculating the coordinate difference between every two adjacent points in the one or more polygons includes: The horizontal coordinate information of each point in the one or more polygons is traversed, and the difference between the horizontal coordinate information of each two adjacent points is calculated to obtain the difference between the horizontal coordinates of each two adjacent points in the one or more polygons. Iterate through the vertical coordinate information of each point in the one or more polygons, calculate the difference between the vertical coordinate information of each pair of adjacent points, and obtain the vertical coordinate difference between each pair of adjacent points in the one or more polygons; and The coordinate difference between each pair of adjacent points in the one or more polygons is obtained based on the difference in horizontal coordinates and the difference in vertical coordinates between each pair of adjacent points in the one or more polygons.

7. The method according to claim 1, characterized in that, After obtaining the coordinate difference between every two adjacent points in the one or more polygons, the method further includes: A preset list is set up, wherein if the difference in the horizontal coordinates of two adjacent points is greater than 0 and less than the first preset feature value, or the difference in the vertical coordinates of two adjacent points is greater than 0 and less than the first preset feature value, then the coordinate information of the two adjacent points and the corresponding difference in horizontal or vertical coordinates are placed in the preset list.

8. The method according to claim 7, characterized in that, Also includes: Determine whether the preset list is empty; If the preset list is not empty, then it is determined that at least two macro modules have layout violations; as well as If the preset list is empty, then it is determined that neither of the at least two macro modules has a layout violation.

9. The method according to claim 7, characterized in that, When it is determined that at least two macro modules have layout violations, the layout violations are repaired according to a preset repair strategy, including: If there are two coordinate differences of the same size in the preset list and the coordinate difference is less than the second preset feature value, then the coordinate information of the four points corresponding to the two coordinate differences of the same size is obtained from the preset list. Based on the coordinate information of the four points, the two macro modules contained in the four points are determined, and the two macro modules are adjusted to align their positions in order to repair the layout violation.

10. The method according to claim 7, characterized in that, When it is determined that at least two macro modules have layout violations, the layout violations are repaired according to a preset repair strategy, including: If four points in the preset list have the same horizontal coordinate information or the same vertical coordinate information, then the two macro modules contained in the four points are identified, and the two macro modules are adjusted to align their positions in order to repair the layout violation.

11. The method according to claim 7, characterized in that, When it is determined that at least two macro modules have layout violations, the layout violations are repaired according to a preset repair strategy, including: If there are no four points in the preset list with the same horizontal or vertical coordinate information, then the two macro modules contained in the four points are identified, and a layout block is added to the area corresponding to the layout violation to fix the layout violation.

12. A circuit design method based on electronic design automation (EDA) tools, characterized in that, The method includes: Receive at least two macro modules of the circuit to be designed, and the macro modules are surrounded by layout halos; Generate the initial layout result of the circuit to be designed; Determine the layout halo graphic coordinate information corresponding to the at least two macro modules; Based on the determined layout halo graphic coordinate information, when it is determined that at least two macro modules have layout violations, the layout violations are repaired according to a preset repair strategy, and the initial layout result is updated based on the obtained layout repair result. Then, the process returns to the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules until there are no layout violations in the at least two macro modules, so as to determine the target layout result of the circuit to be designed. Based on the target layout result, a routing operation is performed on the circuit to be designed to obtain the routing result of the circuit to be designed. Before determining that at least two macro modules have layout violations, the method further includes: Based on the determined layout halo graphic coordinate information, determine the coordinate difference between every two adjacent points in one or more polygons; wherein, the at least two macro modules are combined into one or more polygons; The coordinate difference between each pair of adjacent points is compared with a first preset feature value, wherein the coordinate difference includes a horizontal coordinate difference and a vertical coordinate difference; If the difference in the horizontal coordinates of two adjacent points is greater than 0 and less than the first preset feature value, or the difference in the vertical coordinates of two adjacent points is greater than 0 and less than the first preset feature value, then it is determined that at least two macro modules have layout violations; and If the difference in the horizontal coordinates of two adjacent points is greater than or equal to the first preset feature value and the difference in the vertical coordinates of two adjacent points is greater than or equal to the first preset feature value, then it is determined that neither of the at least two macro modules has a layout violation.

13. The method according to claim 12, characterized in that, The step of determining the coordinate difference between every two adjacent points in one or more polygons based on the determined layout halo graphic coordinate information includes: Perform coordinate calculations on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons; Iterate through the coordinate information of each point in the one or more polygons to determine the coordinate difference between every two adjacent points in the one or more polygons.

14. The method according to claim 12, characterized in that, After obtaining the wiring result of the circuit to be designed, the method further includes: Perform timing analysis on the wiring results and output a timing analysis report for the circuit to be designed.

15. A layout apparatus for a chip circuit, characterized in that, The chip circuit layout device includes an acquisition unit, a determination unit, and a calculation unit; wherein, The acquisition unit is configured to acquire the initial layout result of the circuit to be designed, wherein the circuit to be designed includes at least two macro modules, and the macro modules are surrounded by layout halos. The determining unit is configured to determine the layout halo graphic coordinate information corresponding to the at least two macro modules; The computing unit is configured to perform coordinate calculations on the layout halo graphic coordinate information corresponding to the at least two macro modules, and combine the at least two macro modules into one or more polygons to obtain the coordinate information of the one or more polygons; and to calculate the coordinate difference between every two adjacent points in the one or more polygons. The determining unit is further configured to determine whether the at least two macro modules have layout violations based on the coordinate difference between every two adjacent points in the one or more polygons; The determining unit is further configured to compare the coordinate difference between each pair of adjacent points with a first preset feature value, wherein the coordinate difference includes a horizontal coordinate difference and a vertical coordinate difference; if the horizontal coordinate difference between two adjacent points is greater than 0 and less than the first preset feature value, or the vertical coordinate difference between two adjacent points is greater than 0 and less than the first preset feature value, then it is determined that at least two macro modules have layout violations; and if the horizontal coordinate difference between two adjacent points is greater than or equal to the first preset feature value and the vertical coordinate difference between two adjacent points is greater than or equal to the first preset feature value, then it is determined that neither of the at least two macro modules has a layout violation.

16. A circuit design device, characterized in that, The circuit design device includes a receiving unit, a layout unit, and a wiring unit; wherein... The receiving unit is configured to receive at least two macro modules of the circuit to be designed, and the macro modules are surrounded by a layout halo. The layout unit is configured to generate an initial layout result for the circuit to be designed; and to determine the layout halo graphic coordinate information corresponding to the at least two macro modules; based on the determined layout halo graphic coordinate information, when it is determined that there is a layout violation in the at least two macro modules, the layout violation is repaired according to a preset repair strategy, and the initial layout result is updated based on the obtained layout repair result, and the process returns to the step of determining the layout halo graphic coordinate information corresponding to the at least two macro modules, until there are no layout violations in the at least two macro modules, so as to determine the target layout result of the circuit to be designed; The wiring unit is configured to perform wiring operations on the circuit to be designed according to the target layout result, so as to obtain the wiring result of the circuit to be designed. The layout unit is further configured to determine the coordinate difference between every two adjacent points in one or more polygons based on the determined layout halo graphic coordinate information; wherein the at least two macro modules are combined into one or more polygons; compare the coordinate difference between every two adjacent points with a first preset feature value, wherein the coordinate difference includes a horizontal coordinate difference and a vertical coordinate difference; if the horizontal coordinate difference between two adjacent points is greater than 0 and less than the first preset feature value, or the vertical coordinate difference between two adjacent points is greater than 0 and less than the first preset feature value, then it is determined that the at least two macro modules have a layout violation; and if the horizontal coordinate difference between two adjacent points is greater than or equal to the first preset feature value and the vertical coordinate difference between two adjacent points is greater than or equal to the first preset feature value, then it is determined that neither of the at least two macro modules has a layout violation.

17. A chip circuit layout device, characterized in that, The chip circuit layout device includes a memory and a processor; wherein, The memory is used to store executable instructions that can run on the processor; The processor is configured to execute the method as described in any one of claims 1 to 11 when running the executable instructions.

18. An EDA device, characterized in that, The EDA device includes a memory and a processor; wherein... The memory is used to store executable instructions that can run on the processor; The processor is configured to execute the method as described in any one of claims 12 to 14 when running the executable instructions.

19. A computer storage medium, characterized in that, The computer storage medium stores a computer program that, when executed by a chip circuit layout device, implements the method as described in any one of claims 1 to 11, or when executed by an EDA device, implements the method as described in any one of claims 12 to 14.

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