A vertical MOSFET device, its manufacturing method, and applications

Abstract

The present invention relates to a vertical MOSFET device, a manufacturing method thereof, and an application. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer, and a second silicon layer that are vertically stacked from bottom to top on a substrate; wherein, the molar content of germanium in the first germanium-silicon layer and the third germanium-silicon layer is greater than that in the second germanium-silicon layer; etching to form a nano-stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner sidewalls of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming source and drain electrodes; forming an active region having a shallow trench isolation layer; removing the dummy gate to form a gate dielectric layer and a gate electrode. The present invention can well control the channel size, the inner sidewall size of the extension region, the gate size, etc., and is applicable to both nano-sheet or nano-wire structures.

Description

Technical Field

[0001] The present invention relates to the field of transistors, and particularly to a vertical MOSFET device, a manufacturing method thereof, and an application thereof. Background Art

[0002] For MOSFETs, since their integration level is an important factor determining the product price, there is a particular expectation to improve the integration level. For two-dimensional or planar semiconductor devices, since their integration level is mainly determined by the area of the projection occupied by a unit memory cell on the silicon wafer surface, the integration level is greatly affected by the level of fine pattern formation technology. However, extremely expensive process equipment for improving pattern fineness sets practical limitations on improving the integration level of two-dimensional or planar semiconductor devices. To overcome this limitation, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have been proposed. 3D integration is a breakthrough in the scaling of logic devices, memory devices such as DRAM, etc. However, due to the process fluctuations during etching processes such as lithography and reactive ion etching, and the complexity of process integration, problems such as difficulty in controlling dimensions such as the thickness of the inner sidewall exist in vertical nanosheet or nanowire MOSFETs.

[0003] Currently, there is still a large gap in the performance of vertical transistor devices compared to mature planar transistors and FinFETs. This is because there are many challenges in the key process modules and process integration of vertical transistors. The key process modules of vertical transistors include etching and selective etching, forming nanowire and nanosheet channels, and inner sidewalls. For this reason, the present invention is proposed. Summary of the Invention

[0004] The main object of the present invention is to provide a manufacturing method of a vertical MOSFET device, which can well control the channel dimensions, the inner sidewall dimensions of the extension region, the gate dimensions, etc., and is applicable to both nanosheet or nanowire structures.

[0005] Another object of the present invention is to provide a vertical MOSFET device, which increases the inner sidewall of the extension region with controllable dimensions and has better electrical performance compared to existing vertical transistor devices, such as low leakage current and small parasitic capacitance.

[0006] To achieve the above objects, the present invention provides the following technical solutions.

[0007] The first aspect of the present invention provides a manufacturing method of a vertical MOSFET device, including the following steps:

[0008] Provide a substrate;

[0009] A first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer, and a second silicon layer are vertically stacked from bottom to top on the substrate; wherein, the molar content of germanium in the first germanium-silicon layer and the third germanium-silicon layer is greater than that in the second germanium-silicon layer;

[0010] The first silicon layer, the first germanium-silicon layer, the second germanium-silicon layer, the third germanium-silicon layer, and the second silicon layer are etched to form a nano-stack structure;

[0011] The first germanium-silicon layer and the third germanium-silicon layer in the nano-stack structure are selectively etched, so as to form a first groove and a third groove at the side walls of the first germanium-silicon layer and the third germanium-silicon layer respectively;

[0012] Inner sidewalls of the extended regions are formed in the first groove and the third groove;

[0013] The second germanium-silicon layer is selectively etched to form a gate groove at the side wall of the second germanium-silicon layer;

[0014] A dummy gate is formed in the gate groove;

[0015] The first silicon layer and the second silicon layer are respectively doped to form source / drain electrodes;

[0016] After the source / drain electrodes are formed, the substrate is etched and a dielectric material is deposited to form an active region having a shallow trench isolation layer;

[0017] The dummy gate in the active region is removed, and then a gate dielectric layer and a gate are sequentially formed in the gate groove;

[0018] Subsequent processes are carried out.

[0019] The second aspect of the present invention provides a vertical MOSFET device, which includes a substrate, and source / drain electrodes, a first extended region, a channel, a second extended region, and source / drain electrodes stacked from bottom to top on the substrate; the two sides of the channel are gates, and the gates are isolated from the channel by a gate dielectric; the two sides of the first extended region are first inner sidewalls, the two sides of the second extended region are second inner sidewalls, and the gates are located between the first inner sidewalls and the second inner sidewalls;

[0020] Wherein, the first extended region, the channel, and the second extended region are all made of germanium-silicon materials, and the molar content of germanium in the first extended region and the second extended region is greater than that in the channel; the source / drain electrodes are doped silicon.

[0021] The third aspect of the present invention provides the above-mentioned vertical MOSFET device, or an application of the vertical MOSFET device prepared by the above-mentioned manufacturing method in an electronic device.

[0022] Compared with the prior art, the present invention achieves the following technical effects: An inner sidewall is added between the gate and the source-drain electrodes, and by designing a specific process sequence (for example, designing a germanium-silicon epitaxial stack, a replacement mask, and an inner sidewall protection layer structure with different germanium compositions and different etching selectivities, the integrated development of the inner sidewall process for vertical transistors is realized), the size of the inner sidewall can be controlled, and the controllability of the gate size and the channel size is also achieved synchronously, thereby reducing the leakage problem of the device, reducing the parasitic capacitance, and reducing the defective phenomena in device processing; The vertical MOSFET device fabricated by the method of the present invention can be used in various memory devices such as SRAM, DRAM, and Flash. Brief Description of the Drawings

[0023] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention.

[0024] Figures 1 to 25 Structural diagrams obtained in each step of the manufacturing method of the vertical MOSFET device provided by the present invention;

[0025] Figure 26 Cross-sectional structural schematic diagram of the vertical MOSFET device provided by the present invention. Detailed Description of the Embodiments

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0027] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in actuality due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0028] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element.

[0029] As introduced in the background art, in the prior art, for vertically stacked nanowire / sheet transistors, due to the uncontrollability of structural dimensions such as the sidewall dimensions and gate dimensions in the extension region, there are differences in the structural dimensions of each component in the transistor, which further limits the practical application of vertically stacked nanowire / sheet transistors. The present invention conducts research on the above problems and proposes a manufacturing method for a vertical MOSFET device. This method adds an inner sidewall between the gate and the source / drain electrodes, and realizes the controllability of the size of the inner sidewall by designing a specific process sequence. At the same time, the controllability of the gate size and the channel size is also achieved, thereby reducing the leakage problem of the device, reducing the parasitic capacitance, and reducing the defective phenomena in device processing. The manufacturing method provided by the present invention includes the following steps.

[0030] First, in step S1, a first silicon layer 2, a first germanium-silicon layer 3, a second germanium-silicon layer 4, a third germanium-silicon layer 5, and a second silicon layer 6 are vertically stacked on the substrate 1 from bottom to top, obtaining a structure as Figure 1 shown.

[0031] Among them, the molar content of germanium in the first germanium-silicon layer 3 and the third germanium-silicon layer 5 is greater than that in the second germanium-silicon layer 4. By the difference in germanium content, selective etching of the three germanium-silicon layers can be achieved. In addition, since the first germanium-silicon layer 3 and the third germanium-silicon layer 5 need to be etched synchronously in subsequent processes, it is preferred that the first germanium-silicon layer 3 and the third germanium-silicon layer 5 use materials with the same germanium content. For example, the molar content of germanium in the first germanium-silicon layer 3 and the third germanium-silicon layer 5 is preferably more than 15% (15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, etc., and more preferably 15% - 30%). Correspondingly, the molar content of germanium in the second germanium-silicon layer 4 is preferably less than 15% (for example, 1%, 3%, 5%, 7%, 10%, 13%, 15%, etc., and more preferably 5% - 15%).

[0032] The above-mentioned substrate 1 can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, germanium-silicon, gallium arsenide, or germanium-on-insulator, etc. The corresponding top semiconductor material is silicon, germanium, germanium-silicon, or gallium arsenide, etc. At the same time, the doping type of the semiconductor layer on the substrate is determined according to the device type to form a P-well (for nMOSFET) or an n-well (for pMOSFET). As Figure 1 shown by the dashed box in the cross-sectional view of the substrate where the doping region ( Figures 1 to 25 the dividing line between the doped region 1a and the non-doped region is marked in the cross-sectional view of the substrate).

[0033] The first silicon layer 2 and the second silicon layer 6 can be used as the source / drain electrodes of the transistor through subsequent etching and doping, or can be in-situ doped during the epitaxial growth of the first silicon layer 2 and the second silicon layer 6 to form a highly doped n-type or p-type conductive layer (the doping concentration is 1×10 19 ~1×10 21 cm -3 ). Therefore, parameters such as its thickness, doping concentration, and doping type are determined according to the product design.

[0034] The first germanium-silicon layer 3 and the second germanium-silicon layer 5 are formed by epitaxial growth. The first germanium-silicon layer 3 and the second germanium-silicon layer 5 can be undoped, or can be in-situ doped during epitaxial growth, and the doping concentration is 1×10 18 ~1×10 20 cm -3 . The doping concentration of the first germanium-silicon layer 3 and the second germanium-silicon layer 5 should be lower than that of the first silicon layer 2 and the second silicon layer 6 to suppress the hot carrier injection effect.

[0035] The second germanium-silicon layer 4 will be used as the channel after subsequent etching. Therefore, its thickness is preferably greater than that of the first germanium-silicon layer 3 and the third germanium-silicon layer 5. For example, in some typical electronic devices, the thicknesses of the first germanium-silicon layer 3 and the third germanium-silicon layer 5 are each independently 5 - 15 nm, and the thickness of the second germanium-silicon layer 4 is 15 - 100 nm.

[0036] According to the material types of the above three germanium-silicon layers and two silicon layers, an appropriate formation process is selected, usually including but not limited to epitaxial growth methods such as reduced pressure chemical vapor deposition (RPCVD) and metalorganic chemical vapor deposition (MOCVD).

[0037] Continue with step S2 to etch the first silicon layer 2, the first germanium-silicon layer 3, the second germanium-silicon layer 4, the third germanium-silicon layer 5, and the second silicon layer 6 to form a nano-stack structure.

[0038] Since the second silicon layer 6 is to be used as the source / drain electrode of the transistor, it needs to be fully protected during etching, and at the same time, the pattern needs to be regularized. Therefore, etching needs to be carried out with the aid of a mask, that is, a mask is deposited on the second silicon layer 6 in advance and then etched. For example, the following method is adopted.

[0039] Step S201, deposit a mask stack 7 on the second silicon layer 6. The mask stack 7 preferably uses a hard mask (HM), such as TiN, SiN, SiO2, amorphous silicon, polysilicon, etc. It is preferably stacked in multiple layers, which can adapt to different selectivities in different etching processes. At the same time, it includes an etch stop layer, etc., playing a better protection role. For example, common silicon nitride - silicon - silicon nitride or silicon oxide - silicon - silicon oxide stacks. In the present invention, a mask formed by stacking a silicon oxide layer 701, an amorphous silicon layer 702 (or replaced with other dummy mask layers, taking amorphous silicon as an example below), and a silicon oxide layer 703 from bottom to top is preferred (as Figure 2 shown).

[0040] Step S202, pattern the mask stack 7: First, etch the top silicon oxide layer 703 and the amorphous silicon layer 702 in the mask stack by combining photolithography and etching processes to form a pattern mandrel, obtaining a structure as Figure 3 shown; then remove the photoresist 8.

[0041] Step S203, etch the silicon oxide layer 701.

[0042] Step S204, etch the second silicon layer 6, the third germanium - silicon layer 5, the second germanium - silicon layer 4, the first germanium - silicon layer 3, and the first silicon layer 2 to form a nano - stack structure as Figure 4 shown. Determine the shape of the nano - stack structure according to the nanowire or nanosheet. For example, Figure 5 and 6 respectively represent the top - view structures of the nanowire and the nanosheet (the arrows in Figure 5 and 6 indicate the cross - section direction of Figure 4 ). All subsequent steps are described taking the nanowire as an example (but this does not limit the application scope of the present invention).

[0043] The etching in the above - mentioned step S2 can be selected in ways such as dry etching (reactive ion etching RIE, plasma etching, high - pressure plasma etching, high - density plasma etching), wet etching (selecting an appropriate solvent or solution), etc. It can also be combined with a polishing (CMP) step before etching. Usually, the preferred etching means is selected according to the material type. The present invention does not make special restrictions on this.

[0044] Next, perform step S3, selectively etch the first germanium - silicon layer 3 and the third germanium - silicon layer 5 in the nano - stack structure, so as to form a first groove 3a and a third groove 5a at the side walls of the first germanium - silicon layer 3 and the third germanium - silicon layer 5 respectively, obtaining a structure as Figure 7 shown.

[0045] The methods for etching the first germanium-silicon layer 3 and the third germanium-silicon layer 5 in step S3 include but are not limited to dry continuous etching, dry atomic layer etching (ALE), wet continuous etching, wet ALE, etc. The etching amount can be controlled by adjusting various etching parameters, including the difference in germanium in the three germanium-silicon layers, the etching dose, the etching power, the etching gas flow rate, the pressure in the etching chamber, and the duration. The preferred etching method is ALE. At the same time, in addition to considering the selectivity for the second germanium-silicon layer, the selectivity of the etching method and conditions for the first silicon layer and the second silicon layer also needs to be considered. Since the germanium-silicon layer and the silicon layer selected in the present invention have a large difference in etching selectivity, the sizes of the first groove and the third groove can be better controlled, and then the size of the inner sidewall filled subsequently can be controlled. For a typical MOSFET device, the etching amount in this step is preferably controlled at 5 nm - 25 nm, that is, the depths of the first groove and the third groove reach 5 nm - 25 nm.

[0046] Proceed to step S4 to form an inner sidewall of the extended region in the first groove and the third groove. The inner sidewall of the extended region is preferably made of a material with good dielectric properties and a simple deposition process, such as typical silicon oxide.

[0047] Since the structural morphology obtained after step S3 is irregular, when forming the inner sidewall of the gate extended region in step S4, a process of over-deposition and etch-back is required. Specifically, the following steps can be adopted.

[0048] Step S401, deposit the material 9 of the inner sidewall of the extended region (taking silicon oxide as an example below) until all outer surfaces are covered. The deposition methods include but are not limited to PECVD, LPCVD, ALD and other methods, and the obtained structure is as Figure 8 shown.

[0049] Step S402, then chemically mechanically polish or selectively etch the silicon oxide until the pseudo-mask amorphous silicon layer 702 in the mask stack is exposed. In this step, if the material of the inner sidewall of the extended region is not silicon oxide, it needs to be carried out step by step.

[0050] Step S403, then anisotropically etch until the material of the inner sidewall of the extended region only fills the first groove and the third groove.

[0051] Among them, in order to avoid damage to the second silicon layer during the etching in step S403, it is preferable to replace the silicon layer in the mask with a material having a large difference in etching selectivity from the material of the inner sidewall of the extended region. The "large difference" here is compared with the etching selectivity between the material of the inner sidewall of the extended region and silicon. Taking silicon oxide as the material of the inner sidewall of the extended region as an example, it is preferable to replace the silicon in the mask with silicon nitride. To achieve the above purpose, the following steps can be added between step S402 and step S403 (for convenience of description, silicon oxide inner sidewall of the extended region is taken as an example here):

[0052] Step S402a, on the basis of Figure 8 fill the inner sidewall material of the extended area, such as silicon dioxide, over a large area.

[0053] Step S402b, remove the silicon layer in the mask to form a mask groove 704. In this step, the inner sidewall material of the extended area, such as silicon dioxide, can be first CMPed until the pseudo-mask amorphous silicon layer in the mask is exposed, obtaining Figure 9 the structure shown; then use wet etching means such as TMAH to etch away the pseudo-mask amorphous silicon layer to form a mask groove 704, obtaining Figure 10 the structure shown.

[0054] Step S402c, fill the mask groove 704 with a material having a large etching selectivity difference from the inner sidewall material of the extended area, such as silicon nitride, obtaining Figure 11 the structure shown. Similarly, in this step, when depositing silicon nitride, it is also necessary to deposit over a large area and then remove the silicon nitride outside the mask groove by CMP so that only the mask groove is filled with silicon nitride, which is the replacement mask 705.

[0055] Then perform step S403, form the morphology shown in Figure 12 by anisotropic etching to obtain the inner sidewall 9a of the extended area. In addition, the replacement mask 705 can also be removed after step S403 is completed to obtain Figure 13 the structure shown, and there is still the top silicon dioxide etch stop layer 701 remaining. In the actual process, the replacement mask 705 can be removed in subsequent processes, and the present invention does not make special restrictions on this.

[0056] Continue with step S5, selectively etch the second germanium silicon layer 4 to form a gate groove 4a at the sidewall of the second germanium silicon layer 4, such as Figure 14 the structure shown.

[0057] This step of etching preferably uses atomic layer etching (ALE). Since this layer of the present invention uses germanium silicon material, which has a large etching selectivity difference from silicon, it can better control the channel size and the size of the subsequent two side gates, etc., improving the device yield. The etching amount of this step is determined according to the channel size.

[0058] Continue with step S6, form a dummy gate in the gate groove. The purpose of pre-forming the dummy gate is on the one hand to dope to form source and drain electrodes, and on the other hand to form shallow trench isolation. Since the protection and conformal shape of the inner sidewall of the extended area need to be considered, comprehensive consideration should be given when selecting the dummy material. The present invention preferably uses a nitride, such as common silicon nitride. Similarly, in this step, due to the shape limitation of the dummy gate, it needs to be completed step by step, such as the following method.

[0059] Step S601, depositing a dummy gate material 10 until all outer surfaces are covered, preferably using an isotropic deposition method, such as Figure 15 The structure shown.

[0060] Step S602, etching is then performed until only the gate groove is filled with the dummy gate material 10 to form a dummy gate 10a, preferably using an anisotropic etching method to obtain the following Figure 16 The structure shown.

[0061] Step S603, remove the mask. If the replacement mask has been removed before, this step only requires removing the silicon oxide layer 701 (etching stop layer) to obtain the following: Figure 17 The structure shown.

[0062] Continuing with step S7, the first silicon layer 2 and the second silicon layer 6 are doped to form source / drain electrodes 2a and 6a. For example, elements such as boron, phosphorus or arsenic are injected, and the type depends on the device type. When doping the first silicon layer 2, the substrate surface layer is doped, and it is possible that only the edge regions 1b on both sides of the first silicon layer are doped. Figure 18 In actual applications, the doping method and injection angle are controlled according to device requirements.

[0063] Continuing to step S8, after forming the dummy gate, the substrate is etched and a dielectric material is deposited to form an active region with a shallow trench isolation layer.

[0064] When forming the active area, the side walls of the extension area need to be conformal, thereby ensuring the etching selectivity of the isolation material and each layer in the nano-stack structure. Therefore, a protective layer needs to be formed on the side walls of the nano-stack structure before proceeding. Specifically, the following steps can be used.

[0065] Step S801, forming a sidewall protection layer 11 on the sidewall of the nano stack structure, Figure 19 The structure shown. The protective layer can be made of a dielectric material such as silicon nitride. On the one hand, it protects the stacked structure (especially the inner sidewalls). On the other hand, its bottom can be retained as an isolation layer for the source and drain to reduce leakage current and parasitic capacitance. The thickness of the protective layer 11 can be selected to be 5 to 10 nm. Using a common deposition process, the protective layer is also formed in two steps: first, large-area deposition, followed by anisotropic etching.

[0066] Step S802: the substrate is then etched to form an active area.

[0067] Step S803 : depositing dielectric materials such as silicon oxide until all outer surfaces are covered.

[0068] Step S804, etching back until the surface height of the dielectric material is flush with the upper surface height of the first silicon germanium layer to form a shallow trench isolation layer 12. Figure 20 The structure shown.

[0069] Proceed to step S9 to remove the dummy gate 10a in the active region, obtaining the structure as shown in Figure 21 the figure.

[0070] If there is a protective layer in step S801, the protective layer needs to be removed first. To simplify the process, the protective layer is preferably made of the same material as the dummy gate, such as silicon nitride. In this way, the protective layer and the dummy gate 10a can be removed isotropically by means of thermal H3PO4 solution or RIE. During the removal process, the etching amount and etching conditions need to be controlled to ensure that a part of the sidewall protective layer material 11a (as shown in the structure of Figure 21 the figure) remains between the shallow trench isolation (STI) and the first silicon layer (source / drain electrodes have been formed through the previous process). This remaining part can separate the STI from the source / drain electrodes to reduce the leakage problem and at the same time reduce the parasitic capacitance.

[0071] Proceed to step S10 to form a replacement gate stack layer, including a gate dielectric layer 13 and a gate electrode 14, obtaining the structure as shown in Figure 22 the figure.

[0072] At this step, the gate dielectric layer can be made of a high-k dielectric material, including but not limited to HfO2, HfSiO x , HfAlO x , HfZrO x and so on. A thinner oxide layer (0.3 - 1.5 nm) can be deposited as a barrier layer before depositing the gate dielectric. A gate electrode material is deposited outside the gate layer. The gate electrode material includes but not limited to titanium, tungsten, titanium nitride, etc., and can be a single layer or a multi-layer stack. When depositing the gate dielectric and the gate electrode, large-area deposition is carried out. Therefore, back-etching and / or polishing are required for a preset thickness and height. Among them, the height of the gate electrode is preferably lower than the height of the upper source / drain electrodes, and more preferably lower than the height of the upper inner sidewall to reduce the parasitic capacitance.

[0073] Proceed to step S11 to pattern the gate electrode 14 with a photoresist to form a patterned gate electrode 14a and a gate dielectric 13a, leaving a landing pad 14b for leading out contact holes, and removing the photoresist, obtaining the structure as shown in Figure 23 the figure.

[0074] Finally, deposit silicon oxide over a large area and introduce source / drain contact holes and gate contact holes respectively (including source / drain contact holes 16, 17, and gate contact hole 15) to achieve metal interconnection, etc., obtaining the structure as shown in Figure 24 the figure, Figure 25 which is Figure 24 the top view morphology of.

[0075] The vertical MOSFET device manufactured by using the method of the present invention has a structure approximately as follows:

[0076] As shown Figure 26 in the figure, it includes a substrate 21, and a source / drain 22, a first extended region 23, a channel 28, a second extended region 25, and a source / drain 26 that are stacked from bottom to top on the substrate 21; both sides of the channel 28 are gates, and the gates are isolated from the channel 28 by a gate dielectric; both sides of the first extended region 23 are first inner sidewalls 20, both sides of the second extended region 25 are second inner sidewalls 27, and the gate 29 is located between the first inner sidewall 10 and the second inner sidewall 27.

[0077] Among them, the first extended region 23, the channel, and the second extended region 25 are all made of SiGe materials, and the molar content of Ge in the first extended region 23 and the second extended region 25 is greater than that in the channel; the source / drains 22 and 26 are doped silicon.

[0078] The first extended region 23 and the second extended region 25 are the remaining parts after etching the first GeSi layer and the third GeSi layer by the above method, and are sandwiched by the inner sidewalls. These two extended regions can be used as extensions of the channel.

[0079] In the MOSFET device prepared by the above process, the sidewalls of the source / drain, the sidewalls of the first inner sidewall 20, and the sidewalls of the second inner sidewall 27 are connected to form a groove profile, and the gate 29 is located in the groove. The width of the first inner sidewall of the first extended region 23 parallel to the nanowire channel direction is preferably 5 - 15 nm, and the depth of the groove perpendicular to the nanowire channel direction is preferably 5 - 25 nm.

[0080] At the same time, the materials of each layer in this MOSFET device can be selected from a variety of types suitable as described in the above process.

[0081] Although the present invention provides a MOSFET device with the above structure, this does not mean that the vertical MOSFET device provided by the present invention can only be made by the above process, and it can also be obtained by other feasible methods.

[0082] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A manufacturing method of a vertical MOSFET device, characterized in that, It includes the following steps: Provide a substrate; Form a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer, and a second silicon layer that are vertically stacked from bottom to top on the substrate; wherein, the molar content of germanium in the first germanium-silicon layer and the third germanium-silicon layer is greater than the content of germanium in the second germanium-silicon layer; Etch the first silicon layer, the first germanium-silicon layer, the second germanium-silicon layer, the third germanium-silicon layer, and the second silicon layer to form a nano-stack structure; Selectively etch the first germanium-silicon layer and the third germanium-silicon layer in the nano-stack structure, so as to form a first groove and a third groove at the sidewalls of the first germanium-silicon layer and the third germanium-silicon layer respectively; Form inner sidewalls of the extended region in the first groove and the third groove; form a sidewall protection layer for the inner sidewalls of the extended region on the sidewalls of the nano-stack structure; Selectively etch the second germanium-silicon layer to form a gate groove at the sidewall of the second germanium-silicon layer; Form a dummy gate in the gate groove; Dope the first silicon layer and the second silicon layer respectively to form source / drain electrodes; Etch the substrate and deposit a dielectric material to form an active region with a shallow trench isolation layer; Remove the dummy gate in the active region, specifically including etching the sidewall protection layer until a remaining part of the sidewall protection layer material is left between the shallow trench isolation layer and the first silicon layer; Then form a replacement gate of the gate stack layer in the gate groove, wherein the replacement gate includes a gate dielectric layer and a gate electrode in a stacked order; Perform subsequent processes.

2. The manufacturing method according to claim 1, characterized in that, The molar content of germanium in the first germanium-silicon layer and the third germanium-silicon layer is the same and is above 15%.

3. The manufacturing method according to claim 1, characterized in that, The molar content of germanium in the first germanium-silicon layer and the third germanium-silicon layer is 15% - 30%, and / or the molar content of germanium in the second germanium-silicon layer is 5% - 15%.

4. The manufacturing method according to claim 1, characterized in that, The thicknesses of the first germanium-silicon layer and the third germanium-silicon layer are less than the thickness of the second germanium-silicon layer.

5. The manufacturing method according to claim 4, characterized in that, The thicknesses of the first germanium-silicon layer and the third germanium-silicon layer are each independently 5 - 15 nm, and the thickness of the second germanium-silicon layer is 15 - 100 nm.

6. The manufacturing method according to claim 1, characterized in that, The method for forming the nano-stack structure is as follows: Form a mask stack on the surface of the second silicon layer; Pattern the mask stack; Under the protection of the mask stack, etch the first silicon layer, the first germanium-silicon layer, the second germanium-silicon layer, the third germanium-silicon layer, and the second silicon layer to form a nano-stack structure.

7. The manufacturing method according to claim 6, wherein The mask stack includes an etch stop layer, a dummy mask layer, and a silicon oxide layer that are stacked in sequence from bottom to top.

8. The manufacturing method according to claim 7, characterized in that, The etch stop layer is silicon oxide; And / or The dummy mask layer has a high etch selectivity with respect to silicon oxide.

9. The manufacturing method according to claim 1, characterized in that, The depths of the first groove and the third groove are 5 nm - 25 nm.

10. The manufacturing method according to claim 7, characterized in that, The method for forming the inner sidewalls of the extended region in the first groove and the third groove includes: Deposit inner sidewall material of the extended region until all outer surfaces are covered; Then perform chemical mechanical polishing or selective etching on the inner sidewall material of the extended region and the silicon oxide layer in the mask stack until the dummy mask layer in the mask stack is exposed; Then perform anisotropic etching until the inner sidewall material of the extended region only fills the first groove and the third groove, thereby forming the inner sidewalls of the extended region.

11. The manufacturing method according to claim 10, characterized in that, The inner sidewall material of the extended region is silicon oxide.

12. The manufacturing method according to claim 10, characterized in that, Before the anisotropic etching and after the silicon layer in the mask stack is exposed, it further includes: Filling the inner sidewall material of the extended region over a large area; Remove the dummy mask layer in the mask stack by selective etching to form a mask groove; Fill the mask groove with a material having a large etching selectivity ratio with respect to silicon oxide to form a replacement mask.

13. The manufacturing method according to claim 12, characterized in that, The material filled in the mask groove is the same as the dummy gate.

14. The manufacturing method according to any one of claims 7, 10 or 12, characterized in that, The method of forming a dummy gate in the gate groove includes: Deposit a dummy gate material until all outer surfaces are covered; Then anisotropically etch until only the gate groove is filled with the dummy gate material to form a dummy gate; Remove the mask stack before performing doping to form source / drain implants.

15. The manufacturing method according to claim 1, characterized in that, The method of forming an active region having a shallow trench isolation layer includes: Form a sidewall protection layer of the inner sidewall of the extended region on the sidewall of the nano stack structure; Then etch the substrate to form an active region; Deposit a dielectric material until all outer surfaces are covered again; Etch back again until the surface height of the dielectric material is flush with the upper surface height of the first germanium silicon layer to form a shallow trench isolation layer.

16. The manufacturing method according to claim 1, wherein The dielectric material includes at least one of silicon oxide, PSG, BSG, and BPSG.

17. The manufacturing method according to claim 15, characterized in that, The method of removing the dummy gate includes: Etch the sidewall protection layer until a part of the sidewall protection layer material remains between the shallow trench isolation layer and the first silicon layer, and the remaining sidewall protection layer and the dummy gate are removed by selective etching.

18. The manufacturing method according to claim 1, characterized in that, After forming the gate, the gate is also patterned to form contact holes.

19. The manufacturing method according to claim 15, characterized in that, The sidewall protection layer and the dummy gate are made of the same material.

20. The manufacturing method according to claim 19, characterized in that, The sidewall protection layer and the dummy gate are silicon nitride or silicon oxynitride.

21. A vertical MOSFET device, characterized in that, Comprising a substrate, and source / drain electrodes, a first extended region, a channel, a second extended region, and source / drain electrodes stacked on the substrate from bottom to top; on both sides of the channel are gates, and the gates are isolated from the channel by a gate dielectric; on both sides of the first extended region are first inner sidewalls, on both sides of the second extended region are second inner sidewalls, and the gates are located between the first inner sidewalls and the second inner sidewalls; Wherein, the first extended region, the channel, and the second extended region are all made of germanium silicon material, and the molar content of germanium in the first extended region and the second extended region is greater than the molar content of germanium in the channel; the source / drain electrodes are doped silicon; The device further includes a shallow trench isolation layer, and a part of the sidewall protection layer material is provided between the shallow trench isolation layer and the source / drain electrodes.

22. The vertical MOSFET device according to claim 21, wherein The first inner sidewall and the second inner sidewall are silicon oxide.

23. The vertical MOSFET device according to claim 21, wherein, The molar content of germanium in the first extended region and the second extended region is the same, and is more than 15%.

24. The vertical MOSFET device according to claim 21, wherein The molar content of germanium in the first extended region and the second extended region is 15% - 30%, and / or, the molar content of germanium in the channel is 5% - 15%.

25. The vertical MOSFET device according to claim 21, wherein The sidewalls of the source / drain electrodes, the sidewalls of the first inner sidewalls, and the sidewalls of the second inner sidewalls are connected to form a groove profile, and the gates are located in the grooves.

26. The vertical MOSFET device according to claim 25, wherein, The width of the first inner sidewall of the first extended region parallel to the nanowire channel direction is 5 - 15 nm, and / or, the depth of the groove perpendicular to the nanowire channel direction is 5 - 25 nm.

27. The application of the vertical MOSFET device according to any one of claims 21 - 26 or the vertical MOSFET device manufactured by the manufacturing method according to any one of claims 1 - 20 in an electronic device.

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