A power control device, a chip, a charging case, and earphones

Abstract

This application discloses a power control device, a chip, a charging case, and earphones, belonging to the field of power control. The device includes a DC-DC boost circuit, a low-power oscillation circuit, and a logic circuit. The logic circuit is connected to the other two circuits. The DC-DC boost circuit is connected to the output terminal and the power supply, and is used to output electrical energy from the power supply. The low-power oscillation circuit provides a periodic trigger signal to the logic circuit to determine whether the DC-DC boost circuit is activated when the earphones are continuously in the case. The logic circuit controls the DC-DC boost circuit to be activated during a first time period and deactivated during a second time period. The first time period is the period during which electrical energy is output to the output terminal via the power supply. By using the periodic trigger signal from the low-power oscillation circuit and the logic circuit to control the DC-DC boost circuit to be deactivated when it is determined that no electrical energy needs to be output to the output terminal via the power supply, the power consumption of the power control device can be reduced.

Description

Technical Field

[0001] This application relates to the field of power control, and in particular to a power control device, a chip, a charging case, and earphones. Background Technology

[0002] With the continuous development of electronic technology, true wireless stereo (TWS) earbuds have also emerged. TWS earbuds come with a charging case to charge them. When the earbuds are inserted into the charging case, the case's power module charges them. However, when the earbuds are not in the charging case, the case's power module remains on, and this additional power consumption reduces the case's standby time. Summary of the Invention

[0003] This application provides a power control device, a chip, a charging case, and earphones for reducing the power consumption of Bluetooth earphone charging cases.

[0004] The technical solution is as follows:

[0005] In a first aspect, a power control method is provided, the method being applied to a power control device, the device comprising:

[0006] The system includes a DC boost circuit, a low-power oscillation circuit, and a logic circuit. The logic circuit is connected to the DC boost circuit and the low-power oscillation circuit, respectively. The DC boost circuit is also connected to an output terminal and a power supply.

[0007] The DC boost circuit converts the electrical energy from the power supply and outputs it through the output terminal;

[0008] When the power supply is required to convert electrical energy and output it through the output terminal, the low-power oscillation circuit provides a periodic trigger signal to the logic circuit. The trigger signal is used to determine whether the DC boost circuit is turned on when the headphones are continuously in the case.

[0009] The logic circuit controls the DC boost circuit to turn on during a first time period and controls the DC boost circuit to turn off during a second time period outside the first time period. The first time period is the period during which electrical energy is output to the output terminal through the power supply. The start time of the first time period is the first moment, which is the moment corresponding to the rising edge of the trigger signal.

[0010] This application provides a power control method that, through the design of a low-power oscillation circuit and a logic circuit, uses the low-power oscillation circuit to provide a periodic trigger signal to the logic circuit. Therefore, when it is determined that no power is needed to output to the output terminal through the power supply, the logic circuit can control the DC-DC boost circuit to shut down according to the trigger signal. Since the DC-DC boost circuit is shut down when no power is needed to output to the output terminal, the power consumption generated by the DC-DC boost circuit when no power supply is required is reduced, thereby lowering the power consumption of the power control device.

[0011] Secondly, a power control device is provided, the device comprising: a DC boost circuit, a low-power oscillation circuit, and a logic circuit, wherein the logic circuit is connected to the DC boost circuit and the low-power oscillation circuit respectively, the DC boost circuit is also connected to an output terminal and a power supply, and the DC boost circuit is used to convert the electrical energy of the power supply and output it through the output terminal.

[0012] The low-power oscillation circuit is used to provide a periodic trigger signal to the logic circuit, and the trigger signal is used to determine whether the DC boost circuit is turned on when the earphone is continuously in the cabin.

[0013] The logic circuit is used to control the DC boost circuit to turn on during a first time period and to control the DC boost circuit to turn off during a second time period outside the first time period. The first time period is the period during which electrical energy is output to the output terminal through the power supply. The start time of the first time period is the first moment, which is the moment corresponding to the rising edge of the trigger signal.

[0014] In one possible implementation of this application, the logic circuit is configured to output a first enable signal to the DC-DC boost circuit during a first time period, the first enable signal being used to trigger the DC-DC boost circuit to turn on, and to output a first disable signal to the DC-DC boost circuit during a second time period, the first disable signal being used to trigger the DC-DC boost circuit to turn off.

[0015] This application controls the opening and closing of the DC boost circuit by outputting a first enable signal or a first disable signal at different time periods through a logic circuit, which can accurately enable the power control device to operate at the appropriate time period.

[0016] In one possible implementation of this application, the logic circuit is used to determine the time period during which the output terminal is not connected to the electrical device, or the time period during which the output terminal is connected to the electrical device but the electrical device has a full charge, as the second time period during which no power needs to be output to the output terminal through the power supply.

[0017] In this application, the logic circuit can determine the time period during which no power is needed to be output from the power supply under different conditions. The power control device can then control the circuit based on the determined time period to reduce power consumption.

[0018] In one possible implementation of this application, the end time of the first time period is the time when the electrical equipment is fully charged, and the power control device further includes a device insertion detection circuit connected to the logic circuit.

[0019] The device insertion detection circuit is connected to the output terminal and is used to detect whether the electrical device is connected to the output terminal. Optionally, the device insertion detection circuit is used to output a first control signal to the logic circuit during the time period when the electrical device is not connected to the output terminal, the first control signal being used to determine that the electrical device is not connected to the output terminal;

[0020] The logic circuit is further configured to determine the time period during which the electrical equipment is not connected to the output terminal as the second time period.

[0021] Optionally, the device insertion detection circuit is configured to output a second control signal to the logic circuit from the rising edge of the trigger signal during a third time period during which the electrical device is connected to the output terminal, when the electrical device is connected to the output terminal. The second control signal is used to determine that the electrical device is connected to the output terminal.

[0022] The logic circuit is further configured to determine the first time period based on the time period during which the electrical equipment is connected to the output terminal.

[0023] The device insertion detection circuit in this application can provide a signal of device insertion. Based on the signal emitted by the device insertion detection circuit, the power control device can determine a first time period and a second time period.

[0024] Optionally, the power control device further includes a device full charge detection circuit, which is used to output a third control signal to the logic circuit during a fourth time period when the power device is not fully charged, starting from the rising edge of the trigger signal. The third control signal is used to determine that the power device is not fully charged.

[0025] The logic circuit is further configured to determine the first time period based on the third time period and the fourth time period. Optionally, the first time period is the intersection of the third time period and the fourth time period.

[0026] In this application, the power status of electrical equipment can be determined by the equipment full charge detection circuit and the control signal emitted by the equipment full charge detection circuit.

[0027] Optionally, when an electrical device is connected to the output terminal and the electrical device is fully charged, the device full charge detection circuit is further configured to output a third control signal to the logic circuit when the rising edge of each RECH signal output by the logic circuit arrives, and to output a fourth control signal to the logic circuit each time the electrical device is fully charged. The third control signal is used to determine that the electrical device is not fully charged, and the fourth control signal is used to indicate that the electrical device is fully charged.

[0028] Optionally, the DC boost circuit is also configured to activate upon the arrival of the rising edge of each RECH signal, at which time the device full-charge detection circuit also activates. After a period of time, once the device full-charge detection circuit detects that the device is fully charged, the DC boost circuit is deactivated.

[0029] Optionally, the power control device further includes: a linear charger and the power supply, the logic circuit is connected to the linear charger, the linear charger is connected to the power supply, and when the input voltage of the linear charger is greater than the voltage of the power supply, the logic circuit is used to trigger the linear charger to charge the power supply.

[0030] In this application, a linear charger is used to charge a power supply. Under the control of logic circuits, the linear charger charges the power supply when an adapter is connected.

[0031] Thirdly, a chip is provided that employs the aforementioned power control device.

[0032] Fourthly, a charging case is provided, which employs the aforementioned power control device or the aforementioned chip.

[0033] Optionally, the charging case is a Bluetooth headset charging case.

[0034] Fifthly, an earphone is provided, the earphone including an earphone body and a charging case as described above, wherein when the earphone body is located in the charging case, the charging case is used to charge the earphone body.

[0035] It is understood that the beneficial effects of the second, third, fourth, and fifth aspects mentioned above can be found in the relevant descriptions in the first aspect above, and will not be repeated here. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of a power control device provided in an embodiment of this application;

[0038] Figure 2 This is a graph showing the changes of various signals over time in the power control device provided in the embodiments of this application;

[0039] Figure 3 This is a schematic diagram of the structure of a power control device provided in an embodiment of this application;

[0040] Figure 4 This is a graph showing the changes of various signals over time in the power control device provided in the embodiments of this application;

[0041] Figure 5 The power supply voltage curve and the signal curve of the linear charger are provided in the embodiments of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0043] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0044] Before providing a detailed explanation of the embodiments of this application, the application scenarios of these embodiments will be described first.

[0045] During the operation of the Bluetooth earphone charging case, various modules consume electrical energy, especially the DC-DC boost circuit 103, which requires significant power consumption. The main function of the DC-DC boost circuit 103 is to convert the electrical energy from the power supply 20 and output it through the output terminal to charge the connected device. However, the device does not always need to be charged. For example, when the device is not connected to the output terminal or has sufficient power, it does not need to be charged, and therefore the DC-DC boost circuit 103 does not need to be in operation. However, in the current technology, the DC-DC boost circuit 103 is always in operation regardless of whether it needs to charge the device. The power consumption of the DC-DC boost circuit 103 can reach 200μA, resulting in excessive power consumption of the Bluetooth earphone charging case and a shorter standby time.

[0046] Therefore, this application provides a power control device applicable to a wireless Bluetooth headset charging case for controlling the switching state of the DC boost circuit 103, thereby reducing the power consumption caused by the DC boost circuit 103.

[0047] It is worth noting that the power control device provided in this application is not limited to use in Bluetooth headset charging cases. In the following embodiments, a Bluetooth headset charging case is used as an example. The power user is a Bluetooth headset that is paired with the charging case. After the Bluetooth headset is inserted into the charging case, it is directly connected to the power output terminal of the power control device. It is understood that the Bluetooth headset has one or more contact terminals, which can be connected to one or more contact terminals of the Bluetooth headset charging case, allowing the Bluetooth headset to obtain power from the charging case. Optionally, the one or more contact terminals of the Bluetooth headset charging case can be the output terminal of the power control device, or the one or more contact terminals of the Bluetooth headset charging case can correspond to the output terminal of the power control device.

[0048] The power control device provided in the embodiments of this application will be explained in detail below.

[0049] Figure 1 A power control device 10 provided in the embodiments of this application, such as Figure 1 As shown, the power control device 10 includes a low-power oscillator 101, a logic circuit 102, and a DC-DC boost circuit 103. The logic circuit 102 is connected to both the DC-DC boost circuit 103 (e.g., a Boost DC-DC module) and the low-power oscillator 101. The DC-DC boost circuit 103 is also connected to its output terminal (VOUT) and the power supply 20. The DC-DC boost circuit 103 converts the electrical energy from the power supply 20 and outputs it through its output terminal. The low-power oscillator 101 provides a periodic trigger signal (LP_CNT signal) to the logic circuit 102. The trigger signal is used to determine whether to turn on the DC-DC boost circuit 103.

[0050] The logic circuit 102 is used to control the DC boost circuit 103 to turn on in a first time period and to control the DC boost circuit 103 to turn off in a second time period other than the first time period. The first time period is the time period during which electrical energy is output to the output terminal through the power supply 20. The start time of the first time period is the first moment, which is the moment corresponding to the rising edge of the trigger signal.

[0051] Combination Figure 2 The first time period can be the period from t2 to t3. The first moment is time t2. The second time period can be the period before time t2 and / or the period after time t3.

[0052] It is understandable that when the DC boost circuit 103 is turned on, it is in a working state, meaning it can convert the electrical energy from the power supply 20 and output it through the output terminal. When the DC boost circuit 103 is turned off, it will no longer convert the electrical energy from the power supply 20 and output it through the output terminal.

[0053] The so-called low-power oscillation circuit 101 is a clock generation circuit used to output periodic signals.

[0054] The so-called logic circuit 102 is a discrete signal transmission and processing circuit. It is a circuit that implements digital signal logic operations and manipulations based on binary principles. In this application, the logic circuit 102 is used to receive and send corresponding high-level or low-level signals to control the switching state of the modules or circuits connected to the logic circuit 102.

[0055] The so-called DC boost circuit 103 is used to convert a voltage of value A into DC voltage of different values, and its output voltage will be higher than the input voltage.

[0056] This application provides a power control device. This device includes a logic circuit and a low-power oscillator 101. The periodic trigger signal provided by the low-power oscillator 101 is used to determine whether to turn on the DC-DC boost circuit 103. The logic circuit then controls the DC-DC boost circuit 103 to turn on during a first time period starting from the rising edge of the trigger signal. Since the first time period is the period when the power supply 20 outputs power to the output terminal, turning on the DC-DC boost circuit 103 during this time can supply power to the electrical equipment. During a second time period, excluding the first time period, the DC-DC boost circuit 103 is turned off. The second time period is the period when no power is needed to output to the output terminal. Therefore, turning off the DC-DC boost circuit 103 during this time can reduce the power consumption caused by turning on the DC-DC boost circuit 103 during periods when no power is needed to supply power to the electrical equipment.

[0057] like Figure 2As shown, Figure 2 The waveform of the trigger signal LP_CNT output by the low-power oscillator circuit 101 is shown. As an example, the trigger signal for each cycle includes an enable signal and a disable signal. For example, the enable signal can be a high-level signal, and the disable signal can be a low-level signal. The duration of the high-level signal is the ratio of the duty cycle Du to the frequency f, and the duration of the low-level signal is 1 - the ratio of the duty cycle Du to the frequency f.

[0058] The trigger signal LP_CNT output by the low-power oscillation circuit 101 is used by the logic circuit 102 to determine whether to enable the DC boost circuit 103.

[0059] In one possible implementation of this application, a logic circuit is configured to output a first enable signal to a DC-DC boost circuit during a first time period, wherein the first enable signal is used to trigger the DC-DC boost circuit to turn on, and to output a first disable signal to the DC-DC boost circuit during a second time period, wherein the first disable signal is used to trigger the DC-DC boost circuit to turn off.

[0060] As an example, the first enable signal is a high-level signal, and the first disable signal is a low-level signal.

[0061] Specifically, during the time period when the logic circuit 102 determines that there is no need to output power to the output terminal through the power supply 103, the logic circuit 102 controls the DC boost circuit 103 to turn off, regardless of whether the trigger signal is a high-level signal or a low-level signal. For example... Figure 2 As shown, during the period before time t1, the earphones were not inserted into the charging case, meaning there was no need for power supply 103 to output power to the output terminal. However, due to the periodicity of the trigger signal before time t1, the trigger signal exhibited both high and low level signals during this period. Figure 2 As can be seen from the BET_EN waveform, before time t1 and after time t0, that is, during the time period from t0 to t1, the BET_EN signal output by logic circuit 102 is always an inactive signal (i.e., a low-level signal).

[0062] In one possible implementation of this application, a logic circuit is used to determine the second time period in which no electrical energy needs to be output to the output terminal through the power supply, either the time period in which the output terminal is not connected to the electrical device, or the time period in which the output terminal is connected to the electrical device but the electrical device has a full charge.

[0063] It is understandable that if the output terminal is not connected to the electrical device (e.g., headphones), it means that there is no need to supply power to the electrical device at this time; in other words, there is no need to output electrical energy to the output terminal through the power supply.

[0064] In one possible embodiment of this application, combined with Figure 1 ,like Figure 3 As shown, the power control device 10 in this embodiment may further include a device insertion detection circuit 105 connected to the output terminal and the logic circuit 102. The device insertion detection circuit 105 detects the state of the output terminal and provides information to the logic circuit 102 to determine the state of the output terminal. The state of the output terminal indicates whether a power-consuming device is connected to the output terminal. In other words, the device insertion detection circuit 105 detects whether a power-consuming device is connected to the output terminal.

[0065] For example, the device insertion detection circuit is used to output a first control signal to the logic circuit during the time period when the electrical device is not connected to the output terminal. The first control signal is used to determine that the electrical device is not connected to the output terminal. Correspondingly, the logic circuit is also used to determine the time period when the electrical device is not connected to the output terminal as the second time period.

[0066] Combination such as Figure 2 The CH_OK waveform diagram shown illustrates this. Taking headphones as the device and a low-level signal as the first control signal, during the time period before time t1 and after time t5, the headphones are not plugged into the output terminal (also known as the headphones not connected to the output terminal or connected to the output terminal). During this time period, the device insertion detection circuit 105 continuously outputs a low-level CH_OK signal to the logic circuit 102. Therefore, during the time period before time t1 and after time t5, the BET_EN signal output by the logic circuit 102 is the first non-enable signal (e.g., a low-level signal). Although the headphones are inserted into the output terminal at time t1, since time t1 corresponds to the inactive trigger signal, the device insertion detection circuit 105 continues to output a low-level CH_OK signal to the logic circuit 102 between time t1 and the rising edge of the trigger signal after time t1. Therefore, during the time period between time t1 and the rising edge t2 of the trigger signal after time t1, the BET_EN signal output by the logic circuit 102 continues to be the first inactive signal (e.g., a low-level signal). At time t5, the device insertion detection circuit 105 detects that the headphones have been removed from the output terminal. At this time, the device insertion detection circuit 105 outputs a first active BET_EN signal to the logic circuit 102 starting from time t5.

[0067] Therefore, as Figure 2As shown, during the time period before time t2 and during the time period after time t5, the logic circuit 102 is used to output the BET_EN signal as the first non-enable signal to trigger the DC boost circuit 103 to turn off, thereby achieving the purpose of controlling the DC boost circuit 103 to turn off when the electrical equipment is not connected to the output terminal, and reducing the power consumption caused by the DC boost circuit 103.

[0068] In one possible embodiment of this application, combined with Figure 3 The device insertion detection circuit is configured to, when the electrical device is connected to the output terminal, output a second control signal to the logic circuit during a third time period from the rising edge of the trigger signal, wherein the second control signal is used to determine that the electrical device is connected to the output terminal. The logic circuit is further configured to determine the start time of the first time period based on the time period during which the electrical device is connected to the output terminal.

[0069] Optionally, the logic circuit is specifically used to determine the time period during which the electrical equipment is connected to the output terminal as a first time period.

[0070] For example, such as Figure 2 As shown, although the headphones are inserted into the output terminal at time t1, the trigger signal is not enabled at time t1, and the rising edge of the trigger signal occurs at time t2. Since the trigger signal is a periodic signal, although falling and rising edges of the trigger signal appear periodically after a certain period of time (e.g., Du / f), the phone is still inserted into the output terminal during this period (tx to t5). Therefore, during the tx to t5 period, the device insertion detection circuit continues to output a high-level signal to the logic circuit. At time t5, the device insertion detection circuit 105 detects that the headphones have been removed from the output terminal. Therefore, the time period between time t2 and time t5 is the third time period. tx is the time determined by t2 + Du / f.

[0071] Although the above solution controls the DC-DC boost circuit 103 to be off when the electrical equipment is plugged into the output terminal, this reduces power consumption caused by the DC-DC boost circuit 103 compared to the prior art where the DC-DC boost circuit 103 is always on regardless of whether the electrical equipment is plugged in. However, in practice, when the electrical equipment is continuously in the compartment, the DC-DC boost circuit is forcibly turned on to charge the electrical equipment after the rising edge of each RECH signal. However, since the power consumption of the electrical equipment continuously in the compartment is very small, the equipment full charge detection circuit will quickly detect that the electrical equipment is fully charged and then turn off the DC-DC boost circuit. Because the power consumption of the electrical equipment continuously in the compartment is small, the period of the periodic signal RECH is set to a longer time to reduce the average power consumption of the power control device itself. Based on this, we will continue to combine... Figure 3 ,like Figure 3 As shown, the power control device also includes the device full charge detection circuit, which is used to detect the power of the electrical device connected to the output terminal, and to report an LD_OK signal to the logic signal to indicate whether the electrical device is in a fully charged state based on the power of the electrical device.

[0072] Specifically, the device full-charge detection circuit outputs a third control signal to the logic circuit during a fourth time period when the device is not fully charged, starting from the rising edge of the trigger signal. This third control signal determines that the device is not fully charged. The logic circuit also determines the first time period based on the third and fourth time periods. For example, the third control signal can be a low-level signal, and the fourth control signal can be a high-level signal.

[0073] Optionally, the first time period is the intersection of the third and fourth time periods; that is, the logic circuit uses the intersection of the third and fourth time periods to determine the first time period. However, typically, the time period during which the electrical device is plugged into the output terminal is longer than or equal to the time period during which the device's battery level rises from its initial charge state to full charge. Therefore, the first time period is actually the fourth time period. The initial charge state refers to the battery level when power is supplied to the device after it is plugged into the output terminal.

[0074] Combination Figure 4During the time period t2-t3, the power consumption of the electrical equipment continuously increases until it reaches full charge at time t3. t2 can also be considered the moment when power supply to the electrical equipment begins. Therefore, the time period t2-t3 is the fourth time period. During this period, the device is fully charged, and the detection circuit outputs the LD_OK signal, which is the third control signal, to the logic circuit. For example, the third control signal can be a low-level signal. In this case, for logic circuit 102, during the fourth time period, the logic circuit outputs a high-level signal to the DC-DC boost circuit based on the low-level signal from the device full charge detection circuit and the high-level signal from the device insertion detection circuit, thereby triggering the DC-DC boost circuit to turn on.

[0075] Optionally, the device full charge detection circuit is used to output a fourth control signal to the logic circuit from the fifth time period starting from the moment when the electrical device is in a fully charged state. The fourth control signal is used to indicate that the electrical device is in a fully charged state. The fifth time period corresponds to the time period corresponding to the non-enable signal of the trigger signal.

[0076] like Figure 4 The LD_OK waveform diagram shown indicates that the device is fully charged at time t3. Therefore, the time period after time t3 can be considered the fifth time period. The device is fully charged, and the detection circuit outputs the LD_OK signal, which is the fourth control signal, to the logic circuit. The fourth control signal can be a high-level signal.

[0077] Optionally, when an electrical device is connected to the output terminal and the electrical device is fully charged, the device full charge detection circuit is further configured to output a third control signal to the logic circuit when the rising edge of each RECH signal output by the logic circuit arrives, and to output a fourth control signal to the logic circuit when the falling edge of each RECH signal arrives. The third control signal is used to determine that the electrical device is not fully charged, and the fourth control signal is used to indicate that the electrical device is fully charged.

[0078] For example, to continue combining, such as Figure 4 As shown in the LD_OK waveform diagram, the device is fully charged at time t3, and the rising edge of the RECH signal output by logic circuit 102 occurs at time t4. Therefore, during the time period from time t3 to time t4, which is the period when the RECH signal is low, the device's charge detection circuit outputs a high-level signal to logic circuit 102. At time t4, due to the arrival of the rising edge of the RECH signal, the device's charge detection circuit resets, i.e., it outputs a low-level signal, and at the same time, the DC boost circuit 103 is turned off.

[0079] Specifically, the device insertion detection circuit 105 is configured with a preset period of 1. It periodically detects whether the electrical device is connected to the output terminal, i.e., the output terminal's state. When the output terminal is in the first state, it indicates that the electrical device is connected to the output terminal, and the CH_OK signal output by the device insertion detection circuit 105 is a high-level signal. When the output terminal is in the second state, it indicates that the electrical device is not connected to the output terminal, and the CH_OK signal output by the device insertion detection circuit 105 is a low-level signal. A third control signal is used to indicate that the electrical device is not connected to the output terminal. In this case, the logic circuit 102 determines that there is no need to output power to the output terminal through the power supply 20. The logic circuit 102 then combines the BST_EN signal output by the low-power oscillator 101 (whether it is a high-level or low-level signal) to determine whether to output power to the output terminal through the power supply 20. For example, if the electrical device is connected to the output terminal during the corresponding time period and the BST_EN signal is a high-level signal, then power will be output to the output terminal through the power supply 20. Figure 2 The time period following time t2 is shown. During the time period corresponding to the output terminal of the electrical equipment, and if the BST_EN signal is low, there is no need to output power to the output terminal through power supply 20. For example... Figure 2 The time intervals t1-t2 are shown.

[0080] Specifically, the device full charge detection circuit 106 is configured with a preset period 2, and the device full charge detection circuit 106 periodically detects the power level of the electrical device connected to the output terminal. When the electrical device is fully charged, the LD_OK signal provided by the device full charge detection circuit 106 to the logic circuit 102 is a high-level signal. At this time, the logic circuit 102 determines based on the high-level signal that there is no need to output power to the output terminal through the power supply.

[0081] Optionally, the device full charge detection circuit 106 is also used to provide a low-level signal to the logic circuit 102 indicating that the device is not fully charged. In other words, the LD_OK signal provided by the device full charge detection circuit 106 to the logic circuit 102 is a low-level signal at this time. At this time, the logic circuit 102 determines, based on the fourth control signal, that a power supply is needed to output power to the output terminal.

[0082] To reduce the power consumption of the device full charge detection circuit 106 when it is in operation, under normal circumstances, when no electrical device is connected to the output terminal, the logic circuit 102 does not need to know whether the electrical device is fully charged. Therefore, the logic circuit 102 provided in this application embodiment is also used to send a trigger signal X to the device full charge detection circuit 106 when it is determined that the electrical device is connected to the output terminal. The trigger signal X is used to trigger the device full charge detection circuit 106 to start detecting the power status of the electrical device. In other words, before receiving the trigger signal X, the device full charge detection circuit 106 can be in a closed state.

[0083] It is understandable that the device full detection circuit 106 and the device insertion detection circuit 105 can be configured to continuously detect in addition to periodic detection according to their respective cycles, except that continuous detection consumes more power than periodic detection.

[0084] In one possible embodiment of this application, when an electrical device is connected to the output terminal and the device is fully charged, the DC boost circuit is further configured to activate upon the arrival of each rising edge of the RECH signal, and the full charge detection circuit 103 will also activate. After a period of time, once the device full charge detection circuit 106 detects that the device is fully charged (full charge will be detected even without load), the DC boost circuit will deactivate.

[0085] Specifically, when a power device is connected to the output terminal and the device is fully charged, the DC-DC boost circuit is forcibly activated after each rising edge of the RECH signal. Subsequently, the device full-charge detection circuit detects whether the device is fully charged, and shuts off the DC-DC boost circuit when the device is fully charged. When the device is continuously connected to the output terminal, the RECH signal is used to send a trigger signal for repeatedly charging the device, i.e., triggered by a rising edge, activating the DC-DC boost circuit 103. After the device full-charge detection circuit 106 detects that the device is fully charged, it shuts off the DC-DC boost circuit 103. It can be understood that the time period from the falling edge of the RECH signal to the next rising edge is the low-level time period, and the time period from the rising edge of the RECH signal to the next falling edge is the high-level time period.

[0086] Understandably, when fully charged, the DC-DC boost circuit periodically turns on, following the cycle of the RECH signal. To further reduce power consumption caused by the DC-DC boost circuit in this scenario, the period when the RECH signal is low is longer than the period when it is high. Since the period when the RECH signal is high is relatively short, the power consumption caused by the DC-DC boost circuit can be reduced.

[0087] In an optional embodiment of this application, the power control device further includes: a linear charger and the power supply, the logic circuit is connected to the linear charger, the linear charger is connected to the power supply, and when the input voltage of the linear charger is greater than the voltage of the power supply, the logic circuit is used to trigger the linear charger to charge the power supply.

[0088] In one possible implementation of this application, the total charge consumed by the power supply control device is determined by calculating the quiescent current. The formula for calculating the quiescent current is as follows:

[0089] IQ = IDC + Q*f

[0090] Where IQ is an adjustable parameter, representing the total charge consumed by the power control device, with an adjustment range greater than or equal to 400nA, which can be understood as the power consumption of the power control device. IDC refers to the operating current of the low-power oscillation circuit 101, which is 400nA. Q represents the current at which the power is consumed. Figure 2 The figure shows the total charge consumed by the DC boost circuit 103 during the time period Tb. f is the frequency of the low-power oscillation circuit 101LP_CNT signal.

[0091] As an example, IDC is 400nA. The typical output voltage of the DC-DC boost circuit 103 is 5V, the capacitor is 4.7μF, and the charge required to charge the capacitor from 0V to 5V is 23.5μC, therefore Q is 24.1μC. The frequency f is 1 / 40s. Therefore, the calculation yields:

[0092] IQ=400nA+24.1μC / 40S=1002.5nA=1.0025μA

[0093] This indicates that the power consumption of the power control device is 1.0025μA, which meets the standard for reducing the power consumption of the charging case. Here, the frequency f is a range value, i.e., f≤1 / 40s. Therefore, in practice, the power consumption of the power control device is ≤1.0052μA.

[0094] This application provides a chip that uses the power control device described above. The chip includes a low-power oscillation circuit 101, a logic circuit 102, a DC boost circuit 103, a linear charger 104, a device insertion detection circuit 105, and a device full charge detection circuit 106.

[0095] This application provides a charging case that uses the power control device described above, or, as described above, the chip.

[0096] In one embodiment of this application, the electronic device includes a Bluetooth headset charging case. The power chip in the Bluetooth headset charging case is designed using the power control device described above, or the above chip is used as the power chip for the Bluetooth headset charging case.

[0097] This application provides an earphone, which includes an earphone body and the aforementioned charging case. When the earphone body is located in the charging case, the charging case is used to charge the earphone body.

[0098] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0099] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0100] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power control device, characterized by comprising: The device comprises a direct current boosting circuit, a low-power oscillation circuit, a logic circuit and a device fullness detection circuit, The logic circuit is connected with the direct current boosting circuit and the low-power oscillation circuit respectively, and the direct current boosting circuit is further connected with an output end and a power supply; the direct current boosting circuit is used to convert the power of the power supply and output through the output end; In the case that the power of the power supply needs to be converted and output through the output end, the low-power oscillation circuit is used to provide a periodic trigger signal to the logic circuit; the trigger signal is used to determine whether the direct current boosting circuit is started when the power-using device is continuously connected with the power supply; The logic circuit is used to control the direct current boosting circuit to be started in a first time period and to be stopped in a second time period except the first time period; the first time period is a time period in which the power of the power supply is output to the output end; the starting time of the first time period is a first time; the first time is a time corresponding to a rising edge of the trigger signal; The device fullness detection circuit is used to output a third control signal to the logic circuit in a fourth time period in which the power-using device is not in a full power state from the rising edge of the trigger signal; the third control signal is used to determine that the power-using device is not in the full power state; the logic circuit is further used to determine the first time period according to a third time period and the fourth time period; the second time period comprises a time period in which the output end is connected with the power-using device and the power-using device is in the full power state; the third time period is a time period from the first time to a time when the power-using device is not connected with the output end.

2. The power control device of claim 1, wherein The logic circuit is used to output a first enable signal to the direct current boosting circuit in the first time period; the first enable signal is used to trigger the direct current boosting circuit to be started; and output a first non-enable signal to the direct current boosting circuit in the second time period; the first non-enable signal is used to trigger the direct current boosting circuit to be stopped.

3. The power control device of claim 1, wherein The logic circuit is used to determine, as the second time period in which the power of the power supply is not output to the output end, a time period in which the output end is not connected with the power-using device or a time period in which the output end is connected with the power-using device but the power-using device is in a full power state.

4. The power supply control device according to any one of claims 1 to 3, characterized by The ending time of the first time period is a time when the power-using device is in the full power state; the power control device further comprises a device insertion detection circuit connected with the logic circuit; The device insertion detection circuit is connected with the output end and is used to detect whether the power-using device is connected with the output end.

5. The power control device of claim 4, wherein The device insertion detection circuit is used to output a first control signal to the logic circuit in a time period in which the power-using device is not connected with the output end; the first control signal is used to determine that the power-using device is not connected with the output end. The logic circuit is further used to determine, as the second time period, a time period in which the power-using device is not connected with the output end.

6. The power control device of claim 4, wherein The device insertion detection circuit is configured to output a second control signal to the logic circuit in a third time period during which the electrical device is connected to the output terminal, starting from a rising edge of the trigger signal, when the electrical device is connected to the output terminal, the second control signal being configured to determine that the electrical device is connected to the output terminal. The logic circuit is further configured to determine the first time period according to a time period during which the electrical device is connected to the output terminal.

7. The power control device of claim 1, wherein The first time period is an intersection of the third time period and the fourth time period.

8. The power control device of claim 7, wherein The device fullness detection circuit is configured to output a fourth control signal to the logic circuit in a fifth time period, starting from a time point at which the electrical device is in a full state, the fourth control signal being configured to indicate that the electrical device is in the full state, the fifth time period corresponding to a time period corresponding to a non-enabled signal of the trigger signal.

9. The power control device according to any one of claims 1 to 3, characterized by When the electrical device is connected to the output terminal and the electrical device is in the full state, the device fullness detection circuit is further configured to output a third control signal to the logic circuit when a rising edge of each RECH signal output by the logic circuit arrives, and output a fourth control signal to the logic circuit when a falling edge of each RECH signal output by the logic circuit arrives, the third control signal being configured to determine that the electrical device is not in the full state, and the fourth control signal being configured to indicate that the electrical device is in the full state.

10. The power control device of claim 9, wherein The DC boost circuit is further configured to be turned on when a rising edge of each RECH signal arrives, and the device fullness detection circuit is turned on when the output terminal is connected to the electrical device. The DC boost circuit is turned off when the device fullness detection circuit detects that the electrical device is in the full state.

11. The power control device according to any one of claims 1 to 3, characterized by The power supply control device further comprises a linear charger and the power supply, the logic circuit is connected to the linear charger, the linear charger is connected to the power supply, and the logic circuit is configured to trigger the linear charger to charge the power supply when an input voltage of the linear charger is greater than a voltage of the power supply.

12. A chip, characterized by The chip adopts the power supply control device according to any one of claims 1 to 11.

13. A charging pod characterized by, The charging bin adopts the power supply control device according to any one of claims 1 to 11, or the chip according to claim 12.

14. The charging pod of claim 13, wherein, The charging bin is a Bluetooth earphone charging bin.

15. An earphone, characterized by The earphone comprises an earphone body and the charging bin according to claim 13 or 14, and the charging bin is configured to charge the earphone body when the earphone body is located in the charging bin. The earphone comprises an earphone body and the charging bin according to claim 13 or 14, and the charging bin is configured to charge the earphone body when the earphone body is located in the charging bin.

Images