Solid-state imaging device and electronic apparatus

Abstract

In such a solid-state imaging device for measuring distance, miniaturization of pixels is promoted. The solid-state imaging device is provided with a pixel array unit and a photon number detection unit. In the solid-state imaging device provided with the pixel array unit and the photon number detection unit, a plurality of pixels that generate a prescribed analog signal according to the incidence of photons and a signal line to which the plurality of pixels are commonly connected are provided to the pixel array unit. Further, in the solid-state imaging device, the photon number detection unit detects the number of photons that have been incident based on the analog signal transmitted via the signal line.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element. Specifically, the present technology relates to a solid-state imaging element and an electronic device that count the number of incident photons. Background Art

[0002] In an electronic device having a distance measurement function, a distance measurement method called the time-of-flight (ToF) method is generally known. The ToF method is a method of measuring the distance by irradiating an object with irradiation light from a distance measurement device and obtaining the round-trip time until the irradiation light is reflected and returned. For example, a distance measurement device has been designed in which each of a plurality of pixels is connected to an adder via a pulse waveform circuit and a signal line, histograms of the respective pixels are synthesized by the adder, and the time of the peak of the synthesized histogram is converted into a distance (for example, see Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-176750 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In the above conventional technology, compared with the case where histograms are not synthesized, the signal-to-noise ratio (S / N) can be improved by synthesizing histograms of the respective pixels. However, since each pixel needs to be connected to the adder via a signal line, the number of signal line wirings increases as the number of pixels increases due to the miniaturization of the pixels. When the number of wirings increases, the signal lines need to be made thinner, making it difficult to ensure the transmission band. In addition, due to the increase in the number of wirings, the degree of freedom in designing the wirings is reduced and the skew increases. As described above, there is a problem that it becomes difficult to miniaturize the pixels due to the increase in the number of wirings.

[0008] The present technology has been made in view of this situation, and an object thereof is to promote the miniaturization of pixels in a solid-state imaging element for measuring distance.

[0009] Solution to the Problem

[0010] The present technology has been made to solve the above problems, and a first aspect thereof is a solid-state imaging element including: a pixel array unit provided with a plurality of pixels and signal lines, the plurality of pixels generating a predetermined analog signal according to the incidence of photons, and the plurality of pixels being commonly connected to the signal line; and a photon number detection unit that detects the number of incident photons based on the analog signal transmitted via the signal line. This brings the effect of reducing the number of signal line wirings.

[0011] In addition, in the first aspect, each of the plurality of pixels may provide a current signal as an analog signal via a signal line, and the photon number detection unit may include: a current-voltage conversion unit that converts the current signal into a voltage signal; and an analog-to-digital conversion unit that converts the voltage signal into a photon number. This achieves the effect of detecting the photon number based on the current signal.

[0012] In addition, in the first aspect, each of the plurality of pixels may include: a light receiving circuit that outputs a cathode potential that decreases when photons are incident; a first pulse signal generation unit that generates a first pulse signal based on the cathode potential; and a current source transistor that outputs a current signal to the signal line according to the pulse signal. This achieves the effect of transmitting a current signal corresponding to the decrease in the cathode potential.

[0013] In addition, in the first aspect, each of the plurality of pixels may further include: a second pulse signal generation unit that generates a second pulse signal having a pulse width shorter than that of the first pulse signal based on an inverted signal obtained by inverting the cathode potential; and a masking processing unit that stops the output of the current signal to the signal line during a predetermined masking period after the second pulse signal is generated, and the analog-to-digital conversion unit may convert the voltage signal into a photon number during the masking period. This achieves the effect of masking the current signal during the masking period after generating a pulse signal based on the inverted signal of the cathode potential.

[0014] In addition, in the first aspect, each of the plurality of pixels may transmit a pair of differential signals as a current signal, and the pair of differential signals is obtained by differentially amplifying a pulse signal and a signal obtained by inverting the pulse signal. This achieves the effect of suppressing a decrease in signal level caused by an increase in wiring resistance.

[0015] In addition, in the first aspect, the analog-to-digital conversion unit may include: a zero current confirmation circuit that confirms whether a current signal is output; a time-to-digital converter that converts the elapsed time from the light emission timing to the decrease in the cathode potential into a digital value when no current signal is output; and a simultaneous reaction number detection unit that detects the number of photons incident during the elapsed time based on the digital value and the voltage signal. This achieves the effect of detecting the number of simultaneous reactions.

[0016] In addition, in the first aspect, the simultaneous reaction number detection unit may include: a peak holding circuit that holds the peak value of the voltage signal during the elapsed time; and a logic circuit that detects the photon number based on the peak value. This achieves the effect of detecting the photon number from the peak value of the voltage signal.

[0017] In addition, in the first aspect, the simultaneous reaction number detection unit may include: a sample-and-hold circuit that receives a voltage signal at a predetermined timing within an elapsed time and holds the voltage signal as a held value; and a logic circuit that detects the number of photons based on the held value. This brings the effect of detecting the number of photons from the value obtained by sample-and-hold.

[0018] In addition, in the first aspect, each of the plurality of pixels may provide a voltage signal as an analog signal via a signal line, and the photon number detection unit may include: an analog-to-digital conversion unit that converts the voltage signal into the number of photons. This brings the effect of not requiring a current-voltage conversion unit.

[0019] In addition, in the first aspect, the analog-to-digital conversion unit may detect the number of photons based on the frequency characteristics of the voltage signal. This brings the effect of not requiring a current-voltage conversion unit and detecting the number of photons based on the frequency characteristics.

[0020] In addition, in the first aspect, the analog-to-digital converter may detect the number of photons based on the conversion rate of the voltage signal. This brings the effect of reducing the circuit scale.

[0021] In addition, in the first aspect, the pixel array unit may be divided into a plurality of pixel blocks, and the photon number detection unit may detect the number of photons for each of the plurality of pixel blocks. This brings the effect of generating ranging data for each pixel block.

[0022] In addition, a second aspect of the present technology is an electronic device, including: a pixel array unit provided with a plurality of pixels and signal lines, the plurality of pixels generating a predetermined analog signal according to the incidence of photons, and the plurality of pixels being commonly connected to the signal lines; a photon number detection unit that detects the number of incident photons based on the analog signal transmitted via the signal line; and a signal processing unit that measures the distance to a predetermined object based on the number of photons. This brings the effect of reducing the number of signal line wirings in a device that performs distance measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a block diagram showing a configuration example of a ranging module in a first embodiment of the present technology.

[0024] Figure 2 is a diagram showing an example of a stacked structure of a solid-state imaging element in a first embodiment of the present technology.

[0025] Figure 3 is a plan view showing a configuration example of an optical reception chip in a first embodiment of the present technology.

[0026] Figure 4 is a plan view showing a configuration example of a logic chip in a first embodiment of the present technology.

[0027] Figure 5 is a block diagram showing a configuration example of a current signal generation unit in a first embodiment of the present technology.

[0028] Figure 6 is a circuit diagram showing a configuration example of a pixel in a first embodiment of the present technology.

[0029] Figure 7 is a plan view showing a wiring example in a pixel array unit in a first embodiment of the present technology.

[0030] Figure 8 is a block diagram showing a configuration example of an analog-to-digital conversion unit in a first embodiment of the present technology.

[0031] Figure 9 is a circuit diagram showing a configuration example of a simultaneous reaction number detection circuit in a first embodiment of the present technology.

[0032] Figure 10 is a diagram showing configuration examples of a pixel array unit, a current-voltage conversion unit, and an analog-to-digital conversion unit in a first embodiment of the present technology.

[0033] Figure 11 is a timing chart showing an operation example of a solid-state imaging element in a first embodiment of the present technology.

[0034] Figure 12 is a diagram showing an example of a histogram in a first embodiment of the present technology.

[0035] Figure 13 is a diagram showing an example of a histogram in a comparative example.

[0036] Figure 14 is a flowchart showing an operation example of a pixel in a first embodiment of the present technology.

[0037] Figure 15 is a flowchart showing an operation example of an analog-to-digital conversion unit in a first embodiment of the present technology.

[0038] Figure 16 is a plan view showing an example in which a pixel block of one column or one row is arranged in a modified example of a first embodiment of the present technology.

[0039] Figure 17 is a plan view showing an example in which a pixel block of two rows × two columns is arranged in a modified example of a first embodiment of the present technology.

[0040] Figure 18 is a plan view showing an example in which a pixel block of three rows × two columns or three rows × three columns is arranged in a modified example of a first embodiment of the present technology.

[0041] Figure 19 It is a plan view showing an example of a pixel block arranged in four rows × four columns in a modification of the first embodiment of the present technology.

[0042] Figure 20 It is a plan view showing an example of pixel blocks arranged in a staggered manner in a modification of the first embodiment of the present technology.

[0043] Figure 21 It is a plan view showing an example of a pixel block arranged in a hexagonal shape in a modification of the first embodiment of the present technology.

[0044] Figure 22 It is a plan view showing an example of a pixel block in which each pixel is hexagonal in a modification of the first embodiment of the present technology.

[0045] Figure 23 It is a circuit diagram showing an example of the configuration of pixels in the second embodiment of the present technology.

[0046] Figure 24 It is a circuit diagram showing an example of the configuration of a pulse shaping unit and a masking processing unit in the second embodiment of the present technology.

[0047] Figure 25 It is a timing diagram showing an example of the operation of a solid-state imaging device in the second embodiment of the present technology.

[0048] Figure 26 It is a timing diagram showing an example of the operation of a solid-state imaging device when masking a current signal in the second embodiment of the present technology.

[0049] Figure 27 It is a flowchart showing an example of the operation of pixels in the second embodiment of the present technology.

[0050] Figure 28 It is a circuit diagram showing an example of the configuration of a simultaneous reaction number detection circuit in the third embodiment of the present technology.

[0051] Figure 29 It is a circuit diagram showing an example of the configuration of pixels in the fourth embodiment of the present technology.

[0052] Figure 30 It is a circuit diagram showing an example of the configuration of a pixel array unit in the fifth embodiment of the present technology.

[0053] Figure 31 It is a block diagram showing an example of the configuration of an analog-to-digital conversion unit in the fifth embodiment of the present technology.

[0054] Figure 32 It is a block diagram showing an example of the configuration of a simultaneous reaction number detection unit in the fifth embodiment of the present technology.

[0055] Figure 33 It is a timing chart showing an operation example of the solid-state imaging device in the fifth embodiment of the present technology.

[0056] Figure 34 It is a flowchart showing an operation example of the pixel in the fifth embodiment of the present technology.

[0057] Figure 35 It is a block diagram showing a configuration example of the simultaneous reaction number detection circuit in the sixth embodiment of the present technology.

[0058] Figure 36 It is a block diagram showing an example of the schematic configuration of the vehicle control system.

[0059] Figure 37 It is an explanatory diagram showing an example of the installation positions of the vehicle external information detection unit and the imaging unit. Detailed Description of the Invention

[0060] The following is a description of the modes for carrying out the present technology (these modes will hereinafter be referred to as embodiments). The description will be made in the following order.

[0061] 1. First Embodiment (Example in which a plurality of pixels are commonly connected to a signal line)

[0062] 2. Second Embodiment (Example in which a plurality of pixels are commonly connected to a signal line and masking processing is performed)

[0063] 3. Third Embodiment (Example in which a plurality of pixels are commonly connected to a signal line and a sample-and-hold circuit is provided)

[0064] 4. Fourth Embodiment (Example in which a plurality of pixels are commonly connected to a signal line and differential amplification is performed)

[0065] 5. Fifth Embodiment (Example in which a plurality of pixels are commonly connected to a signal line and a voltage signal is transmitted)

[0066] 6. Sixth Embodiment (Example in which a plurality of pixels are commonly connected to a signal line and a conversion rate is obtained)

[0067] 7. Mobile Body Application Example

[0068] <1. First Embodiment>

[0069] [Configuration Example of the Distance Measurement Module]

[0070] Figure 1FIG. 0 is a block diagram showing a configuration example of the distance measurement module 100 in an embodiment of the present technology. The distance measurement module 100 is an electronic device that measures distance by the ToF method, and includes a light emitting unit 110, a control unit 120, and a solid-state imaging element 200. Note that the distance measurement module 100 is an example of the electronic device described in the claims.

[0071] The light emitting unit 110 intermittently emits irradiation light to irradiate an object. For example, the light emitting unit 110 generates irradiation light in synchronization with a square wave synchronization signal. In addition, for example, a light emitting diode is used as the light emitting unit 110, and near-infrared light or the like is used as the irradiation light. Note that the motion signal is not limited to a square wave as long as the motion signal is a periodic signal. For example, the synchronization signal may be a sine wave. In addition, the irradiation light is not limited to near-infrared light and may be visible light or the like.

[0072] The control unit 120 controls the light emitting unit 110 and the solid-state imaging element 200. The control unit 120 generates a synchronization signal and supplies the synchronization signal to the light emitting unit 110 and the solid-state imaging element 200 via signal lines 128 and 129. For example, the frequency of the synchronization signal is 20 megahertz (MHz). Note that the frequency of the synchronization signal is not limited to 20 megahertz (MHz) and may be 5 megahertz (MHz) or the like.

[0073] The solid-state imaging element 200 receives the reflected light with respect to the intermittently irradiated light and measures the distance to the object by the ToF method. The solid-state imaging element 200 generates distance measurement data indicating the measured distance and outputs the distance measurement data to the outside.

[0074] [Configuration Example of Solid-State Imaging Element]

[0075] Figure 2 FIG. 16 is a diagram showing an example of a stacked structure of the solid-state imaging element 200 in an embodiment of the present technology. The solid-state imaging element 200 includes a light receiving chip 201 and a logic chip 202 stacked on the light receiving chip 201. Signal lines for transmitting signals are provided between these chips.

[0076] [Configuration Example of Light Receiving Chip]

[0077] Figure 3 FIG. 23 is a plan view showing a configuration example of the light receiving chip 201 in an embodiment of the present technology. The light receiving chip 201 is provided with a light receiving unit 210, and the light receiving unit 210 is provided with a plurality of light receiving circuits 220 in a two-dimensional dot matrix pattern. Details of the light receiving circuit 220 will be described later.

[0078] [Configuration Example of Logic Chip]

[0079] Figure 4It is a block diagram showing a configuration example of the logic chip 202 in an embodiment of the present technology. In the logic chip 202, an analog circuit accessory 230, a current signal generation unit 240, a current-voltage conversion unit 260, an analog-to-digital conversion unit 270, and a signal processing unit 290 are arranged.

[0080] The analog circuit accessory 230 controls the operations of the analog-to-digital conversion unit 270 and the signal processing unit 290. For example, the analog circuit accessory 230 provides a bias voltage, a bias current, a clock signal, etc.

[0081] The current signal generation unit 240 generates a current signal according to the number of photons incident on the light receiving unit 210. The current signal generation unit 240 supplies the current signal to the current-voltage conversion unit 260.

[0082] The current-voltage conversion unit 260 converts the current signal into a voltage signal and outputs the voltage signal to the analog-to-digital conversion unit 270.

[0083] The analog-to-digital conversion unit 270 converts the voltage signal into a digital signal indicating the number of incident photons. The analog-to-digital conversion unit 270 supplies the digital signal to the signal processing unit 290.

[0084] The signal processing unit 290 processes the digital signal synchronously with the synchronization signal from the control unit 120 and generates ranging data.

[0085] [Configuration example of the current signal generation unit]

[0086] Figure 5 It is a block diagram showing a configuration example of the current signal generation unit 240 in the first embodiment of the present technology. A plurality of circuit blocks 241 are arranged in the current signal generation unit 240. A plurality of current supply circuits 250 are arranged in each circuit block 241. For example, in the circuit block 241, the current supply circuits 250 of four rows × four columns are arranged in a two-dimensional dot matrix pattern. The current supply circuits 250 are provided to the respective light receiving circuits 220 of the light receiving chip 201 and are connected to the corresponding light receiving circuits 220 via signal lines. A circuit including one of the light receiving circuits 220 and one of the current supply circuits 250 corresponding to the light receiving circuit 220 is used to generate ranging data for one pixel in the ranging image.

[0087] [Configuration example of the pixel]

[0088] Figure 6A circuit diagram showing an example configuration of a pixel 305 in a first embodiment of the present technology. A circuit including a light-receiving circuit 220 and a corresponding current supply circuit 250 in a light-receiving chip 201 serves as one pixel 305. In addition, four rows by four columns of current supply circuits 250 in a circuit block 241 are commonly connected to a signal line 249-j (j is an integer). The signal line 249-j serves as a bus for transmitting signals from each current supply circuit 250.

[0089] The light-receiving circuit 220 includes a resistor 221 and a photoelectric conversion element 222. The resistor 221 and the photoelectric conversion element 222 are connected in series between a power supply terminal and a ground terminal.

[0090] The photoelectric conversion element 222 performs photoelectric conversion on incident light and outputs a photocurrent. The cathode of the photoelectric conversion element 222 is connected to a terminal of the power supply potential via the resistor 221, and the anode is connected to a terminal having a potential lower than the power supply potential (such as a ground terminal). As a result, a reverse bias is applied to the photoelectric conversion element 222. In addition, the photocurrent flows in a direction from the cathode to the anode of the photoelectric conversion element 222.

[0091] As the photoelectric conversion element 222, for example, an avalanche photodiode is used, which can detect the presence or absence of the incidence of a single photon by amplifying the photocurrent. In addition, it is desirable to use a SPAD in the avalanche diode.

[0092] One end of the resistor 221 is connected to a terminal of the power supply potential, and the other end is connected to the cathode of the photoelectric conversion element 222. Whenever a photon is incident, a photocurrent flows through the resistor 221, and the cathode potential COUT of the photoelectric conversion element 222 drops to a value lower than the power supply potential.

[0093] When the cathode potential of the photoelectric conversion element 222 drops (in other words, a photon is incident), the current supply circuit 250 supplies a current signal to the current-voltage conversion unit 260 via the signal line 249-j. The current supply circuit 250 includes an inverter 251, a monostable multivibrator 252, and a transistor 253. As the transistor 253, for example, an n-channel metal oxide semiconductor (nMOS) transistor is used.

[0094] The inverter 251 inverts the signal of the cathode potential COUT and supplies the inverted signal to the monostable multivibrator 252.

[0095] The monostable multivibrator 252 outputs a pulse signal MMOUT having a predetermined pulse width to the transistor 253 according to the high-level inverted signal from the inverter 251. Note that the circuit including the inverter 251 and the monostable multivibrator 252 is an example of the first pulse signal generation unit described in the claims.

[0096] The transistor 253 generates a current signal based on the pulse signal MMOUT and supplies the current signal to the signal line 249-j.

[0097] Note that the pixel 305 generates a pulse signal through the inverter 251 and the monostable multivibrator 252, but is not limited to having such a configuration. The pixel 305 may also generate a pulse signal only through the inverter 251.

[0098] Figure 7 is a plan view showing an example of wiring in the pixel array unit 300 in the first embodiment of the present technology. In the pixel array unit 300, a plurality of pixels 305 are arranged in a two-dimensional dot matrix pattern. In addition, the pixel array unit 300 is divided into a plurality of pixel blocks 301, and each pixel block 301 includes four rows × four columns of pixels 305. In addition, the signal line 249-j is wired in the vertical direction in the column j of the pixel 305.

[0099] Each signal line 249-j is connected to the pixels 305 in different pixel blocks 301 from each other. For example, one of the pixel blocks 301 including the first to fourth rows is set as PB1, and one of the pixel blocks 301 including the fifth to eighth rows is set as PB2. One of the pixel blocks 301 including the ninth to twelfth rows is set as PB3, and one of the pixel blocks 301 including the thirteenth to sixteenth rows is set as PB4. At this time, the pixel block PB1 is connected to the signal line 249-4, and the pixel block PB2 is connected to the signal line 249-3. In addition, the pixel block PB3 is connected to the signal line 249-2, and the pixel block PB4 is connected to the signal line 249-1. The signal lines 249-5 and subsequent lines are similarly connected to different pixel blocks 301 from each other.

[0100] Sixteen pixels 305 in one of the pixel blocks 301 corresponding to the signal line 249-j are commonly connected to the signal line 249-j. In addition, each signal line 249-j is connected to the current-voltage conversion unit 260.

[0101] With the connection configuration illustrated in the figure, the 16 pixels 305 in each pixel block 301 supply a current signal to the signal line 249-j to which the 16 pixels 305 are commonly connected. Among these pixels 305, in the case where two or more pixels 305 are incident with photons substantially simultaneously, the current signals generated by the two or more pixels 305 are combined in the signal line 249-j and input to the current-voltage conversion unit 260. The current-voltage conversion unit 260 converts the current signal into a voltage signal for each column through a resistor or the like. As a result, a voltage signal whose level depends on the number of photons incident substantially simultaneously is generated.

[0102] [Configuration Example of Analog-to-Digital Conversion Unit]

[0103] Figure 8 is a block diagram showing a configuration example of the analog-to-digital conversion unit 270 in the first embodiment of the present technology. The analog-to-digital conversion unit 270 includes a plurality of zero-current confirmation circuits 271, a plurality of time-to-digital converters 272, and a plurality of simultaneous reaction number detection circuits 280. The zero-current confirmation circuits 271, the time-to-digital converters 272, and the simultaneous reaction number detection circuits 280 are arranged for each column and are commonly connected to the signal line 249-j of the corresponding column.

[0104] The zero-current confirmation circuit 271 confirms whether the current flowing through the corresponding signal line 249-j is zero, in other words, confirms whether a current signal is output via the signal line 249-j. The zero-current confirmation circuit 271 provides the confirmation result to the time-to-digital converter 272.

[0105] When it is confirmed that the corresponding signal line 249-j has zero current, the time-to-digital converter 272 converts the elapsed time from the light emission timing of the light emitting unit 110 to the cathode potential drop into a digital value. In addition, the time-to-digital converter 272 provides the converted digital value to the simultaneous reaction number detection circuit 280 and the signal processing unit 290.

[0106] The simultaneous reaction number detection circuit 280 detects the number of photons that are incident on the corresponding pixel block 301 substantially simultaneously as the number of simultaneous reactions based on the voltage signal from the signal line 249-j and the digital value from the time-to-digital converter 272. Here, "substantially simultaneously" means a case where the incident timings of a plurality of photons are completely simultaneous, or a case where the incident timings are not completely simultaneous, but there is only a time difference in which partial pulse periods of the corresponding pulse signals overlap each other. The simultaneous reaction number detection circuit 280 provides a digital signal indicating the detection result to the signal processing unit 290.

[0107] The signal processing unit 290 generates a histogram for each pixel block 301 based on the detection results from the analog-to-digital conversion unit 270. The histogram represents the detection frequency at each timing when the number of simultaneous reactions is detected. In addition, as the number of simultaneous reactions increases, the detection frequency is weighted with a larger weight. Then, the signal processing unit 290 detects the timing of the peak of the histogram as the incident timing of the reflected light, and converts the round-trip time from the irradiation timing of the irradiation light to the incident timing of the reflected light into the distance to the object.

[0108] [Configuration Example of Simultaneous Reaction Number Detection Circuit]

[0109] Figure 9It is a circuit diagram showing a configuration example of the simultaneous reaction number detection circuit 280 in the first embodiment of the present technology. The simultaneous reaction number detection circuit 280 includes a peak hold circuit 281, an analog-to-digital converter (ADC) 285, and a logic circuit 286.

[0110] The peak hold circuit 281 holds the peak of the voltage signal transmitted via the corresponding signal line 249-j. The peak hold circuit 281 includes an nMOS transistor 282, a capacitor 283, and a reset switch 284.

[0111] The nMOS transistor 282 and the capacitor 283 are inserted in series between the power supply terminal and the ground terminal. The gate of the nMOS transistor 282 is connected to the corresponding signal line 249-j. In addition, the connection point between the nMOS transistor 282 and the capacitor 283 is connected to the reset switch 284 and the ADC 285.

[0112] The reset switch 284 initializes the charge amount of the capacitor 283 under the control of the logic circuit 286.

[0113] The ADC 285 converts the potential at the connection point between the nMOS transistor 282 and the capacitor 283 into a digital signal and provides the digital signal to the logic circuit 286.

[0114] The logic circuit 286 detects the number of simultaneous reactions based on the digital value indicated by the ADC 285 (i.e., the voltage value of the voltage signal). For example, in the case where up to 16 simultaneous reactions are detected, 16 thresholds THk (k is an integer from 1 to 16) are preset, and when the voltage value is less than THk, the voltage value is converted to k, etc. The logic circuit 286 provides the detected number of simultaneous reactions to the signal processing unit 290.

[0115] In addition, when the digital value TDCOUT from the time-to-digital converter 272 is a predetermined value (e.g., "1"), the logic circuit 286 controls the reset switch 284 to initialize the capacitor 283. As a result, the peak of the voltage signal within the elapsed time measured by the time-to-digital converter 272 is held in the peak hold circuit 281.

[0116] Figure 10 It is a diagram showing a configuration example of the pixel array unit 300, the current-voltage conversion unit 260, and the analog-to-digital conversion unit 270 in the first embodiment of the present technology. The current-voltage conversion unit 260 and the analog-to-digital conversion unit 270 function as a photon number detection unit 306 for detecting the number of simultaneous reactions.

[0117] The pixel array unit 300 is provided with a pixel block 301 in which a plurality of pixels 305 are arranged and signal lines 249-j to which the pixels 305 are commonly connected. Each of the pixels 305 generates a current signal as an analog signal according to the incidence of photons. The photon number detection unit 306 detects the number of photons (i.e., the number of simultaneous responses) that are incident on the pixel block 301 substantially simultaneously based on the analog signal (i.e., the current signal).

[0118] The current-voltage conversion unit 260 in the photon number detection unit 306 converts the current signal into a voltage signal. In addition, the analog-to-digital conversion unit 270 in the photon number detection unit 306 converts the voltage signal into the number of simultaneous responses.

[0119] In addition, the zero current confirmation circuit 271 in the analog-to-digital conversion unit 270 confirms whether a current signal is output. In the case where no current is output, the time-to-digital converter 272 in the analog-to-digital conversion unit 270 converts the elapsed time from the light emission timing to the cathode potential drop into a digital value. The simultaneous response number detection circuit 280 in the analog-to-digital conversion unit 270 detects the number of simultaneous responses based on the digital value and the voltage signal.

[0120] Here, a comparative example in which signal lines are individually wired to the photon number detection unit 306 for each pixel 305 is assumed. In the comparative example, as the pixels 305 are miniaturized, the number of wirings of the signal lines between the pixels 305 and the photon number detection unit 306 increases. When the number of wirings increases, the signal lines need to be thinned, making it difficult to ensure the transmission bandwidth. In addition, due to the increase in the number of wirings, the degree of freedom in designing the wirings is reduced and the skew increases. As described above, it becomes difficult to miniaturize the pixels due to the increase in the number of wirings.

[0121] On the other hand, in a configuration in which the signal lines 249-j are shared by a plurality of pixels 305, an increase in the number of wirings can be suppressed, thereby promoting the miniaturization of the pixels.

[0122] Figure 11 is a timing chart showing an operation example of the solid-state imaging device 200 in the first embodiment of the present technology. For 16 pixels 305 in the pixel block 301, cathode potentials COUT_1 to COUT_16 are set, and pulse signals MMOUT_1 to MMOUT_16 are set.

[0123] Assume that the cathode potential COUT_1 decreases with the incidence of photons immediately before the timing T0, and the cathode potential COUT_2 decreases with the incidence of photons immediately before the timing T1. In this case, a pulse signal MMOUT_1 with a pulse width from the timing T0 to the timing T2 is generated, and immediately thereafter, a pulse signal MMOUT_2 with a pulse width from the timing T1 to the timing T3 is generated. Then, immediately after the timing T1, a current signal of two photon levels is output via the signal line 249-j. At the same time, the coincidence number detection circuit 280 detects "2" as the coincidence number based on the peak value of the current signal.

[0124] When it is confirmed that the current is zero after the timing T3, the time-to-digital converter 272 is initialized. Then, immediately before the timing T4, assume that the cathode potential COUT_16 decreases according to the incidence of photons. In this case, a pulse signal MMOUT_16 with a pulse width from the timing T4 to the timing T5 is generated, and immediately after the timing T4, a current signal of one photon level is output via the signal line 249-j. The coincidence number detection circuit 280 detects "1" as the coincidence number based on the peak value of the current signal.

[0125] Figure 12 It is a diagram showing an example of a histogram in the first embodiment of the present technology. The signal processing unit 290 generates a histogram based on the detection results of a predetermined number of coincidences for the pixel block 301.

[0126] Assume that four pixels are arranged in the pixel block 301. In this case, "0" to "4" are detected as the number of coincidences. In the figure, the vertical axis represents the detection frequency of the number of coincidences, and the horizontal axis represents the detection time. The larger the number of coincidences, the larger the weighted value of the detection frequency. For example, when the weight of the detection frequency with the number of coincidences being "1" is "w" (w is a real number), the weight of the detection frequency with the number of coincidences being "4" is set to "4w".

[0127] Here, assume a comparative example where the number of photons incident on the pixel block 301 substantially simultaneously is not detected, and it is detected whether photons are incident on each pixel.

[0128] Figure 13 It is a diagram showing a histogram of the comparative example. Comparison Figure 12 and Figure 13, when the number of simultaneous reactions of multiple photons is detected, the peak of the histogram is more obvious than the peak of the comparison example. This is because, for example, in the case where four photons are incident simultaneously, when the number of simultaneous reactions is detected, all four photons can be detected, while in the comparison example, only one of the four photons can be detected. Therefore, the detection accuracy of the histogram peak is improved by detecting the number of simultaneous reactions, and the ranging accuracy can be improved by improving the detection accuracy.

[0129] [Operation example of solid-state imaging element]

[0130] Figure 14 is a flowchart showing an operation example of pixel 305 in the first embodiment of the present technology. For example, when a predetermined application program for performing distance measurement is executed, this operation starts. First, pixel 305 determines whether the cathode potential of the photoelectric conversion element 222 has decreased (in other words, whether photons have been incident) (step S901). In the case where the cathode potential has decreased (step S901: Yes), pixel 305 generates a current signal and transmits the current signal via the signal line (step S902). In the case where the cathode potential has not decreased (step S901: No), or after step S902, pixel 305 repeatedly executes step S901 and subsequent steps.

[0131] Figure 15 is a flowchart showing an operation example of the analog-to-digital conversion unit 270 in the first embodiment of the present technology. For example, when a predetermined application program for performing distance measurement is executed, this operation starts. The analog-to-digital conversion unit 270 determines whether zero current is confirmed (step S951).

[0132] In the case where zero current is confirmed (step S951: Yes), the analog-to-digital conversion unit 270 performs time-to-digital conversion processing (step S952) and detects the number of simultaneous reactions (step S953). In the case where zero current is not confirmed (step S951: No), or after step S953, the analog-to-digital conversion unit 270 repeatedly executes step S951 and subsequent steps.

[0133] As described above, in the first embodiment of the present technology, the analog-to-digital conversion unit 270 detects the number of simultaneous reactions based on the current signal transmitted via the signal line 249-j commonly connected to multiple pixels 305, so there is no need to wire signal lines for each pixel. As a result, compared with the case of wiring signal lines for each pixel, the number of wirings can be reduced, and the miniaturization of pixels can be promoted.

[0134] [Modification example]

[0135] In the above first embodiment, pixels 305 are arranged in a four-row × four-column pattern in pixel block 301. However, in this configuration, the number of distance measurement points (i.e., resolution) per unit area may be insufficient. The solid-state imaging device 200 according to a modified example of the first embodiment is different from the first embodiment in that the number of pixels in pixel block 301 is reduced to improve the resolution.

[0136] Figure 16 FIG. is a plan view showing an example of a pixel block 301 in which one column or one row of pixels is arranged in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which four rows × one column of pixels 305 are arranged. In the figure, b is an example of a pixel block 301 in which two rows × one column of pixels 305 are arranged. In the figure, c is an example of a pixel block 301 in which one row × four columns of pixels 305 are arranged.

[0137] Figure 17 FIG. is a plan view showing an example of a pixel block 301 in which two rows × two columns of pixels are arranged in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which two rows × two columns of pixels 305 are arranged and signal lines are wired in a fishbone shape. In the figure, b is an example of a pixel block 301 in which two rows × two columns of pixels 305 are arranged and signal lines are wired in an H shape.

[0138] Figure 18 FIG. is a plan view showing an example of a pixel block 301 in which three rows × two columns and three rows × three columns of pixels are arranged in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which three rows × two columns of pixels 305 are arranged and signal lines are wired in an H shape. In the figure, b is an example of a pixel block 301 in which three rows × three columns of pixels 305 are arranged and signal lines are wired in a fishbone shape.

[0139] As Figures 16 to 18 illustrated, by reducing the number of pixels to less than four rows × four columns, the number of distance measurement points (resolution) in the horizontal and vertical directions can be increased.

[0140] Figure 19 FIG. is a plan view showing an example of a pixel block 301 arranged in a four-row × four-column pattern in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which signal lines are wired in an H shape, and b in the figure is an example of a pixel block 301 in which signal lines are wired in a fishbone shape. When the number of pixels is not reduced, as illustrated in the figure, the wiring can be made in an H shape or in a fishbone shape.

[0141] Figure 20It is a plan view showing an example of pixel blocks 301 arranged in a staggered manner in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which 8 pixels 305 are arranged in a staggered manner, and in the figure, a is an example of a pixel block 301 in which 16 pixels 305 are arranged in a staggered manner. As illustrated in the figure, the pixels 305 can be arranged in a staggered manner.

[0142] Figure 21 It is a plan view showing an example of pixel blocks 301 arranged in a hexagonal shape in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which one of the seven pixels 305 is the center, and the remaining six pixels are arranged in a hexagonal shape and wired in a fishbone shape. In the figure, b is an example of a pixel block 301 in which one of the seven pixels 305 is the center, and the remaining six pixels are arranged in a hexagonal shape and radially wired. As illustrated in the figure, the pixels 305 can be arranged in a hexagonal shape.

[0143] Figure 22 It is a plan view showing an example of pixel blocks 301 in which each pixel is hexagonal in a modified example of the first embodiment of the present technology. In the figure, a is an example of a pixel block 301 in which one of the seven hexagonal pixels 305 is the center, and the remaining six pixels are arranged in a hexagonal shape and wired in a fishbone shape. In the figure, b is an example of a pixel block 301 in which one of the seven hexagonal pixels 305 is the center, and the remaining six pixels are arranged in a hexagonal shape and radially wired. The pixels 305 can have a rectangular shape or a hexagonal shape as illustrated in the figure.

[0144] As described above, according to the modified example of the first embodiment of the present technology, since the number of pixels in the pixel block 301 is reduced, the resolution can be improved.

[0145] <2. Second Embodiment>

[0146] In the above first embodiment, the analog-to-digital conversion unit 270 detects the number of simultaneous reactions; however, when photons newly enter during a period in which the photons maintain linearity between the photon number and the current signal level, an error detection may occur. The solid-state imaging element 200 of the second embodiment is different from the solid-state imaging element of the first embodiment in that an error detection is suppressed by masking the provided current signal during a masking period in which linearity is maintained.

[0147] Figure 23This is a circuit diagram showing an example configuration of pixel 305 in the second embodiment of the present technology. Pixel 305 differs from pixel 305 in the first embodiment in that a pulse shaping unit 320 and a masking processing unit 330 are further provided in the current supply circuit 250. In addition, signal lines 259-j are further wired for each pixel block 301, and each masking processing unit 330 in the pixel block 301 is commonly connected to the signal line 259-j. A masking signal MSK is transmitted via the signal line 259-j.

[0148] Figure 24 This is a circuit diagram showing an example configuration of the pulse shaping unit 320 and the masking processing unit 330 in the second embodiment of the present technology. The pulse shaping unit 320 includes an inverter 321 and an AND (logical product) gate 322. The masking processing unit 330 includes a resistor 331, an nMOS transistor 332, an AND gate 333, switches 334, 335, and 337, and a NOR (negative OR) gate 336. Note that the number of inverters 321 in the pulse shaping unit 320 is not limited to one as long as it is odd.

[0149] The inverter 321 inverts the inverted signal from the inverter 251 and supplies the inverted signal to the AND gate 322. The AND gate 322 supplies the logical product of the inverted signal from the inverter 251 and the signal from the inverter 321 to the AND gate 333 and the monostable multivibrator 252 as a pulse signal A1'.

[0150] In the masking processing unit 330, the AND gate 333 outputs the logical product of the pulse signal A1' from the AND gate 322 and the masking signal MSK to the switches 334 and the NOR gate 336 as a pulse signal A1. In addition, the resistor 331 and the nMOS transistor 332 are connected in series between the power supply terminal and the ground terminal.

[0151] The monostable multivibrator 252 in the second embodiment supplies a pulse signal B1 to the gate of the nMOS transistor 332, the switches 335, and the NOR gate 336.

[0152] The switch 334 opens and closes the path between the power supply terminal and the switch 337 according to the pulse signal A1. The switch 335 opens and closes the path between the terminal of the bias voltage V bias and the connection point between the switches 334 and 337 according to the pulse signal B1. The connection point is connected to the gate of the transistor 253. The NOR gate 336 supplies a control signal C1, which is the negative OR of the pulse signal A1 and the pulse signal B1, to the switch 337. The switch 337 opens and closes the path between the switch 334 and the ground terminal according to the control signal C1.

[0153] In the circuit configuration illustrated in the figure, the pulse shaping unit 320 generates a pulse signal A1 having a pulse width shorter than that of the pulse signal generated by the monostable multivibrator 252 in the subsequent stage, based on the inverted signal from the inverter 251. The pulse width of the pulse signal A1 is adjusted by the number of inverters 321. Note that the pulse shaping unit 320 is an example of the second pulse signal generation unit in the claims. Further, the masking processing unit 330 supplies a low-level masking signal MSK to the signal line 259-j during a specific masking period after the generation and fall of the pulse signal A1. The masking period corresponds to the period during which the pulse signal B1 or the like is at a high level. During the masking period, even if a new pulse signal A1 is generated, the masking processing unit 330 keeps the transistor 253 in the off state and masks the output of the current signal. Note that the circuit of the pulse shaping unit 320 is not limited to the circuit illustrated in the figure, as long as it can generate a pulse signal having a shorter pulse width than that of the monostable multivibrator 252 in the subsequent stage. For example, a monostable multivibrator may also be arranged in the pulse shaping unit 320.

[0154] Note that the resistor 331 and the nMOS transistor 332 are arranged for each pixel 305, but the present invention is not limited to this configuration. It is also possible to have a configuration in which each of the resistor 331 and the nMOS transistor 332 is arranged in the pixel block 301 and shared by all the pixels in the pixel block 301.

[0155] Figure 25 is a timing chart showing an operation example of the solid-state imaging device 200 in the second embodiment of the present technology.

[0156] Assume that the cathode potential COUT_1 decreases with the incidence of photons immediately before the timing T0, and the cathode potential COUT_2 decreases with the incidence of photons immediately before the timing T1. In this case, the rising of the inverted signal is detected at the timing T0, and the pulse signal A1' is generated. Further, the pulse signal A2' is generated at the timing T1. After the pulse signal A2' falls, the masking signal MSK is controlled to a low level during the masking period from the timing T2 to the timing t3. The masking period corresponds to the period during which either the pulse signal B1 or B2 is at a high level. It is assumed that no new photons are incident during this pulse period.

[0157] Further, the pulse signals A1 and A2 are generated at the timings T0 and T1, respectively, so as to transmit the current signal. The number of simultaneous reactions is detected based on the current signal.

[0158] Then, when the pulse signal A16' is generated at the timing T3 after the masking period, the masking signal MSK is controlled to a low level during the masking period from the timing T4 to the timing t5.

[0159] As illustrated in the figure, in the case where no new photons are incident during the masking period, the unmasked current signal is not masked, and the number of simultaneous reactions is detected from the current signal as in the first embodiment.

[0160] Figure 26 is a timing chart showing an operation example of the solid-state imaging device when masking the current signal in the second embodiment of the present technology.

[0161] It is assumed that the cathode potential COUT_1 decreases with the incidence of photons immediately before timing T0, and the cathode potential COUT_2 decreases with the incidence of photons immediately before timing T1. It is assumed that the cathode potential COUT_16 decreases with the incidence of photons before a later timing T3. In this case, the rising of the inverted signal is detected at timing T0, and the pulse signal A1' is generated. In addition, the pulse signal A2' is generated at timing T1, and the pulse signal A3' is generated at timing t3.

[0162] In addition, after detecting the fall of the signal A2', during the masking period from timing T2 to timing t4, the masking signal MSK is controlled to a low level. The masking period corresponds to the period during which any one of the pulse signals B1, B2, and B16 is at a high level.

[0163] In the figure, light is incident during the masking period, and the pulse signal A16' is generated. In this case, the masking processing unit 330 causes the corresponding pulse signal A16 to disappear according to the low-level masking signal MSK. As a result, the output of the current signal corresponding to the pulse signal A16 is masked.

[0164] In addition, pulse signals A1 and A2 are generated at timings T0 and T1, respectively, to transmit the current signal. The number of simultaneous reactions is detected based on the current signal. Here, during the period from the rising to the falling of the pulse signal A1, there is no linear relationship between the number of photons incident substantially simultaneously and the level of the current signal, but a linear relationship is maintained after this period has passed. Therefore, in the first embodiment where the current signal is not masked, when new photons are incident during the period of maintaining linearity, there is a possibility of detecting an incorrect number of simultaneous reactions due to fluctuations in the current signal dependent on the new photons. On the other hand, in the second embodiment, as shown in the figure, since the new current signal is masked during the masking period of maintaining linearity, the number of simultaneous reactions can be accurately detected.

[0165] Figure 27 is a flowchart showing an operation example of the pixel 305 in the second embodiment of the present technology. The pixel 305 in the second embodiment is different from the pixel 305 in the first embodiment in that step S903 is further performed. When the cathode potential decreases (step S901: Yes), the pixel 305 refers to the masking signal MSK and determines whether it is within the masking period (step S903).

[0166] When it is not within the masking period (step S903: No), pixel 305 generates a current signal and transmits the current signal via the signal line (step S902). When it is within the masking period (step S903: Yes), or after step S902, pixel 305 repeatedly executes step S901 and subsequent steps.

[0167] As described above, according to the second embodiment of the present technology, since the masking processing unit 330 masks the new current signal during the masking period that maintains linearity between the number of photons and the current signal level, false detection of the number of simultaneous responses can be suppressed.

[0168] <3. Third Embodiment>

[0169] In the second embodiment described above, the masking processing unit 330 masks the current signal during the masking period, but does not mask the current signal during the pulse period of pulse signal B16 corresponding to pulse signal B16 after pulse signal B2. Therefore, the level of signal line 249-j may fluctuate during this period. The solid-state imaging device 200 of the third embodiment is different from the solid-state imaging device of the second embodiment in that the influence of the fluctuation of the current signal during the unmasked period is suppressed by providing a sample-and-hold circuit.

[0170] Figure 28 FIG. is a circuit diagram showing a configuration example of the simultaneous response number detection circuit 280 in the third embodiment of the present technology. The simultaneous response number detection circuit 280 of the third embodiment is different from that of the second embodiment in that a sample-and-hold circuit 310 is provided instead of the peak-hold circuit 281.

[0171] The sample-and-hold circuit 310 receives a voltage signal from the current-voltage conversion unit 260 at a predetermined timing and holds the voltage signal as a hold value. The sample-and-hold circuit 310 includes a sampling switch 311 and a capacitor 312.

[0172] The sampling switch 311 opens and closes the path between the signal line 249-j and the ADC 285 under the control of the logic circuit 286. The capacitor 312 is inserted between the path between the sampling switch 311 and the ADC 285 and the ground terminal. Note that the circuit configuration of the sample-and-hold circuit 310 is not limited to the circuit configuration illustrated in the figure. For example, a circuit that performs bottom plate sampling may be provided.

[0173] The logic circuit 286 detects the number of simultaneous responses based on the held value. Further, for example, when the digital value TDCOUT from the time-to-digital converter 272 is a predetermined value (e.g., "1"), the logic circuit 286 controls the sampling switch 311 so that the voltage signal is received (i.e., sampled). As a result, since the voltage signal in the subsequent pulse period of the pulse signal B16 is not sampled, the held value does not fluctuate even if the current signal fluctuates in the pulse period. As a result, false detection due to fluctuations in the current signal can be suppressed.

[0174] As described above, in the third embodiment of the present technology, since the sample-and-hold circuit 310 receives and holds the voltage signal at a predetermined timing, the held value does not fluctuate even if the current signal fluctuates thereafter. As a result, false detection due to fluctuations in the current signal can be suppressed.

[0175] <4. Fourth Embodiment>

[0176] In the first embodiment described above, the current signal is transmitted through one signal line 249-j for each pixel block 301. However, as the signal line becomes longer, the wiring resistance increases, and the signal level may decrease. The solid-state imaging device 200 of the fourth embodiment is different from that of the first embodiment in that a pair of differential signals obtained by transmitting a differential amplified pulse signal and its inverted signal is transmitted.

[0177] Figure 29 is a circuit diagram showing a configuration example of the pixel 305 in the fourth embodiment of the present technology. The pixel 305 of the fifth embodiment is different from the pixel 305 of the first embodiment in that it includes an inverter 256, differential transistors 254 and 255, and a current source 257 instead of the transistor 253.

[0178] Further, in the fourth embodiment, in addition to the signal line 249-j for each pixel block 301, a signal line 248-j is also wired. A plurality of pixels 305 in the pixel block 301 are commonly connected to this pair of signal lines.

[0179] The monostable multivibrator 252 of the fourth embodiment supplies a pulse signal to the gates of the differential transistor 254 and the inverter 256. The inverter 256 inverts the pulse signal and supplies the inverted pulse signal to the gate of the differential transistor 255.

[0180] The differential transistor 254 is inserted between the signal line 248-j and the current source 257, and the differential transistor 255 is inserted between the signal line 249-j and the current source 257. The current source 257 supplies a constant current.

[0181] A circuit including differential transistors 254 and 255 and a current source 257 serves as a differential amplifier circuit that differentially amplifies a pulse signal and its inverted signal. Then, this pair of differential signals is provided as current signals to the current-voltage conversion unit 260 via signal lines 248-j and 249-j. As described above, by transmitting this pair of differentially amplified differential signals, compared with the case of transmitting differential signals without differential amplification, a reduction in signal level due to an increase in wiring resistance can be suppressed.

[0182] Note that the third embodiment can also be applied to the fourth embodiment.

[0183] As described above, according to the fourth embodiment of the present technology, since the pixel 305 transmits this pair of differentially amplified differential signals, a reduction in signal level due to an increase in wiring resistance can be suppressed compared with the case where differential amplification is not performed.

[0184] <5. Fifth Embodiment>

[0185] In the above-described first embodiment, each pixel 305 transmits a current signal as an analog signal, but alternatively, a voltage signal can be transmitted. The solid-state imaging device 200 of the fifth embodiment is different from the solid-state imaging device 200 of the first embodiment in that a voltage signal is transmitted.

[0186] Figure 30 It is a circuit diagram showing a configuration example of the pixel array unit 300 in the fifth embodiment of the present technology. In the pixel array unit 300 of the fifth embodiment, an nMOS transistor 361, an inverter 362, and a recharge control unit 350 are provided for each pixel block 301. In addition, in each of the pixels 305, a voltage control circuit 340 is arranged instead of the current signal supply circuit 250.

[0187] In the voltage control circuit 340, an inverter 341, a NOR gate 342, an AND gate 343, and an NMOS transistor 344 are arranged. In addition, an OR gate 351, a delay circuit 352, and a monostable multivibrator 353 are arranged in the recharge control unit 350.

[0188] The inverter 341 inverts the signal of the cathode potential COUT and provides the inverted signal INVOUT_1 to the OR gate 351 and the AND gate 343. The AND gate 343 outputs the logical product of the inverted signal from the inverter 341 and the pulse signal MMOUT from the monostable multivibrator 353 to the NOR gate 342. The NOR gate 342 provides the negative OR signal of the cathode potential COUT and the signal from the AND gate 343 to the gate of the nMOS transistor 344. The nMOS transistor 344 is inserted between the signal line 249-j and the ground terminal.

[0189] In the recharge control unit 350, an OR gate 351 supplies the logical sum of the inverted signals INVOUT_1 to INVOUT_16 from the respective pixels 305 in the pixel block 301 to a delay circuit 352. The delay circuit 352 delays the signal from the OR gate 351 and supplies the delayed signal to a monostable multivibrator 353. The monostable multivibrator 353 generates a pulse signal MMOUT based on the delayed signal from the delay circuit 352 and outputs the pulse signal MMOUT to an inverter 362 and an AND gate 343 of each pixel 305.

[0190] The inverter 362 inverts the pulse signal MMOUT and outputs the inverted signal to the gate of an nMOS transistor 361. The nMOS transistor 361 is inserted between a power supply terminal and a signal line 249-j.

[0191] In addition, in the fifth embodiment, the current-voltage conversion unit 260 is not arranged, and the signal line 249-j is connected to the analog-to-digital conversion unit 270 without passing through the current-voltage conversion unit 260.

[0192] With the configuration illustrated in the figure, the recharge control unit 350 detects the earliest rise among the inverted signals INVOUT_1 to INVOUT_16 and delays the detection result to generate the pulse signal MMOUT.

[0193] In addition, the recharge control unit 350 turns on the nMOS transistor 361 on the power supply side during the pulse period of the pulse signal MMOUT and turns off the nMOS transistor outside the pulse period to recharge the signal line 249-j (i.e., the bus). Through these controls, as the number of simultaneous reactions increases, a voltage signal whose level changes rapidly is generated as an analog signal and transmitted via the signal line 249-j.

[0194] Figure 31 is a block diagram showing a configuration example of the analog-to-digital conversion unit 270 in the fifth embodiment of the present technology. The analog-to-digital conversion unit 270 of the fifth embodiment is different from that of the first embodiment in that a zero-current confirmation circuit 271 is not arranged in each column.

[0195] In addition, a time-to-digital converter 272 converts a timing (falling, falling, etc.) synchronized with a clock signal CLK, that is, a time elapsed from the light emission timing, into a digital value.

[0196] Figure 32FIG. is a block diagram showing a configuration example of a simultaneous reaction number detection circuit 280 in a fifth embodiment of the present technology. The simultaneous reaction number detection circuit 280 of the fifth embodiment includes a plurality of frequency component extraction circuits 370 that extract mutually different frequency components and a logic circuit 380. Further, each frequency component extraction circuit 370 includes a band-pass filter 371, a peak hold circuit 372, and an ADC 373.

[0197] The band-pass filter 371 passes a corresponding frequency component in the voltage signal and supplies the frequency component to the peak hold circuit 372. The configurations of the peak hold circuit 372 and the ADC 373 are similar to the configurations of the peak hold circuit 281 and the ADC 285 in the first embodiment.

[0198] The logic circuit 380 detects the number of simultaneous reactions based on the frequency characteristics of the voltage signal. For example, when a low-frequency component having a frequency lower than a predetermined value and a high-frequency component having a frequency higher than the predetermined value are extracted, the higher the level of the high-frequency component relative to the low-frequency component, the larger the number of detected simultaneous reactions. Further, when the digital value from the time-to-digital converter 272 is a predetermined value, the logic circuit 380 initializes the peak hold circuit 372.

[0199] Figure 33 FIG. is a timing chart showing an operation example of the solid-state imaging device in the fifth embodiment of the present technology.

[0200] It is assumed that the cathode potential COUT_1 decreases with the incidence of photons immediately before the timing T0, and the cathode potential COUT_2 decreases with the incidence of photons immediately before the timing T1. Further, then, immediately before the timing T3, it is assumed that the cathode potential COUT_16 decreases according to the incidence of photons. In this case, an inverted signal INVOUT_1 is generated at the timing T0, and an inverted signal INVOUT_2 is generated at the timing T1.

[0201] Then, immediately after the timing T0, the logical sum OROUT having a high level starts to be output by the OR gate 351. Then, according to the delayed signal OROUTd obtained by delaying the logical sum OROUT, a pulse signal MMOUT having a pulse width from the timing T2 to the timing T4 is output.

[0202] Further, immediately after the timing T0, a voltage signal having a frequency characteristic corresponding to the number of simultaneous reactions is output via the signal line 249-j. After the timing T2, the signal line 249-j is recharged by the inverted signal of the pulse signal MMOUT. Further, the pulse signal MMUOT having a high level is input to the AND gate 343, thereby suppressing the generation of the inverted signal INVOUT_16 corresponding to photons that are not incident substantially simultaneously.

[0203] Figure 34It is a flowchart showing an operation example of pixel 305 in the fifth embodiment of the present technology. First, pixel 305 determines whether the cathode potential of the photoelectric conversion element 222 has decreased (in other words, whether photons have been incident) (step S901). In the case where the cathode potential has decreased (step S901: Yes), pixel 305 determines whether the photons of the pixel have been incident substantially simultaneously with the photons of another pixel (step S904). This determination is performed by AND gate 343. The fact that the output of AND gate 343 is at a high level indicates that the photons have not been incident substantially simultaneously.

[0204] In the case where the photons have been incident substantially simultaneously (step S904: Yes), pixel 305 generates a voltage signal and transmits the voltage signal via the signal line (step S905). Then, pixel 305 determines whether the recharge of signal line 249-j has been completed (step S906). In the case where the photons have not been incident substantially simultaneously (step S904: No), no voltage signal is output from pixel 305, and step S906 is executed.

[0205] In the case where the recharge has not been completed (step S906: No), pixel 305 repeats step S906. In the case where the recharge has been completed (step S906: Yes), pixel 305 repeatedly executes step S901 and subsequent steps.

[0206] As described above, in the fifth embodiment of the present technology, since pixel 305 generates a voltage signal based on the incidence of light and transmits the voltage signal, current-voltage conversion unit 260 and zero-current confirmation circuit 271 become unnecessary.

[0207] <6. Sixth Embodiment>

[0208] In the above-described fifth embodiment, for each frequency component, simultaneous reaction number detection circuit 280 has band-pass filter 371 and peak-hold circuit 372 to extract the frequency component. However, in this configuration, as the number of frequency components to be extracted increases, the number of band-pass filters 371 and the like increases, and the circuit scale of simultaneous reaction number detection circuit 280 increases. The solid-state imaging device 200 of the sixth embodiment is different from that of the fifth embodiment in that the circuit scale of simultaneous reaction number detection circuit 280 is reduced by detecting the number of simultaneous reactions based on the conversion rate.

[0209] Figure 35It is a block diagram showing a configuration example of the simultaneous reaction number detection circuit 280 in the sixth embodiment of the present technology. The simultaneous reaction number detection circuit 280 of the sixth embodiment includes comparators 391 and 392, latch circuits 393 and 394, inverters 395 and an AND gate 396. In addition, the simultaneous reaction number detection circuit 280 further includes a current source 397, a switch 398, a capacitor 399, an ADC 400, a reset switch 401, and a logic circuit 402.

[0210] Comparator 391 compares the level of the voltage signal transmitted via signal line 249-j with a predetermined upper threshold ThH. Comparator 391 outputs the comparison result to the clock terminal of latch circuit 393. Comparator 392 compares the level of the voltage signal with a lower threshold ThL that is lower than the upper threshold ThH. Comparator 392 outputs the comparison result to the clock terminal of latch circuit 394.

[0211] Latch circuit 393 holds a high level synchronously with the signal from comparator 391 and outputs the high level to inverter 395. In addition, logic circuit 402 initializes the held value of latch circuit 393 to a low level. Latch circuit 394 holds a high level synchronously with the signal from comparator 392 and outputs the high level to AND gate 396. In addition, logic circuit 402 initializes the held value of latch circuit 394 to a low level.

[0212] Inverter 395 inverts the output of latch circuit 393 and outputs the inverted output to AND gate 396. AND gate 396 outputs the logical product of the output of inverter 395 and the output of latch circuit 394 to switch 398.

[0213] Current source 397 provides a constant current. When the logical product of AND gate 396 is at a high level, switch 398 supplies the current from current source 397 to capacitor 399. On the other hand, when the logical product of AND gate 396 is at a low level, switch 398 switches the output destination of the current to the ground terminal.

[0214] Reset switch 401 initializes the charge amount of capacitor 399 under the control of logic circuit 402.

[0215] ADC 400 converts the potential at the connection point between switch 398 and capacitor 399 into a digital signal and outputs the digital signal to logic circuit 402. The potential is a value depending on the time when the voltage signal changes from one of the upper threshold ThH and the lower threshold ThL to the other.

[0216] The logic circuit 402 obtains the conversion rate based on the digital signal from the ADC 400. As described above, the digital signal (potential) of the ADC 400 indicates the time when the voltage signal changes from one of the upper threshold ThH and the lower threshold ThL to the other. Therefore, the logic circuit 402 can obtain the speed of the voltage signal level change (i.e., the conversion rate) by dividing the difference between the upper threshold ThH and the lower threshold ThL by the time indicated by the digital signal. Then, the logic circuit 402 detects the number of simultaneous responses based on the conversion rate and outputs this number to the signal processing unit 290. For example, the higher the conversion rate, the more the number of simultaneous responses detected.

[0217] In addition, the logic circuit 402 controls the reset switch 401 at a predetermined timing after detecting the number of simultaneous responses, so as to initialize the capacitor 399 and provide a reset signal to the latch circuits 393 and 394 to initialize the held value.

[0218] As illustrated in the figure, when detecting the number of simultaneous responses based on the conversion rate, it is not necessary to provide the band-pass filter 371 and the peak-holding circuit 372 for each frequency component. As a result, the circuit scale of the simultaneous response number detection circuit 280 can be reduced.

[0219] As described above, in the sixth embodiment of the present technology, since the simultaneous response number detection circuit 280 detects the number of simultaneous responses based on the conversion rate, it is not necessary to provide the band-pass filter 371 and the peak-holding circuit 372 for each frequency component. As a result, the circuit scale of the simultaneous response number detection circuit 280 can be reduced.

[0220] <7. Mobile body application example>

[0221] The technology according to the present disclosure (this technology) can be applied to various products. The technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, a robot, etc.

[0222] Figure 36 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0223] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 36In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle external information detection unit 12030, a vehicle internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio-visual output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0224] The drive system control unit 12010 controls the operation of devices related to the vehicle drive system according to various programs. For example, the drive system control unit 12010 serves as a control device for a driving force generation device (such as an internal combustion engine or a drive motor) that generates a vehicle driving force, a driving force transmission mechanism that transmits the driving force to the wheels, a steering mechanism that adjusts the vehicle steering angle, and a braking device that generates a vehicle braking force, etc.

[0225] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights (such as headlights, taillights, brake lights, turn signal lights, and fog lights). In this case, radio waves or signals from a portable device that replaces the key can be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio waves or signals and controls the vehicle door lock device, electric window device, lights, etc.

[0226] The vehicle external information detection unit 12030 detects information about the outside of the vehicle on which the vehicle control system 12000 is installed. For example, an imaging unit 12031 is connected to the vehicle external information detection unit 12030. The vehicle external information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the vehicle external information detection unit 12030 can perform object detection processing or distance detection processing on people, vehicles, obstacles, signs, characters on the road surface, etc.

[0227] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output an electrical signal as an image or as information for measuring distance. In addition, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0228] The vehicle interior information detection unit 12040 detects information about the vehicle interior. For example, the vehicle interior information detection unit 12040 is connected to the driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the vehicle interior information detection unit 12040 can calculate the fatigue level or concentration level of the driver, or determine whether the driver is drowsy, based on the detection information input from the driver state detection unit 12041.

[0229] The microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device based on the information inside or outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control with the aim of realizing the functions of an advanced driver assistance system (ADAS), including collision avoidance or collision mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed holding driving, collision warning of the vehicle, and lane departure warning of the vehicle, etc.

[0230] In addition, the microcomputer 12051 can perform cooperative control aiming at autonomous driving, which does not depend on the driver's operation, etc., by controlling the driving force generation device, the steering mechanism, the braking device, etc., based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040.

[0231] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control to achieve the purpose of preventing glare, such as switching from high beam to low beam, by controlling the headlamp according to the position of the vehicle ahead or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0232] The audio-visual output unit 12052 sends at least one of the audio and image output signals to an output device capable of notifying information visually or auditorily to the occupants in the vehicle or outside the vehicle. In Figure 36 the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are exemplified as output devices. The display unit 12062 can include, for example, at least one of an in-vehicle display and a head-up display.

[0233] Figure 37 is a diagram showing an example of the installation position of the imaging unit 12031.

[0234] In Figure 37 , imaging units 12101, 12102, 12103, 12104, and 12105 are included as imaging unit 12031.

[0235] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at positions such as the front nose, side mirrors, rear bumper, rear door, and upper part of the windshield inside the vehicle of vehicle 12100. The imaging unit 12101 disposed on the front nose and the imaging unit 12105 disposed on the upper part of the windshield inside the vehicle mainly acquire images of the front of vehicle 12100. The imaging units 12102 and 12103 disposed on the side mirrors mainly acquire images of the sides of vehicle 12100. The imaging unit 12104 disposed on the rear bumper or rear door mainly acquires images of the rear of vehicle 12100. The imaging unit 12105 disposed on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc. in front.

[0236] Note that Figure 37 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 disposed at the front nose, and imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 disposed at the side view mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 disposed at the rear bumper or rear door. For example, the image data captured by imaging units 12101 and 12104 are superimposed on each other, thereby obtaining a top view image of vehicle 12100 viewed from above.

[0237] At least one of imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element including pixels for phase difference detection.

[0238] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 obtains the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed to the vehicle 12100), thereby being able to extract the three-dimensional object that is the leading vehicle, which is particularly the three-dimensional object closest to the vehicle 12100 on the traveling path of the vehicle 12100 and traveling in a direction substantially the same as the direction of the vehicle 12100 at a predetermined speed (for example, greater than or equal to 0 km / h). In addition, the microcomputer 12051 can preset the inter-vehicle distance to be ensured in front of the leading vehicle and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. As described above, cooperative control can be performed with the aim of autonomous driving that does not depend on the operations of the driver or the like.

[0239] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can extract three-dimensional object data regarding the three-dimensional object by classifying the object into a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and other three-dimensional objects such as utility poles, and use this data for automatic obstacle avoidance of the obstacle. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to visually recognize. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is greater than or equal to the set value and there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 and the display unit 12062, or performs forced deceleration or avoidance steering via the drive system control unit 12010, thereby being able to perform driving assistance for avoiding collision.

[0240] At least one of imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of imaging units 12101 to 12104. Such pedestrian identification is performed, for example, by a process of extracting feature points in the images captured by imaging units 12101 to 12104 that are infrared cameras and a process of performing pattern matching processing on a series of feature points indicating the contour of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the images captured by imaging units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to superimpose and display a rectangular contour line for emphasis on the identified pedestrian. In addition, the audio-visual output unit 12052 may also control the display unit 12062 to display an icon or the like representing the pedestrian at a desired position.

[0241] Examples of a vehicle control system to which the technology according to the present disclosure can be applied have been described above. For example, the technology according to the present disclosure can be applied to the vehicle external information detection unit 12030 in the above configuration. Specifically, Figure 1 the ranging module 100 can be applied to the vehicle external information detection unit 12030. By applying the technology according to the present disclosure to the vehicle external information detection unit 12030, miniaturization of pixels is promoted, and thus ranging accuracy can be improved.

[0242] Note that each of the embodiments described above describes an example for embodying the present technology, and the matters in the embodiments have a correspondence with the matters specifying the present invention in the claims. Similarly, the matters specifying the present invention in the claims have a correspondence with the matters denoted by the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from its gist.

[0243] Note that the advantageous effects described in this specification are merely examples, and the advantageous effects of the present technology are not limited to them and may include other effects.

[0244] Note that the present technology can also be configured as described below.

[0245] (1) A solid-state imaging device, comprising:

[0246] a pixel array unit provided with a plurality of pixels and signal lines, the plurality of pixels generating a predetermined analog signal according to the incidence of photons, and the plurality of pixels being commonly connected to the signal lines; and

[0247] a photon number detection unit that detects the number of incident photons based on the analog signal transmitted via the signal line.

[0248] (2) The solid-state imaging device according to (1), wherein

[0249] each of the plurality of pixels supplies a current signal as the analog signal via the signal line, and

[0250] the photon number detection unit includes:

[0251] a current-voltage conversion unit that converts the current signal into a voltage signal; and

[0252] an analog-to-digital conversion unit that converts the voltage signal into the photon number.

[0253] (3) The solid-state imaging device according to (2), wherein

[0254] each of the plurality of pixels includes:

[0255] a light receiving circuit that outputs a cathode potential that decreases when the photons are incident;

[0256] a first pulse signal generation unit that generates a first pulse signal based on the cathode potential; and

[0257] a transistor that outputs the current signal to the signal line based on the pulse signal.

[0258] (4) The solid-state imaging device according to (3), wherein

[0259] each of the plurality of pixels further includes:

[0260] a second pulse signal generation unit that generates a second pulse signal having a pulse width shorter than that of the first pulse signal based on an inverted signal obtained by inverting the cathode potential; and

[0261] a masking processing unit that stops the output of the current signal to the signal line during a predetermined masking period after the generation of the second pulse signal, and

[0262] the analog-to-digital conversion unit converts the voltage signal into the photon number during the masking period.

[0263] (5) The solid-state imaging device according to (3) or (4), wherein

[0264] each of the plurality of pixels transmits a pair of differential signals as the current signal, and the pair of differential signals is obtained by differentially amplifying the pulse signal and a signal obtained by inverting the pulse signal.

[0265] (6) The solid-state imaging device according to any one of (3) to (5), wherein

[0266] The analog-to-digital conversion unit includes:

[0267] A zero-current confirmation circuit that confirms whether the current signal is output;

[0268] A time-to-digital converter that, when the current signal is not output, converts the elapsed time from the light emission timing to the cathode potential drop into a digital value; and

[0269] A simultaneous reaction number detection unit that detects the number of photons incident during the elapsed time based on the digital value and the voltage signal.

[0270] (7) The solid-state imaging device according to (6), wherein

[0271] The simultaneous reaction number detection unit includes:

[0272] A peak holding circuit that holds the peak of the voltage signal during the elapsed time; and

[0273] A logic circuit that detects the number of photons based on the peak.

[0274] (8) The solid-state imaging device according to (6), wherein

[0275] The simultaneous reaction number detection unit includes:

[0276] A sample-and-hold circuit that receives the voltage signal at a predetermined timing during the elapsed time and holds the voltage signal as a held value; and

[0277] A logic circuit that detects the number of photons based on the held value.

[0278] (9) The solid-state imaging device according to (1), wherein

[0279] Each of the plurality of pixels provides a voltage signal as the analog signal via the signal line, and

[0280] The photon number detection unit includes an analog-to-digital conversion unit that converts the voltage signal into the photon number.

[0281] (10) The solid-state imaging device according to (9), wherein

[0282] The analog-to-digital conversion unit detects the number of photons based on the frequency characteristics of the voltage signal.

[0283] (11) The solid-state imaging device according to (9), wherein

[0284] The analog-to-digital converter detects the number of photons based on the conversion rate of the voltage signal.

[0285] (12) The solid-state imaging device according to any one of (1) to (11), wherein

[0286] the pixel array unit is divided into a plurality of pixel blocks, and

[0287] the photon number detection unit detects the number of photons for each of the plurality of pixel blocks.

[0288] (13) An electronic device, comprising:

[0289] a pixel array unit provided with a plurality of pixels and signal lines, the plurality of pixels generating a predetermined analog signal according to the incidence of photons, and the plurality of pixels being commonly connected to the signal lines;

[0290] a photon number detection unit that detects the number of incident photons based on the analog signal transmitted via the signal line; and

[0291] a signal processing unit that measures the distance to a predetermined object based on the number of photons.

[0292] List of reference symbols

[0293] 100 Ranging module

[0294] 110 Light emitting unit

[0295] 120 Control unit

[0296] 200 Solid-state imaging device

[0297] 201 Optical receiving chip

[0298] 202 Logic chip

[0299] 210 Optical receiving unit

[0300] 220 Optical receiving circuit

[0301] 221, 331 Resistors

[0302] 222 Photoelectric conversion element

[0303] 230 Analog circuit accessory

[0304] 240 Current signal generation unit

[0305] 241 Circuit block

[0306] 250 Current supply circuit

[0307] 251, 256, 321, 341, 362, 395 Inverters

[0308] 252 and 353 Monostable Multivibrators

[0309] 253 Transistor

[0310] 254 and 255 Differential Transistors

[0311] 257 Current Source

[0312] 260 Current-Voltage Conversion Unit

[0313] 270 Analog-to-Digital Conversion Unit

[0314] 271 Zero-Current Confirmation Circuit

[0315] 272 Time-to-Digital Converter

[0316] 280 Simultaneous Reaction Number Detection Circuit

[0317] 281 and 372 Peak-Hold Circuits

[0318] 282, 332, 344, 361 nMOS Transistors

[0319] 283, 312, 399 Capacitors

[0320] 284 and 401 Reset Switches

[0321] 285, 373, 400 ADC

[0322] 286, 380, 402 Logic Circuits

[0323] 290 Signal Processing Unit

[0324] 300 Pixel Array Unit

[0325] 301 Pixel Block

[0326] 305 Pixel

[0327] 306 Photon Number Detection Unit

[0328] 310 Sample-and-Hold Circuit

[0329] 311 Sampling Switch

[0330] 320 Pulse Shaping Unit

[0331] 322, 333, 343, 396 AND (Logical Product) Gates

[0332] 330 Masking Processing Unit

[0333] 334, 335, 337, 398 Switches

[0334] 336, 342 NOR (Negative OR) Gates

[0335] 340 Voltage Control Circuit

[0336] 350 Recharge Control Unit

[0337] 351 OR (Logical Sum) Gate

[0338] 352 Delay Circuit

[0339] 370 Frequency Component Extraction Circuit

[0340] 371 Band - Pass Filter

[0341] 391, 392 Comparators

[0342] 393, 394 Latch Circuits

[0343] 397 Current Source

[0344] 12030 Vehicle External Information Detection Unit.

Claims

1. A solid-state imaging device, comprising: a pixel array unit provided with a plurality of pixels and signal lines, the plurality of pixels generating a predetermined analog signal according to the incidence of photons, and the plurality of pixels being commonly connected to the signal lines; and a photon number detection unit that detects the number of incident photons based on the analog signal transmitted via the signal lines; wherein each of the plurality of pixels provides a current signal as the analog signal via the signal lines, and each of the plurality of pixels includes a light receiving circuit that outputs a cathode potential that decreases when the photons are incident; wherein the photon number detection unit includes: a current-voltage conversion unit that converts the current signal into a voltage signal; and an analog-to-digital conversion unit that converts the voltage signal into the number of photons; and wherein the analog-to-digital conversion unit includes: a zero current confirmation circuit that confirms whether the current signal is output; a time-to-digital converter that converts the elapsed time from the light emission timing to the decrease in the cathode potential into a digital value when the current signal is not output; and a simultaneous reaction number detection unit that detects the number of photons incident during the elapsed time based on the digital value and the voltage signal.

2. The solid-state imaging device according to claim 1, wherein each of the plurality of pixels further comprises: a first pulse signal generation unit that generates a first pulse signal according to the cathode potential; and a transistor that outputs the current signal to the signal line according to the first pulse signal.

3. The solid-state imaging device according to claim 2, wherein each of the plurality of pixels further comprises: a second pulse signal generation unit that generates a second pulse signal having a pulse width shorter than the pulse width of the first pulse signal based on an inverted signal obtained by inverting the cathode potential; and a masking processing unit that stops the output of the current signal to the signal line during a predetermined masking period after generating the second pulse signal, and the analog-to-digital conversion unit converts the voltage signal into the number of photons during the masking period.

4. The solid-state imaging device according to claim 2, wherein each of the plurality of pixels transmits a pair of differential signals as the current signal, and the pair of differential signals is obtained by differentially amplifying the first pulse signal and a signal obtained by inverting the first pulse signal.

5. The solid-state imaging device according to claim 1, wherein the simultaneous reaction number detection unit comprises: a peak holding circuit that holds the peak value of the voltage signal during the elapsed time; and a logic circuit that detects the number of photons based on the peak value.

6. The solid-state imaging device according to claim 1, wherein the simultaneous reaction number detection unit comprises: a sample and hold circuit that receives the voltage signal at a predetermined timing during the elapsed time and holds the voltage signal as a hold value; and a logic circuit that detects the number of photons based on the hold value.

7. The solid-state imaging device according to claim 1, wherein Each of the plurality of pixels provides a voltage signal as the analog signal via the signal line, and the photon number detection unit includes an analog-to-digital conversion unit that converts the voltage signal into the photon number.

8. The solid-state imaging device according to claim 7, wherein the analog-to-digital conversion unit detects the photon number based on the frequency characteristic of the voltage signal.

9. The solid-state imaging device according to claim 7, wherein the analog-to-digital conversion unit detects the photon number based on the conversion rate of the voltage signal.

10. The solid-state imaging device according to claim 1, wherein the pixel array unit is divided into a plurality of pixel blocks, and the photon number detection unit detects the photon number for each of the plurality of pixel blocks.

11. An electronic device, comprising: a pixel array unit provided with a plurality of pixels and signal lines, the plurality of pixels generating a predetermined analog signal according to the incidence of photons, and the plurality of pixels being commonly connected to the signal lines; a photon number detection unit that detects the number of incident photons based on the analog signal transmitted via the signal line; and a signal processing unit that measures the distance to a predetermined object based on the photon number; wherein each of the plurality of pixels provides a current signal as the analog signal via the signal line, and each of the plurality of pixels includes a light receiving circuit that outputs a cathode potential that decreases when the photons are incident; wherein the photon number detection unit includes: a current-voltage conversion unit that converts the current signal into a voltage signal; and an analog-to-digital conversion unit that converts the voltage signal into the photon number; and wherein the analog-to-digital conversion unit includes: a zero current confirmation circuit that confirms whether the current signal is output; a time-to-digital converter that converts the elapsed time from the light emission timing to the decrease in the cathode potential into a digital value when the current signal is not output; and a simultaneous reaction number detection unit that detects the number of photons incident during the elapsed time based on the digital value and the voltage signal.

Images