Column select architecture with edge pad optimization

Abstract

This application relates to a column selector architecture with edge pad optimization. A memory pad architecture is presented in which a column decoder is disposed within a memory array. The location of the column decoder reduces the distance between the column decoder and a target memory cell and thus reduces the distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller of the memory array. The column decoder can be disposed in the middle of the memory array or offset from the middle towards a far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to memory array architecture. BACKGROUND

[0002] This section is intended to introduce the reader to various aspects of art that can be related to various aspects of the present disclosure and is not intended to limit the scope of the claims. Believed familiar to those skilled in the art, this discussion is intended to provide background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

[0003] Dynamic random access memory (DRAM) device arrays include row segment portions with staggered segments and sense amplifiers coupled to consecutive row segments. Edge memory pads can include staggered digit lines to increase the storage density of the memory array. However, a predecoder and a column decoder are typically disposed at each edge memory pad at either end of the array. That is, a double predecoder and column decoder can be used to improve the access time of the memory array by reducing the distance between a target memory cell and the column decoder. However, the double predecoder and column decoder can increase the size of the memory array and / or consume more physical space on the memory array.

[0004] Embodiments of the present disclosure can be related to one or more of the problems set forth above. SUMMARY

[0005] One aspect of the present disclosure provides an apparatus comprising: a first portion including a first plurality of memory pads; a second portion including a second plurality of memory pads; a plurality of column decoders including a first column decoder and a second column decoder, wherein the first column decoder and the second column decoder are disposed between the first portion and the second portion, wherein the first column decoder is configured to provide a first column select signal to the first portion in response to a predecoder, and wherein the second column decoder is configured to provide a second column select signal to the second portion in response to the predecoder; and a bank controller including a predecoder configured to provide a predecode signal, wherein the second portion is between the plurality of column decoders and the bank controller.

[0006] Another aspect of the disclosure provides an electronic device comprising a command interface comprising a plurality of circuits and configured to receive a plurality of signals; and a plurality of memory banks comprising one or more edge memory pads and one or more internal memory pads, each memory bank of the plurality of memory banks comprising a bank controller coupled to the command interface, and the bank controller configured to provide a voltage to a respective column decoder to perform a column selection operation, wherein the respective column decoder is disposed between adjacent edge memory pads of a respective memory bank, wherein the plurality of signals cause the bank controller of the respective memory bank to perform an operation on the one or more edge memory pads and the one or more internal memory pads of the respective memory bank.

[0007] Another aspect of the disclosure provides a method comprising determining a process inflection point of a column selection operation; identifying a voltage level corresponding to the process inflection point; and driving a column decoder via the voltage level, wherein the column decoder is disposed between a first portion of a memory bank and a second portion of the memory bank, wherein the first portion comprises at least two edge memory pads and at least one internal memory pad, and wherein the first portion is proximate to a bank controller. BRIEF DESCRIPTION OF DRAWINGS

[0008] Various aspects of the disclosure can be better understood after a reading of the following detailed description with reference to the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating some features of a memory device according to an embodiment of the disclosure.

[0010] Figure 2 is a schematic block diagram of a memory architecture for a column selection operation.

[0011] Figure 3A is a schematic block diagram of a column selection memory architecture.

[0012] Figure 3B is a schematic block diagram illustrating a column selection memory architecture according to an embodiment of the disclosure.

[0013] Figure 3C is a schematic block diagram of a column selection memory architecture according to another embodiment of the disclosure.

[0014] Figure 4 is a schematic diagram of a column decoder voltage level shifter according to an embodiment of the disclosure.

[0015] Figure 5 is an example schematic diagram of a column decoder voltage level shifter for various process inflection points according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0016] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

[0017] Memory devices exchange data and store data in memory banks. Each memory bank can include a plurality of sub-arrays, each sub-array including a plurality of memory cells that store data. A subgroup of sub-arrays can be positioned to form a row of a memory array. Each sub-array of the row can be coupled to a common set of sense amplifiers and to a common column select line or common digit line. That is, a set of sense amplifiers can be disposed in a row of sub-arrays such that the sub-arrays alternate with the sense amplifiers. As used herein, a memory mat can include any number of sub-arrays coupled to a common word line, a sub-word line driver, or a set of sub-word line drivers. In some embodiments, a memory mat can also be referred to as a "row segment portion." As used herein, an "edge mat" or "edge memory mat" can refer to a memory mat on an edge of a row of a memory array.

[0018] An edge memory mat can include interleaved separate digit lines. The interleaved digit lines can improve the storage density of a memory array without increasing the size of the array. However, to access data stored in the array, a pre-decoder and a column decoder can be disposed at either end of the memory array of a memory bank. That is, two pre-decoders and column decoders (one at each end of the memory array) can be used to reduce the distance between a target memory cell and the column decoder. However, adding a second pre-decoder and a second column decoder at different locations can increase the physical size of the memory array or reduce the storage capacity. In comparison to conventional memory array architectures, the embodiments disclosed herein provide improved performance and increased speed of memory access operations.

[0019] Embodiments disclosed herein provide memory array architectures with column decoders disposed within the memory array. The location of the column decoders can reduce the distance from the column decoders to target memory cells and thus reduce the distance that column select signals travel from the column decoders to the target memory cells. The column decoders can be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoders enables reduced array access times to obtain data from the target memory cells. A single pre-decoder can be disposed in a bank controller of a memory array.

[0020] Figure 1 is a block diagram illustrating some features of a memory device 100. According to some embodiments, the memory device 100 can be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, increased bandwidth, and increased storage capacity compared to previous generations of DDR SDRAM. The memory device 100 represents a portion of a single memory chip (e.g., SDRAM chip) having a plurality of memory banks 102. The memory banks 102 can be, for example, DDR5 SDRAM memory banks. The memory banks 102 can be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). Each DIMM can include a plurality of SDRAM memory chips (e.g., eight or sixteen memory chips). Each SDRAM memory chip can include one or more memory banks 102.

[0021] For DDR5, the memory banks 102 can be further arranged to form bank groups. For example, a memory chip can include sixteen memory banks 102 for an eight gigabyte (8 Gb) DDR5 SDRAM. The memory banks 102 can be arranged into eight bank groups, each bank group including two memory banks. For a sixteen gigabyte (16 Gb) DDR5 SDRAM, a memory chip can include thirty-two memory banks 102 arranged into eight bank groups, each bank group including, for example, four memory banks 102.

[0022] Various other configurations, organizations, and sizes of the memory banks 102 on the memory device 100 can be utilized depending on the application and design of the overall system. In one embodiment, each memory bank 102 includes a bank controller 120 that controls the execution of commands to and from the memory bank 102 to perform various functions in the memory device, such as decoding, timing control, data control, and any combination thereof.

[0023] The memory bank 102 can include one or more memory pads 130 that store data. Each memory pad 130 is communicatively coupled to a respective bank controller 120. The bank controller 120 can select a particular memory pad 130 and a column and / or row within the memory pad 130 from which data can be retrieved. Reference is made to the following Figures 3A-3C The bank controller 120 is discussed in greater detail.

[0024] The command interface 104 of the memory device 100 is configured to receive and transmit a plurality of signals (e.g., signals 106). The signals 106 can be received from an external device (not shown), such as a processor or controller. The processor or controller can provide various signals 106 to the memory device 100 to facilitate the transmission and reception of data to be written to or read from the memory device 100.

[0025] As will be appreciated, the command interface 104 can include a plurality of circuits, such as a clock input circuit (CIC) 108 and a command address input circuit (CAIC) 110, for example, to ensure proper handling of the signals 106. The command interface 104 can receive one or more clock signals from an external device. Generally, double data rate (DDR) memory uses a system clock signal in a differential pair, referred to herein as a true clock signal Clk t and a bar or complementary clock signal Clk c. A positive clock edge of DDR refers to the point where the rising true clock signal Clk t crosses the falling bar clock signal Clk c. A negative clock edge indicates the transition of the falling true clock signal Clk t and the rising bar clock signal Clk c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal. Data can be sent or received on both the positive and negative clock edges.

[0026] The clock input circuit 108 receives the true clock signal Clk t and the bar clock signal Clk c and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 112. The DLL circuit 112 generates a phased internal clock signal LCLK based on the received internal clock signal CLK. The phased internal clock signal LCLK is supplied to, for example, the I / O interface 124 and is used as a timing signal for determining the output timing of read data. In some embodiments, the clock input circuit 108 can include circuitry that splits the clock signal into multiple (e.g., four) phases. The clock input circuit 108 can also include a phase detection circuit that is used to detect which phase receives the first pulse when the pulse group is too frequent so that the clock input circuit 108 is able to reset between pulse groups.

[0027] An internal clock signal / phase CLK can also be provided to various other components within the memory device 100 and can be used to generate various additional internal clock signals. For example, the internal clock signal CLK can be provided to the command decoder 114. The command decoder 114 can receive command signals from the command bus 116 and can decode the command signals to provide various internal commands. For example, the command decoder 114 can provide command signals to the DLL circuit 112 over bus 118 to coordinate the generation of the phased internal clock signal LCLK. The phased internal clock signal LCLK can be used to, for example, clock data through the I / O interface 124.

[0028] Additionally, the command decoder 114 can decode commands such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to a particular memory bank 102 corresponding to the command via bus path 132. As will be appreciated, the memory device 100 can include various other decoders, such as row and column decoders, to facilitate access to the memory banks 102.

[0029] The memory device 100 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus 116 can be a 14-bit bus (CA<13:0>) to accommodate command / address signals. The command / address signals 106 are clocked to the command interface 104 using clock signals (Clk_t and Clk_c). The command interface 104 can include command address input circuitry 110 configured to receive and transmit commands through the command decoder 114 to provide access to the memory banks 102. In addition, the command interface 104 can receive a chip select signal (CS_n). The CS_n signal enables the memory device 100 to process commands on the incoming CA<13:0> bus. Access to a particular memory bank 102 and / or a particular memory pad 130 within the memory device 100 is encoded using commands on the CA<13:0> bus.

[0030] Additionally, command interface 104 can be configured to receive a plurality of other command signals. For example, a command / address (CA ODT) signal can be provided on a die terminal to facilitate proper impedance matching within memory device 100. For example, a reset command (RESET_n) can be used to reset command interface 104, status registers, state machines, etc. during power up. Command interface 104 can also receive a command / address invert (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on command / address bus 116, for example, depending on the command / address routing of the particular memory device 100. A mirror (MIR) signal can also be provided to facilitate mirror functionality. Based on the configuration of a plurality of memory devices (e.g., memory device 100) in a particular application, the MIR signal can be used to multiplex signals so that the signals can be swapped to enable certain routing of signals to memory device 100. Various signals can also be provided to facilitate testing of memory device 100, for example, a test enable (TEN) signal. For example, the TEN signal can be used to place memory device 100 in a test mode for connectivity testing.

[0031] Command interface 104 can also be used to provide a warning signal (ALERT_n) to a system processor or controller for detectable errors. For example, the warning signal (ALERT_n) can be transmitted from memory device 100 in the event of a cyclic redundancy check (CRC) error being detected. Other warning signals can also be generated. In addition, the bus and pin used to transmit the warning signal (ALERT_n) from memory device 100 can be used as an input pin during some operations, for example, the connectivity test mode described above that is performed using the TEN signal.

[0032] Data can be sent to and from memory device 100 using the command and timing signals discussed above by transmitting and receiving data signals 126 via I / O interface 124. More specifically, data can be sent to or retrieved from memory bank 102 through data path 122, which includes a plurality of bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are generally transmitted and received on one or more bidirectional data buses. For a particular memory device, such as a DDR5 SDRAM memory device, the I / O signals can be divided into upper and lower bytes. For example, for an x16 memory device, the I / O signals can be divided into upper and lower I / O signals (e.g., DQ<16:8> and DQ<7:0>) corresponding to upper and lower bytes of data signals, for example.

[0033] To allow higher data rates within the memory device 100, some memory devices, such as DDR memory devices, can use a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending the data (e.g., for a write command) or by the memory device 100 (e.g., for a read command). For read commands, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For write commands, the DQS signal can be used as a clock signal to capture the corresponding input data. As with the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For some memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) that correspond to upper and lower bytes of data sent to and from the memory device 100.

[0034] An impedance (ZQ) calibration signal can also be provided to the memory device 100 through the I / O interface 124. The ZQ calibration signal can be provided to a reference pin and used to tune the output driver and ODT values by adjusting the pull-up and pull-down resistors of the memory device 100 in changes in process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the ZQ resistor values, the ZQ calibration signal can be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 100 and GND / VSS external to the memory device 100. This resistor acts as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0035] Further, a loopback signal (LOOPBACK) can be provided to the memory device 100 through the I / O interface 124. The loopback signal can be used during a test or debug phase to set the memory device 100 into a mode where the signal loops back through the memory device 100 through the same pin. For example, the loopback signal can be used to set the memory device 100 to test the data output (DQ) of the memory device 100. The loopback can include both data and strobe or can include only data pins. This is generally expected to be used to monitor the data captured by the memory device 100 at the I / O interface 124.

[0036] As will be appreciated, various other components such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operation and configuration), read / write amplifiers (to amplify signals during read / write operations), temperature sensors (for sensing temperature of the memory device 100), and the like can also be incorporated into the memory device 100. Thus, it should be understood that the block diagram of FIG. 1 is provided to highlight some functional features of the memory device 100 to aid in the following detailed description. Moreover, while the foregoing has discussed a DDR5 memory device, the level shifter discussed herein can be used with any type of electronic device and / or other types of memory, such as a double data rate type 4 DRAM (DDR4) memory device. Figure 1

[0037] Figure 2 is a schematic block diagram of a memory architecture 200 for column selection operations. As shown, the memory architecture 200 includes a set of sense amplifiers (SAs) 202, edge memory pads 204, and internal memory pads 214 disposed between the edge memory pads 204. As shown, each edge pad 204 can include at least one of the sense amplifiers 202. While only one internal memory pad 214 is shown, it should be understood that any number of memory pads 214 can be disposed between the edge memory pads 204. The edge memory pads 204 and the internal memory pads 214 each include one or more memory cells (e.g., memory arrays) (not shown) disposed between the sense amplifiers 202.

[0038] The internal memory pads 214 include digit lines 212, 216 (e.g., access lines, bit lines, data I / O lines, etc.) coupled to adjacent sense amplifiers 202. The digit lines 212, 216 of the internal memory pads 214 can be split into first digit lines 212 and second digit lines 216. The first digit lines 212 are coupled to the sense amplifiers 202 on a first side of the internal memory pads 214, and the second digit lines 216 are coupled to the sense amplifiers on a second side of the internal memory pads 214 opposite the first side. The digit lines 212, 216 can also be coupled to respective memory cells of the internal memory pads 214.

[0039] ​The edge memory pad 204 includes digit lines 208, 210. The digit lines 210 can be coupled to respective sense amplifiers 202, while respective pairs of digit lines 208 can be connected via digit line jumper 206 to form extended digit lines from the edge pad 204 to adjacent sense amplifiers 202. The digit lines 208, 210 can be coupled to respective memory cells of the edge memory pad 204. The digit lines 208 can be interleaved with the digit lines 210. The digit line jumper 206 can span a respective sense amplifier 202 such that the corresponding digit line 208 is not coupled to the sense amplifier 202 of the edge pad 204. Each edge memory pad 204 can include memory cells on either side of the sense amplifier 202 (not shown). The size of the entire edge memory pad 204, including both sides of the sense amplifier 202, can be half the size of the memory cells of the internal memory pad 214.

[0040] The length (N) of the respective digit lines 208, 210 (excluding the digit line jumper 206) of the edge memory pad 204 can be about half the length (2N) of the digit lines 212, 216 of the internal memory pad 214. The length of the digit line jumper 206 can be substantially equal to the length (N) of the digit lines 208, 210. That is, the length of the digit lines 208 of the edge memory pad 204 with the digit line jumper 206 can be substantially equal to the length of the digit lines 212, 216 of the internal memory pad 214. While six digit lines 208, 210, 212, 216 are depicted, it should be understood that more or fewer digit lines can be used.

[0041] Advantageously, the edge memory pad 204 can improve the effective use of the memory architecture 200 by allowing the use of every memory cell of the edge memory pad 204. That is, by dividing (e.g., splitting) the digit lines 208, 210 of the edge memory pad 204, the external memory cells positioned outside of the edge memory pad 204 (e.g., opposite the internal memory pad 214) can be accessed and used to store and retrieve data therein. Without the edge memory pad 204, at least half of the external memory cells would be unused because the corresponding digit lines would not be interleaved and the corresponding memory cells would not be accessed. Thus, the edge memory pad 204 enables the efficient use of the memory cells of the memory architecture 200.

[0042] Figure 3A is a schematic block diagram of a column-select memory architecture 230. The memory architecture 230 includes a plurality of sense amplifiers (SAs) 202 disposed between memory pads 244, 246. That is, the sense amplifiers 202 alternate between the memory pads 204. The memory architecture also includes a bank controller 120, a pre-decoder 234, and a column decoder 240.

[0043] The bank controller 120 is disposed at a first end 228 of the memory architecture 230. A second end 229 of the memory architecture 230 is opposite the first end 228 and the bank controller 120. As discussed with reference to Figure 1 The bank controller 120 can control various functions of the memory architecture 230, such as decoding, timing, data control, and combinations thereof, as discussed with reference to

[0044] The pre-decoder 234 can extract or decode an address (e.g., a column address) from an input signal to be used to retrieve data from the memory pads 244, 246. The data sense amplifier 236 can receive a low power data signal from a bit line and amplify the data signal to an identifiable logic level to be interpreted by logic circuitry external to the memory architecture 230. The amplified data signal from the data sense amplifier 236 can be provided to the sense amplifier 202. The CAS controller 238 can receive an input signal and identify a column of a particular memory cell in which the address decoded by the pre-decoder 234 is located. The CAS controller 238 can also verify a column address of a target memory cell. That is, the CAS controller 238 can determine whether a column address of a target memory cell is a valid column address for a corresponding memory architecture. The column decoder 240 can receive a column address from the pre-decoder 234 and send a column select (CS) signal to a particular memory cell and / or digit line to retrieve or modify data at a particular column address.

[0045] The memory architecture 230 includes edge memory pads 246 at the first end 228 and the second end 229. As shown, the edge memory pads 246 do not include sense amplifiers or digit line cross-overs similar to the edge memory pads 204 as discussed with reference to Figure 2 In fact, the edge memory pads 246 can be conventional edge memory pads and include unused memory cells because the corresponding digit lines are not split. Thus, the edge memory pads 246 include memory cells that increase the physical size without increasing the storage capacity of the memory architecture 230.

[0046] Predecoder 234 and column decoder 240 may be located at a first end 228 and a second end 229 of memory architecture 230. The dual predecoder 234 and column decoder 240 reduce the distance a signal travels from the predecoder 234 and column decoder 240 to reach a target memory cell (e.g., a target column address) in the target memory pad 244. That is, as indicated by arrow 222 from column decoder 240 at the first end 228 to intermediate sense amplifier 226, the predecoder 234 and column decoder 240 at the first end 228 can be used to access memory cells in the half of the memory architecture closest to group controller 120. Similarly, as indicated by arrow 220 from column decoder 240 at the second end 229 to intermediate sense amplifier 224, the predecoder 234 and column decoder 240 at the second end 229 can be used to access memory cells in the half of the memory architecture furthest from group controller 120. Each arrow 220, 222 corresponds to the column selection path for the corresponding sense amplifier 202 and the length of four memory pads. That is, the distance from the column decoder 240 to the farthest corresponding sense amplifier 202 is four pads. Reducing the distance from the pre-decoder 234 and the column decoder 240 to the target memory cell also reduces the time (e.g., access time) for retrieving or modifying data in the target memory pad 244, because the column selection signal arrives at the corresponding sense amplifier 202 of the target memory cell earlier.

[0047] The time to access a specific memory cell can be measured in memory pads 244 and 246. That is, the time to access a memory cell can be based on the distance traveled from group controller 120 to the target memory cell and the distance traveled by retrieved data back to group controller 120, using one or more signals. For example, the time to access a memory cell corresponding to intermediate sense amplifier 224 includes the distance (9 pads) from group controller 120 to pre-decoder 234 (and column decoder 240) at second end 229, the distance from column decoder 240 at second end 229 to the corresponding sense amplifier 224 (4 pads indicated by arrow 220), and the distance from sense amplifier 224 to group controller 120 (5 pads indicated by arrow 225). Arrow 225 corresponds to the memory input / output path from sense amplifier 224 to data sense amplifier 224. Therefore, the maximum access time (and distance) to the target memory cell of memory architecture 230 is 18 memory pads.

[0048] Figure 3B This is a schematic block diagram illustrating a column selection memory architecture 250 according to an embodiment of the present disclosure. Memory architecture 250 and reference Figure 3A The memory architectures discussed are similar, but include, as referenced Figure 2The edge memory pads 204 discussed. The memory architecture 250 also includes a column decoder 240 positioned in the middle of the memory architecture 250. A first half 260 of the memory architecture 250 can be between the column decoder 240 and a first end 228 of the memory architecture 250. A second half 262 of the memory architecture 250 can be between the column decoder 240 and a second end 229 of the memory architecture 250. Although the first half 260 and the second half 262 each include two internal memory pads 244, it should be understood that each half 260, 262 can include any number of internal memory pads 244 between the edge memory pads 204.

[0049] In some embodiments, as shown, the column decoder 240 can include two column decoders 240. As depicted by a first arrow 254, a first column decoder 240 closest to the first end 228 can be used to access memory cells in the first half 260 of the memory architecture 250, while as depicted by a second arrow 252, a second column decoder 240 closest to the second end 229 can be used to access memory cells in the second half 262 of the memory architecture 250.

[0050] As shown, the edge memory pads 204 are disposed at the first end 228 and the second end 229 of the memory architecture 250, and on either side of the column decoder 240 in the center of the memory architecture 250. As discussed with respect to Figure 2 The edge memory pads 204 enable a reduction in the size of the memory architecture 250 while allowing access to memory cells corresponding to the edge memory pads 204. Thus, the edge memory pads 204 increase storage density while maintaining or reducing the size of the memory architecture 250. Additionally, the use of the edge memory pads 204 allows a single predecoder 234 to be disposed in the bank controller 120 and shared by each column decoder 240.

[0051] The edge memory pads 204 also reduce the maximum access time (and distance) of a target memory cell. For example, to access target data in a memory cell corresponding to a target sense amplifier 256 at the second end 229 of the memory architecture 250, a predecoder address is sent from the bank controller 120 to the column decoder 240 for the second half of the architecture 250. That is, the predecoder address travels a distance of 4 pads from the predecoder 234 to the column decoder 240.

[0052] Column decoder 240 sends a column select (CS) signal to a target sense amplifier 256 to access data at a pre-decoded address. That is, as depicted by the second arrow 252, the CS signal travels a distance of 3.5 pads from column decoder 240 to target sense amplifier 256. The CS signal travels a distance of half a pad (e.g., 0.5 pads) across edge memory pad 204 at second end 229, as the CS signal travels to target sense amplifier 256 on half 264 of edge memory pad 204. Once the target data is obtained and / or modified, the target data is sent back to a data sense amplifier of group controller 120 in a distance of 7.5 pads, as depicted by arrow 258. Thus, the maximum access time (and distance) of a target memory cell of memory architecture 250 is 15 memory pads. Thus, when compared to the architecture of Figure 3A Edge memory pad 204 allows for a reduced access time of memory architecture 250, while the physical size of memory architecture 250 is reduced and the storage density is increased, when compared to the architecture of

[0053] Figure 3C is a schematic block diagram of a column select memory architecture 280 according to another embodiment of the disclosure. Memory architecture 280 is substantially similar to memory architecture 250 discussed with reference to Figure 3B However, the location of column decoder 240 is biased towards second end 229 of memory architecture 280. That is, column decoder 240 is positioned closer to second end 229 of the memory architecture and further away from group controller 120.

[0054] As shown, a first side 282 of memory architecture 280 closest to first end 228 includes two edge memory pads 204 and three internal memory pads 244, while a second side 284 of memory architecture 280 closest to second end 229 includes two edge memory pads 204 and one internal memory pad 244. While the maximum access time (and distance) of memory architecture 280 is the same as the maximum access time (and distance) of memory architecture 250 discussed with reference to Figure 3C However, the distance that the CS signal travels from column decoder 240 to edge pad 204 at second end 229 is reduced by one (1) memory pad. That is, to access a memory cell corresponding to sense amplifier 256 of edge pad 204 at second end 229, the CS signal travels a distance of 2.5 pads from column decoder 240 to sense amplifier 256. On the other hand, with memory architecture 250, the CS signal travels a distance of 3.5 pads from column decoder 240 to sense amplifier 256 at second end 229. Figure 3Bfour pads in the middle, the predecoder address travels farther from the predecoder 234 to the column decoder, i.e., five pads. However, during operation, the CS signal to access all memory pads (e.g., internal memory pads 244 and edge memory pads 204) is transmitted on a single column select line (not shown) coupled to each sense amplifier 202. Thus, the load of the column selection operation (e.g., sending multiple CS signals from the column decoder 240 to different sense amplifiers 202 at the same time) can be higher than the load of the predecoder operation (e.g., sending a predecoder address from the predecoder 234 to the column decoder 240). The increased load of the column selection operation can limit the access speed of the memory architecture 250, 280.

[0055] Biasing the location of the column decoder toward the second end of the memory architecture 280 reduces the time and distance the CS signal travels from the column decoder 240 to the target memory pad 204, 244 (and corresponding memory cell) in the second side 284 (e.g., distal side) of the memory architecture, thereby reducing the load of the column selection operation. Thus, the location of the column decoder can be moved along the memory architecture 280 (e.g., closer or farther from the bank controller) to further improve the access speed based on the load of the column selection operation. The reduced load of the column selection operation can also reduce the power consumption of the operation to access data in the memory architecture 280.

[0056] In some embodiments, a column selection voltage (VCS) 286 can be coupled to the column decoder and used to set the voltage level at which the column selection operation is performed. The VCS 286 can be adjusted (e.g., increased or decreased) to alter the speed of the column selection operation. That is, an increase in the VCS 286 can correspond to an increase in the speed of the column selection operation, thereby further reducing the access time of the target memory cell. As an example, Figure 4 is a schematic diagram of a column decoder voltage level shifter 350 according to embodiments of the present disclosure. The level shifter 350 receives various inputs, determines a process inflection point of the column selection operation, and determines a corresponding column selection voltage level VCS 286 for the column decoder.

[0057] As shown, the level shifter 350 includes an enable device 306, a multiplexer 314, and a transistor 318. The enable device includes a partial decoder 308 and an AND gate 310. The partial decoder 308 can receive a row address 304 (e.g., target address) and determine the memory array in which the target address resides (e.g., refer to FIG. 2). The partial decoder 308 can also determine the location of the target address within the memory array (e.g., the row and column of the target address). The partial decoder 308 can output a partial address 312 that includes the location of the target address within the memory array. Figure 3B and 3CThe output of the partial decoder 308 can indicate a far portion of the memory array or a near portion of the memory array. The far portion can correspond to the second half 262, 284, respectively, and the near portion can correspond to the first half 260, 282, respectively, of the memory architecture 250, 280.

[0058] The input of the level shifter 350 can include at least the row address 304 of the target memory cell, a column latency 302 (e.g., a delay between when a read command is issued and when data is available), a reference voltage 312, a VARY 326 (e.g., a baseline voltage for a column selection operation), and the like. The column latency 302 can indicate a speed (e.g., high or low) at which a column selection operation is to be performed. In some embodiments, the VARY 326 can be about 1 volt, and is a voltage that is adjusted by the level shifter 350.

[0059] The process monitor 322 and the output bus 320 are communicatively coupled to the multiplexer. If the portion from the partial decoder 308 is a near portion, the enable 306 is not enabled, and thus the VARY voltage 326 is provided as the VCS 286 to the bus 320. If the speed at which a column selection operation is to be performed is high and the portion from the partial decoder 308 is a far portion, the enable 306 is enabled and the process monitor 322 can determine a voltage level of the column selection voltage VCS 286 to be output to the column decoder 240 via the bus 320. The process monitor 322 can determine the voltage level of the VCS 286 based on a process corner (e.g., a corner lot) of the level shifter 350. For example, the process monitor 322 can determine whether the process corner is fast-fast (FF) 332, typical- typical (TT) 330, or slow-slow (SS) 328. Depending on the process corner, the voltage output (e.g., VCS 286) of the process monitor 322 can be 1.2 volts for FF, 1.4 volts for TT, and 1.6 volts for SS. Thus, the VCS 286 can be based at least in part on the process corner determined by the process monitor 322. Advantageously, when the speed of the column selection operation is high and the portion identified by the partial decoder 308 is a far portion, the higher voltage applied to the bus 320 as the VCS 286 is able to increase the speed at which the column selection operation is performed.

[0060] Figure 5is an example schematic of a portion 380 of a column decoder voltage level shifter 350 for various process corners according to embodiments of the present disclosure. The portion 380 of the level shifter 350 includes a comparator 382 and transistors for each of the FF process corner, the TT process corner, and the SS process corner. For example, transistor Tl is a p-channel transistor turned on (e.g., a logic high applied to the gate of transistor Tl) for the FF process corner. Similarly, transistor T2 is turned on for the TT process corner, and transistor T3 is turned on for the SS process corner. Each of the transistors Tl, T2, T3 are coupled to and provide a corresponding voltage level to the comparator 382, which then drives a voltage to the VCS 286 via the bus 320. It should be understood that the portion 380 of the voltage shifter 300 is merely an example, and many other circuit arrangements can be used to drive the VCS 286 based at least in part on the process corner.

[0061] The specific embodiments described herein have been shown by way of example, and it should be understood that these embodiments can be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.

[0062] The technology presented and claimed herein is to be understood to reference and cover subject matter similar to that recited herein, that can now be known or developed in the future, that relates to functionality, compositions, and means for implementing the techniques disclosed herein, and that are within the spirit and scope of the technology. Accordingly, the claims are not intended to be limited to the particular form set forth herein, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein. Additionally, if any claims recite a set of two or more elements of the specification using language that means one of the two or more elements, yet if only one of the two or more elements is essential, then it is intended that the claim not be limited to the set of two or more elements but to the element that is actually named in the claim. Further, no requirement exists for the device or methods disclosed herein to address each and every problem that is desired to be solved by the technology disclosed herein even though aspects of the technology can address multiple problems.

Claims

1. A memory device comprising: a first portion of a memory bank including a first plurality of memory pads; a second portion of the memory bank including a second plurality of memory pads; a plurality of column decoders including a first column decoder and a second column decoder, wherein the first column decoder and the second column decoder are disposed between the first portion and the second portion, wherein the first column decoder is configured to provide a first column select signal to the first portion in response to a predecode signal, and wherein the second column decoder is configured to provide a second column select signal to the second portion in response to the predecode signal; and a bank controller of the memory bank including a predecoder configured to provide the predecode signal, wherein the second portion is located between the second column decoder and the bank controller.

2. The memory device of claim 1, wherein the first portion includes a first plurality of sense amplifiers each arranged between a corresponding memory pad of the first plurality of memory pads, and the second portion includes a second plurality of sense amplifiers each arranged between a corresponding memory pad of the second plurality of memory pads.

3. The memory device of claim 1, wherein a size of the first portion and a size of the second portion are equal.

4. The memory device of claim 2, wherein the bank controller includes a data sense amplifier configured to amplify data from the first plurality of sense amplifiers and the second plurality of sense amplifiers.

5. The memory device of claim 1, wherein the bank controller includes a column address strobe controller configured to verify a column address of a target memory cell.

6. The memory device of claim 1, wherein a ratio of a size of the first portion to a size of the second portion is 3:

1.

7. The memory device of claim 1, configured such that a voltage greater than a baseline voltage is applied to the first column decoder for a column select operation to increase a speed of the column select operation.

8. An electronic device comprising: a command interface including a plurality of circuits and configured to receive a plurality of signals; and a plurality of memory banks each including one or more edge memory pads and one or more internal memory pads, each memory bank of the plurality of memory banks including a bank controller coupled to the command interface and configured to provide a voltage to a respective column decoder to perform a column select operation, wherein the respective column decoder is disposed between edge memory pads and internal memory pads of the respective memory bank, wherein the plurality of signals cause the bank controller of the respective memory bank to perform an operation on the one or more edge memory pads and the one or more internal memory pads of the respective memory bank.

9. The electronic device of claim 8, wherein the respective column decoder is disposed between a first portion of the respective memory bank and a second portion of the respective memory bank.

10. The electronic device of claim 9, wherein the first portion is adjacent to the set of controllers, and wherein a size of the first portion is equal to a size of the second portion.

11. The electronic device of claim 9, wherein the first portion is adjacent to the set of controllers, and wherein the first portion is larger than the second portion.

12. The electronic device of claim 8, wherein each of the one or more edge memory mats comprises a first plurality of access line segments, and each of the one or more interior memory mats comprises a second plurality of access line segments.

13. The electronic device of claim 8, comprising a plurality of sense amplifiers disposed between the interior memory mats and between the one or more edge memory mats and adjacent interior memory mats.

14. The electronic device of claim 12, wherein a plurality of access line crossover wires are configured to couple a first portion of the first plurality of access line segments to a second portion of the first plurality of access line segments across a respective sense amplifier.

15. A method of operating a memory device, comprising: determining a process corner of a column selection operation; identifying a voltage level corresponding to the process corner; and driving a column decoder via the voltage level, wherein the column decoder is disposed between a first portion of a memory bank and a second portion of the memory bank, wherein the first portion comprises at least two edge memory mats and at least one interior memory mat, and wherein the first portion is adjacent to a set of controllers of the memory bank.

16. The method of claim 15, wherein the process corner is at least one of fast-fast, typical- typical, and slow-slow.

17. The method of claim 16, wherein the voltage level for a fast-fast process corner is 1.2 volts, wherein the voltage level for a typical-typical process corner is 1.4 volts, and wherein the voltage level for a slow-slow process corner is 1.6 volts.

18. The method of claim 15, comprising: identifying a location of a target memory cell based on a row address of the target memory cell; and identifying a speed of the column selection operation, wherein the speed includes high or low.

19. The method of claim 18, comprising driving the column decoder at a baseline voltage of 1.0 volts when the location of the target memory cell is determined to be in the first portion or when the speed of the column selection operation is determined to be low.

20. The method of claim 18, comprising driving the column decoder at the voltage level based on the process corner when the location of the target memory cell is determined to be in the second portion and when the speed of the column selection operation is determined to be high.

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