Word line voltage generation circuit and memory

Abstract

This application relates to the technical field of FLASH integrated circuits, and discloses a word line voltage generation circuit. A voltage source generation circuit provides a voltage source; one end of a buffer circuit is electrically connected to one end of the voltage source generation circuit, and the buffer circuit generates a buffer voltage according to the voltage source; one end of an erase / program control voltage and generation circuit is connected to the other end of the buffer circuit, and the other end of the erase / program control voltage and generation circuit is connected to the other end of the voltage source generation circuit. The erase / program control voltage and generation circuit generates a first unselected word line voltage according to the drive of the buffer voltage when the erase enable signal is at a high level, and generates a first selected word line voltage according to the drive of the voltage source when the program signal is at a high level. The embodiments of the present disclosure can generate the first unselected word line voltage and the first selected word line voltage without a frequency compensation capacitor, making the chip area of the word line voltage generation circuit applying the embodiments of the present disclosure smaller. This application also discloses a memory.

Description

Technical Field

[0001] This application relates to the technical field of FLASH integrated circuits, for example, to a word line voltage generation circuit and a memory. Background Art

[0002] FLASH is a non-volatile memory. FLASH includes a memory array, a row decoder, a column selector, and a read circuit. The memory array is composed of multiple pages in the row direction, and the select signal for each page is a word line (WL); in the column direction, it is penetrated by multiple bit lines (BL). When the memory array is programmed (PROG), the number of selected word lines (WL_sel) is 1, and the others are unselected word lines (WL_unsel); when erased, the number of WL_sel is 2, and the others are WL_unsel. Taking a 128Mb Flash as an example, the typical total number of WLs is 64,000. When programmed, the number of WL_unsel is 63,999; when erased, the number of WL_unsel is 63,998. The parasitic capacitance on one WL is 0.5pF. Then, when erased, the total capacitance of all WL_unsel is about 32nF, and when programmed, the total capacitance of all WL_sel is about 0.5pF. In the prior art, when the memory array is erased, the voltage source generation circuit in the word line voltage generation circuit outputs a voltage source to the unselected word line voltage generation circuit. The unselected word line voltage generation circuit generates an unselected word line voltage under the drive of the voltage source, and the unselected word line voltage powers the unselected word lines. At this time, the equivalent capacitance of the load output by the output end of the voltage source generation circuit is 32nF. When the memory array is programmed, the voltage source generation circuit outputs a voltage source to the selected word line generation circuit. The selected word line generation circuit generates a selected word line voltage under the drive of the voltage source, and the selected word line voltage powers the selected word lines. At this time, the equivalent capacitance of the load output by the output end of the voltage source generation circuit is 0.5pF. Thus, the equivalent capacitance of the output end of the voltage source generation circuit is 32nF for the unselected word lines when erased and 0.5pF for the selected word lines when programmed, resulting in a large difference in the load capacitance of the output end of the voltage source generation circuit between erasing and programming. For the loop frequency stability of the voltage source generation circuit, a frequency compensation capacitor with a capacitance value between 100 and 300pF is added. However, the 100 - 300pF frequency compensation capacitor occupies a large chip area and increases the cost of the chip. Summary of the Invention

[0003] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a comprehensive review, nor is it intended to identify key / important elements or delineate the scope of protection of these embodiments. Instead, it serves as a preface to the following detailed description.

[0004] Embodiments of the present disclosure provide a word line voltage generation circuit and a memory to fabricate a chip with a smaller area.

[0005] In some embodiments, the word line voltage generation circuit includes: a voltage source generation circuit for providing a voltage source; a buffer circuit electrically connected to one end of the voltage source generation circuit, the buffer circuit being configured to generate a buffer voltage based on the voltage source; a erase / program control voltage and generation circuit, one end of which is connected to the other end of the buffer circuit, and the other end of the erase / program control voltage and generation circuit is connected to the other end of the voltage source generation circuit. The erase / program control voltage and generation circuit is configured to generate a first unselected word line voltage based on the drive of the buffer voltage when the erase enable signal is at a high level, and generate a first selected word line voltage based on the drive of the voltage source when the program signal is at a high level.

[0006] In some embodiments, the memory includes a word line voltage output circuit and the word line voltage generation circuit as described above. The word line voltage output circuit is connected to the word line voltage generation circuit, and the word line voltage output circuit is configured to generate an output word line voltage based on the selected word line voltage and the unselected word line voltage.

[0007] The word line voltage generation circuit and the memory provided by the embodiments of the present disclosure can achieve the following technical effects: The voltage source generation circuit provides a voltage source, the buffer circuit generates a buffer voltage based on the voltage source, and the erase / program control voltage and generation circuit generates a first selected word line voltage based on the drive of the voltage source when the program signal is at a high level. Since the first selected word line voltage powers the selected word line, the equivalent capacitance of the selected word line is the same as the load capacitance at the output end of the voltage source generation circuit. The erase / program control voltage and generation circuit generates a first unselected word line voltage based on the drive of the buffer voltage. Since the unselected word line voltage powers the unselected word line, the equivalent capacitance of the unselected word line is the same as the load capacitance at the output end of the buffer circuit. The embodiments of the present disclosure isolate the equivalent capacitance of the unselected word line and the equivalent capacitance of the selected word line through the buffer circuit, and can generate the first unselected word line voltage and the first selected word line voltage without a frequency compensation capacitor, thereby realizing programming and erasing of the memory array. Since the capacitance value of the frequency compensation capacitor is very large, the larger the capacitance value, the larger the area occupied by the capacitor. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiments of the present disclosure is smaller.

[0008] The above general description and the following description are only exemplary and explanatory, and are not used to limit the present application. Description of the Drawings

[0009] One or more embodiments are illustrated by way of example in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation, and wherein:

[0010] Figure 1 is a schematic structural diagram of a word line voltage generation circuit provided by an embodiment of the present disclosure;

[0011] Figure 2 is a schematic structural diagram of a second word line voltage generation circuit provided by an embodiment of the present disclosure;

[0012] Figure 3 is a schematic structural diagram of a third word line voltage generation circuit provided by an embodiment of the present disclosure;

[0013] Figure 4 is a schematic structural diagram of a fourth word line voltage generation circuit provided by an embodiment of the present disclosure;

[0014] Figure 5 is a schematic structural diagram of a word line voltage output circuit provided by an embodiment of the present disclosure.

[0015] Reference numerals:

[0016] 1: voltage source generation circuit; 2: buffer circuit; 3: erase / program control voltage and generation circuit; 4: operational amplifier; 5: first PMOS (positive channel Metal Oxide Semiconductor) transistor; 6: first capacitor; 7: first resistor; 8: logic control circuit; 9: second resistor; 10: first NMOS (N-Metal-Oxide-Semiconductor) transistor; 11: third resistor; 12: first transmission gate; 13: second transmission gate; 14: first inverter; 15: second NMOS transistor; 16: second PMOS transistor; 17: third NMOS transistor; 18: third PMOS transistor; 19: level-shift circuit; 20: fourth PMOS transistor; 21: fifth PMOS transistor; 22: sixth PMOS transistor; 23: seventh PMOS transistor; 24: eighth PMOS transistor; 25: fourth NMOS transistor; 26: fifth NMOS transistor; 27: sixth NMOS transistor; 28: seventh NMOS transistor; 29: eighth NMOS transistor; 30: second inverter; 31: second capacitor; 32: unselected word line voltage generation circuit; 33: selected word line voltage generation circuit; 34: memory page (Flash page). Detailed implementation manners

[0017] In order to more comprehensively understand the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are only for reference and explanation, and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, numerous details are provided to give a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be shown in a simplified manner to simplify the drawings.

[0018] In the embodiments of the present disclosure, terms such as "first" and "second" in the specification, claims, and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0019] In the embodiments of the present disclosure, the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "middle", "outer", "front", and "rear" is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and their implementations, and are not used to limit that the indicated devices, elements, or components must have a specific orientation or be constructed and operated in a specific orientation. Moreover, in addition to being able to represent an orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0020] In addition, the terms "arranged", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0021] Unless otherwise specified, the term "plurality" means two or more.

[0022] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0023] The term "and / or" is a description of the association relationship of an object, indicating that there can be three relationships. For example, A and / or B means: A or B, or, A and B these three relationships.

[0024] It should be noted that, without conflict, the embodiments in this disclosure and the features in the embodiments may be combined with each other.

[0025] Combined Figure 1 As shown, an embodiment of the present disclosure provides a word line voltage generation circuit, including a voltage source generation circuit 1, a buffer circuit 2, and an erase / program control voltage and generation circuit 3. The voltage source generation circuit 1 is used to provide a voltage source; one end of the buffer circuit 2 is electrically connected to one end of the voltage source generation circuit 1, and the buffer circuit 2 is used to generate a buffer voltage according to the voltage source; one end of the erase / program control voltage and generation circuit 3 is connected to the other end of the buffer circuit 2, and the other end of the erase / program control voltage and generation circuit 3 is connected to the other end of the voltage source generation circuit 1. The erase / program control voltage and generation circuit 3 is used to generate a first unselected word line voltage according to the drive of the buffer voltage when the erase enable signal is at a high level, and generate a first selected word line voltage according to the drive of the voltage source when the program signal is at a high level.

[0026] By using the word line voltage generation circuit provided in the embodiment of the present disclosure, the voltage source generation circuit provides a voltage source, the buffer circuit generates a buffer voltage according to the voltage source, and the erase / program control voltage and generation circuit generates a first selected word line voltage according to the drive of the voltage source when the program signal is at a high level. Since the first selected word line voltage supplies power to the selected word line, the equivalent capacitance of the selected word line is the same as the load capacitance at the output end of the voltage source generation circuit. The erase / program control voltage and generation circuit generates a first unselected word line voltage according to the drive of the buffer voltage. Since the unselected word line voltage is used to supply power to the unselected word line, the equivalent capacitance of the unselected word line is the same as the load capacitance at the output end of the buffer circuit. The embodiment of the present disclosure isolates the equivalent capacitance of the unselected word line and the equivalent capacitance of the selected word line through the cache circuit, and can generate the first unselected word line voltage and the first selected word line voltage without a frequency compensation capacitor, thereby realizing the programming and erasing of the memory array. Since the capacitance value of the frequency compensation capacitor is very large, the larger the capacitance value, the larger the area occupied by the capacitor. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiment of the present disclosure is smaller.

[0027] In some embodiments, the word line voltage generation circuit is applied to a chip.

[0028] Optionally, when the program enable signal is at a high level, the non-volatile memory performs a programming operation, and the output end of the voltage source generation circuit directly supplies power to the selected word line. When the erase enable signal is at a high level, the non-volatile memory performs an erase operation, and the output end of the voltage source generation circuit supplies power to the unselected word line through the buffer circuit.

[0029] Combined Figure 2As shown, optionally, the voltage source generation circuit 1 includes an operational amplifier 4, a first PMOS transistor 5, a first capacitor 6, a first resistor 7, a logic control circuit 8, and a second resistor 9. The negative input terminal of the operational amplifier 4 is connected to a reference voltage. The positive input terminal of the operational amplifier 4 is connected to one end of the first resistor 7 and the first end of the second resistor 9. The output terminal of the operational amplifier 4 is connected to the gate of the first PMOS transistor 5 and the upper plate of the first capacitor 6. The source of the first PMOS transistor 5 is connected to a first power supply. The drain of the first PMOS transistor 5 is respectively connected to the buffer circuit 2 and the erase programming control voltage and generation circuit 3. The lower plate of the first capacitor 6 is connected to the drain of the first PMOS transistor 5. The other end of the first resistor 7 is connected to the drain of the first PMOS transistor 5. One end of the logic control circuit 8 is connected to an erase enable signal, and the other end of the logic control circuit 8 is connected to the second end of the second resistor 9. The logic control circuit 8 is configured to lower the resistance value of the second resistor 9 when the erase enable signal is at a high level. The third end of the second resistor 9 is grounded.

[0030] The operational amplifier, the first PMOS transistor, and the first resistor form a negative feedback loop. The first PMOS transistor has two poles. The first pole is the gate of the first PMOS transistor, and the second pole is the drain of the first PMOS transistor, that is, the output terminal VD of the voltage source generation circuit. When the erase enable signal is at a high level, the load capacitance at the VD terminal is 1 pF. When the program enable signal is at a high level, the load capacitance at the VD terminal is 0.5 pF. By presetting the size of the first PMOS transistor, the gate of the first PMOS transistor is used as the main pole, and the first capacitor is used as a Miller capacitor to perform frequency compensation on the first PMOS transistor. The equivalent capacitance of the unselected word line and the equivalent capacitance of the selected word line are isolated through the buffer circuit. The equivalent capacitance of the unselected word line is different from the load capacitance at the output terminal of the voltage source generation circuit, and the first unselected word line voltage and the first selected word line voltage can be generated without a frequency compensation capacitor, thereby realizing programming and erasing of the memory array. The capacitance value of the first capacitor is about 2 pF. Compared with the frequency compensation capacitor of 100 - 300 pF in the prior art, the area occupied by the first capacitor is reduced by dozens of times. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiment of the present disclosure is smaller, saving the cost of the chip.

[0031] Combined Figure 2 As shown, optionally, the buffer circuit 2 includes a first NMOS transistor 10 and a third resistor 11. The gate of the first NMOS transistor 10 is respectively connected to the drain of the first PMOS transistor 5 and one end of the erase programming control voltage and generation circuit 3. The source of the first NMOS transistor 10 is connected to a first power supply. The drain of the first NMOS transistor 10 is respectively connected to one end of the third resistor 11 and the other end of the erase programming control voltage and generation circuit 3. The other end of the third resistor 11 is grounded.

[0032] Optionally, the voltage at the output terminal VD_n of the buffer circuit is obtained by calculating VD15_n = VD15 - Vtn; where VD15_n is the voltage at the output terminal of the buffer circuit, that is, VD15_n is the buffer voltage, VD15 is the voltage at the output terminal of the voltage source generation circuit, that is, VD15 is the voltage source, and Vtn is the threshold voltage of the first NMOS transistor.

[0033] Optionally, the voltage at the output terminal of the voltage source generation circuit is obtained by calculating VD15 = VREF * (R2 + R1) / R2; where VD15 is the voltage at the output terminal of the voltage source generation circuit, VREF is the reference voltage, R2 is the resistance value of the second resistor, and R1 is the resistance value of the first resistor.

[0034] In some embodiments, when the erase enable signal is at a high level, the logic control circuit controls the resistance value of the second resistor to decrease, so that the voltage VD15 at the output terminal of the voltage source generation circuit is 1.7V. The first NMOS transistor is a zero-threshold transistor. Considering its body bias effect, the threshold voltage of the first NMOS transistor is a preset value, for example, 0.2V. Then the voltage value of VD15_n at the output terminal of the buffer circuit is 1.5V, so that during the erase operation, the voltage of the first unselected word line is 1.5V. When the program enable signal is at a high level and the erase enable signal is at a low level, the logic control circuit controls the resistance value of the second resistor to increase, so that the voltage at the output terminal of the voltage source generation circuit is 1.5V, and further, during the program operation, the voltage of the first selected word line is 1.5V. The load capacitances of the word line voltage generation circuit during the erase operation and the program operation are very different. Compared with the prior art in which a large frequency compensation capacitor is used to achieve frequency compensation, in the embodiments of the present disclosure, the load capacitance during the program operation and the load capacitance during the erase operation are isolated by the buffer circuit, and at the same time, the voltage source is adjusted by adjusting the resistance value of the second resistor, so as to ensure that the voltage of the first unselected word line during the erase operation and the voltage of the first unselected word line during the program operation are both 1.5V, realizing programming and erasing of the memory array. Since the capacitance value of the frequency compensation capacitor is very large, the larger the capacitance value, the larger the area occupied by the capacitor. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiments of the present disclosure is smaller.

[0035] Combined with Figure 2As shown, optionally, the erase / program control voltage and generation circuit 3 includes an unselected word line voltage generation circuit 32 and a selected word line voltage generation circuit 33. The unselected word line voltage generation circuit 32 is connected to the gate of the first NMOS transistor 10. When the erase enable signal is at a high level, the unselected word line voltage generation circuit 32 generates a first unselected word line voltage according to the drive of the buffer voltage. When the erase enable signal is at a low level, it generates a second unselected word line voltage. The selected word line voltage generation circuit 33 is connected to the drain of the first PMOS transistor 5. When the program enable signal is at a high level, the selected word line voltage generation circuit 33 generates a first selected word line voltage according to the drive of the voltage source. When the program enable signal is at a low level, it generates a second selected word line voltage.

[0036] When the erase enable signal ERASE is at a high level, the unselected word line voltage generation circuit generates a first unselected word line voltage according to the drive of the buffer voltage. At this time, the program enable signal PROG is at a low level, and the selected word line voltage generation circuit generates a second selected word line voltage. Thus, during the erase operation, the equivalent capacitance of the load at the output end of the buffer circuit is the same as the equivalent capacitance of the unselected word line. When the erase enable signal is at a low level, the unselected word line voltage generation circuit generates a second unselected word line voltage. At this time, the program enable signal is at a high level, and the selected word line voltage generation circuit generates a first selected word line voltage according to the drive of the voltage source. Thus, during the program operation, the equivalent capacitance of the load at the output end of the voltage source generation circuit is the same as the equivalent capacitance of the selected word line. Thereby, it is avoided that the load capacitances at the output ends of the voltage source generation circuit are respectively equal to the equivalent capacitances of the selected word line and the unselected word line, resulting in too large a difference in the load capacitances at the output end of the power supply generation circuit. Thus, the first unselected word line voltage and the first selected word line voltage can be generated without the need for a frequency compensation capacitor, realizing the programming and erasing of the memory array. Since the capacitance value of the frequency compensation capacitor is very large, the larger the capacitance value, the larger the area occupied by the capacitor. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiments of the present disclosure is smaller.

[0037] Combined Figure 2 As shown, optionally, the unselected word line voltage generation circuit 3 includes a first transmission gate 12, a second transmission gate 13, and a first inverter 14. The first control terminal of the first transmission gate 12 is connected to the erase enable signal. The input terminal of the first transmission gate 12 is connected to the gate of the first NMOS transistor 10. The second control terminal of the first transmission gate 12 is respectively connected to the output terminal of the first inverter 14 and the first control terminal of the second transmission gate 13. The output terminal of the first transmission gate 12 is connected to the output terminal of the second transmission gate 13. The second control terminal of the second transmission gate 13 is connected to the enable control signal. The input terminal of the second transmission gate 13 is grounded. The input terminal of the first inverter 14 is connected to the enable control signal.

[0038] In some embodiments, the connection node between the output terminal of the first transmission gate and the output terminal of the second transmission gate is the low-potential bias voltage terminal XDBIAS. When the erase enable signal is at a high level, the first transmission gate is turned on and the second transmission gate is turned off. The output terminal of the buffer circuit is connected to the low-potential bias voltage terminal through the first transmission gate, and the low-potential bias voltage terminal generates the first unselected word line voltage. When the erase enable signal is at a low level, the first transmission gate is turned off and the second transmission gate is turned on, and the low-potential bias voltage terminal is grounded, and the low-potential bias voltage terminal generates the second unselected word line voltage. The first unselected word line voltage is generated according to the drive of the buffer voltage. Since the unselected word line voltage is used to supply power to the unselected word line, the equivalent capacitance of the unselected word line is the same as the load capacitance of the output terminal of the buffer circuit, so that the buffer circuit isolates the equivalent capacitance of the unselected word line and the equivalent capacitance of the selected word line, and the first unselected word line voltage can be generated without a frequency compensation capacitor, thereby realizing the programming and erasing of the memory array. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiments of the present disclosure is smaller.

[0039] Combined with Figure 3 As shown, optionally, the first transmission gate 12 includes a second NMOS transistor 15 and a second PMOS transistor 16. The gate of the second NMOS transistor 15 is connected to the erase enable signal. The drain of the second NMOS transistor 15 is respectively connected to the source of the second PMOS transistor 16 and the gate of the first NMOS transistor 10. The source of the second NMOS transistor 15 is respectively connected to the drain of the second PMOS transistor 16 and the output terminal of the second transmission gate 13. The gate of the second PMOS transistor 16 is respectively connected to the output terminal of the first inverter 14 and the first control terminal of the second transmission gate 13.

[0040] When the erase enable signal is at a high level, both the second NMOS transistor and the second PMOS transistor are turned on. The output terminal of the buffer circuit is connected to the low-potential bias voltage terminal through the first transmission gate. At this time, the voltage of the low-potential bias voltage terminal is 1.5V. When the erase enable signal is at a low level, both the second NMOS transistor and the second PMOS transistor are turned off.

[0041] Optionally, the second transmission gate 13 includes a third NMOS transistor 17 and a third PMOS transistor 18. The gate of the third NMOS transistor 17 is respectively connected to the output terminal of the first inverter 14 and the second control terminal of the first transmission gate 12. The source of the third NMOS transistor 17 is respectively connected to the drain of the third PMOS transistor 18 and the output terminal of the first transmission gate 12. The drain of the third NMOS transistor 17 is grounded. The gate of the third PMOS transistor 18 is respectively connected to the input terminal of the first inverter 14 and the erase enable signal. The source of the third PMOS transistor 18 is grounded.

[0042] When the erase enable signal is at a high level, both the third NMOS transistor and the third PMOS transistor are turned off. When the erase enable signal is at a low level, both the second NMOS transistor and the second PMOS transistor are turned on, and the low potential bias voltage terminal is grounded. At this time, the voltage of the low potential bias voltage terminal is 0V.

[0043] Combined with Figure 4 As shown, optionally, the selected word line voltage generation circuit 33 includes a level shift circuit 19, a fourth PMOS transistor 20, and a fifth PMOS transistor 21. The first terminal of the level shift circuit 19 is connected to the programming enable signal, the second terminal of the level shift circuit 19 is connected to the second power supply, the third terminal of the level shift circuit 19 is connected to the gate of the fourth PMOS transistor 20, and the fourth terminal of the level shift circuit 19 is connected to the gate of the fifth PMOS transistor 21; the source of the fourth PMOS transistor 20 is connected to the second power supply, and the drain of the fourth PMOS transistor 20 is connected to the drain of the fifth PMOS transistor 21; the source of the fifth PMOS transistor 21 is connected to the drain of the first PMOS transistor 5.

[0044] Optionally, the level shift circuit is used to convert a logic signal in a low voltage domain into a logic signal in a high voltage domain. The second power supply is used to provide a preset voltage. Optionally, the preset voltage is 12V.

[0045] In some embodiments, the connection node between the drain of the fourth PMOS transistor and the drain of the fifth PMOS transistor is the high-potential bias voltage terminal HVWL. The stable output voltage value at the output terminal of the voltage source generation circuit is 1.5V. When the programming enable signal is at a high level, the fifth PMOS transistor is turned on, the fourth PMOS transistor is turned off, and the voltage source generation circuit output terminal transmits the voltage source to the high-potential bias voltage terminal. At this time, the erase enable signal is at a low level, the first transmission gate is turned off, the second transmission gate is turned on, and the low-potential bias voltage terminal XDBIAS is grounded. Thus, during the programming operation, the equivalent capacitance of the load at the output terminal of the voltage source generation circuit is equal to the equivalent capacitance of the selected word line, which is 0.5pF. When the programming enable signal is at a low level, the fifth PMOS transistor is turned off, the fourth PMOS transistor is turned on, and the second power supply outputs a preset voltage to the high-potential bias voltage terminal. At this time, the erase enable signal is at a high level, the first transmission gate is turned on, the second transmission gate is turned off, and the buffer circuit output terminal transmits the buffer voltage to the low-potential bias voltage terminal. The equivalent capacitance of the load at the buffer circuit output terminal is equal to the equivalent capacitance of the unselected word line, which is 32nF. At this time, the load capacitance at the output terminal of the voltage source generation circuit is only the parasitic capacitance mainly formed by the gate of the first NMOS transistor, and this parasitic capacitance is less than 1pF. Thus, during the erase operation, the equivalent capacitance of the load at the output terminal of the voltage source generation circuit is less than 1pF. In this way, during the programming operation and the erase operation, the load capacitance at the output terminal of the voltage source generation circuit is less than 1pF. Therefore, there is no need for a frequency compensation capacitor at the output terminal of the voltage source generation circuit. Since the capacitance value of the frequency compensation capacitor is very large, the larger the capacitance value, the larger the area occupied by the capacitor. Therefore, the chip area of the word line voltage generation circuit and the memory applying the embodiments of the present disclosure is smaller.

[0046] When the erase enable signal ERASE is at a high level, the unselected word line voltage generation circuit generates a first unselected word line voltage according to the drive of the buffer voltage, and uses the first unselected word line voltage to provide a bias voltage for the unselected word line (WL_unsel). At this time, the programming enable signal PROG is at a low level, and the selected word line voltage generation circuit generates a second selected word line voltage, and uses the second selected word line voltage to provide a bias voltage for the selected word line (WL_sel). When the erase enable signal is at a low level, the unselected word line voltage generation circuit generates a second unselected word line voltage, and uses the second unselected word line voltage to provide a bias voltage for the unselected word line. At this time, the programming enable signal is at a high level, and the selected word line voltage generation circuit generates a first selected word line voltage according to the drive of the voltage source, and uses the first selected word line voltage to provide a bias voltage for the selected word line.

[0047] In some embodiments, Table 1 is an example table of a bias voltage meter. As shown in Table 1, when the programming enable signal is at a high level, i.e., programming is effective, the bias voltage of the unselected word line (WL_unsel) is 0V, and the bias voltage of the selected word line (WL_sel) is 1.5V; when the erase enable signal is at a high level, i.e., erase is effective, the bias voltage of the unselected word line (WL_unsel) is 1.5V, and the bias voltage of the selected word line (WL_sel) is 12V.

[0048] WL_unsel WL_sel Programming valid 0V 1.5V Erasing valid 1.5V 12V

[0049] Table 1

[0050] An embodiment of the present disclosure provides a memory, including a word line voltage output circuit and the word line voltage generation circuit as described above. The word line voltage output circuit is connected to the word line voltage generation circuit and is configured to generate an output word line voltage according to the selected word line voltage and the unselected word line voltage. The word line voltage generation circuit provides a voltage source through a voltage source generation circuit. The buffer circuit generates a buffer voltage according to the voltage source. Then, the write-erase programming control voltage and generation circuit generates a first selected word line voltage according to the drive of the voltage source and generates a first unselected word line voltage according to the drive of the buffer voltage. The word line voltage output circuit generates an output word line voltage according to the first selected word line voltage and the first unselected word line voltage. The output word line voltage is used to select the operation of outputting a memory page. By isolating the equivalent capacitance of the unselected word line and the equivalent capacitance of the selected word line through the cache circuit, the first unselected word line voltage and the first selected word line voltage can be generated without a frequency compensation capacitor, thereby realizing programming and erasing of the memory array. Since the capacitance value of the frequency compensation capacitor is very large, the larger the capacitance value, the larger the area occupied by the capacitor. Therefore, the chip area of the memory applying the embodiment of the present disclosure is smaller.

[0051] Combined with Figure 5As shown, optionally, the word line voltage output circuit includes a sixth PMOS transistor 22, a seventh PMOS transistor 23, an eighth PMOS transistor 24, a fourth NMOS transistor 25, a fifth NMOS transistor 26, a sixth NMOS transistor 27, a seventh NMOS transistor 28, an eighth NMOS transistor 29, a second inverter 30 and a second capacitor 31. The source of the sixth PMOS transistor 22 is respectively connected to one end of the word line voltage generation circuit and the source of the eighth PMOS transistor 24. The drain of the sixth PMOS transistor 22 is respectively connected to the drain of the fourth NMOS transistor 25, the drain of the fifth NMOS transistor 26, the gate of the seventh PMOS transistor 23 and the gate of the sixth NMOS transistor 27. The gate of the sixth PMOS transistor 22 is respectively connected to the gate of the fifth NMOS transistor 26, the drain of the seventh PMOS transistor 23, the drain of the sixth NMOS transistor 27, the drain of the seventh NMOS transistor 28, the gate of the eighth PMOS transistor 24 and the gate of the eighth NMOS transistor 29. The source of the seventh PMOS transistor 23 is connected to one end of the word line voltage generation circuit. The drain of the eighth PMOS transistor 24 is respectively connected to the drain of the eighth NMOS transistor 29, the memory page 34 and the upper plate of the second capacitor 31. The source of the fourth NMOS transistor 25 is connected to the other end of the word line voltage generation circuit, and the gate of the fourth NMOS transistor 25 is connected to the row address signal X1. The source of the fifth NMOS transistor 26 is connected to the other end of the word line voltage generation circuit. The source of the sixth NMOS transistor 27 is connected to the other end of the word line voltage generation circuit. The source of the seventh NMOS transistor 28 is connected to the other end of the word line voltage generation circuit, and the gate of the seventh NMOS transistor 28 is connected to the output end of the second inverter 30. The source of the eighth NMOS transistor 29 is connected to the other end of the word line voltage generation circuit. The input end of the second inverter 30 is connected to the row address signal X1. The lower plate of the second capacitor 31 is grounded.

[0052] Optionally, one end of the word line voltage generation circuit is the high potential bias voltage terminal HVWL of the word line voltage generation circuit, that is, the connection node between the drain of the fourth PMOS transistor and the drain of the fifth PMOS transistor is respectively connected to the source of the sixth PMOS transistor and the source of the eighth PMOS transistor.

[0053] Optionally, the other end of the word line voltage generation circuit is the low potential bias voltage terminal XDBIAS of the word line voltage generation circuit, that is, the connection node between the output end of the first transmission gate and the output end of the second transmission gate is respectively connected to the sources of the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor.

[0054] The above description and the drawings sufficiently illustrate embodiments of the present disclosure such that those skilled in the art can practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A word line voltage generating circuit, characterized in that, Comprising: A voltage source generation circuit for providing a voltage source; A buffer circuit, one end of which is electrically connected to one end of the voltage source generation circuit, and the buffer circuit is used to generate a buffer voltage according to the voltage source; An erase and program control voltage and generation circuit, one end of which is connected to the other end of the buffer circuit, and the other end of the erase and program control voltage and generation circuit is connected to the other end of the voltage source generation circuit. The erase and program control voltage and generation circuit is used to generate a first unselected word line voltage according to the drive of the buffer voltage when the erase enable signal is at a high level, and generate a first selected word line voltage according to the drive of the voltage source when the program enable signal is at a high level; The voltage source generation circuit includes: an operational amplifier, the negative input terminal of which is connected to a reference voltage, the positive input terminal of the operational amplifier is connected to one end of a first resistor and the first end of a second resistor, and the output terminal of the operational amplifier is connected to the gate of a first PMOS transistor and the upper plate of a first capacitor; the first PMOS transistor, the source of which is connected to a first power supply, and the drain of the first PMOS transistor is respectively connected to the buffer circuit and the erase and program control voltage and generation circuit; the first capacitor, the lower plate of which is connected to the drain of the first PMOS transistor; the first resistor, the other end of which is connected to the drain of the first PMOS transistor; A logic control circuit, one end of which is connected to the erase enable signal, and the other end of the logic control circuit is connected to the second end of the second resistor. The logic control circuit is used to reduce the resistance value of the second resistor when the erase enable signal is at a high level; the second resistor, the third end of which is grounded.

2. The word line voltage generation circuit according to claim 1, wherein The buffer circuit includes: A first NMOS transistor, the gate of which is respectively connected to one end of the voltage source generation circuit and the erase and program control voltage and generation circuit, the source of the first NMOS transistor is connected to a first power supply, and the drain of the first NMOS transistor is respectively connected to one end of a third resistor and the other end of the erase and program control voltage and generation circuit; The third resistor, the other end of which is grounded.

3. The word line voltage generation circuit according to claim 1, wherein The erase and program control voltage and generation circuit includes: An unselected word line voltage generation circuit, connected to the buffer circuit. The unselected word line voltage generation circuit generates a first unselected word line voltage according to the drive of the buffer voltage when the erase enable signal is at a high level, and generates a second unselected word line voltage when the erase enable signal is at a low level; A selected word line voltage generation circuit, connected to the voltage source generation circuit. The selected word line voltage generation circuit generates a first selected word line voltage according to the drive of the voltage source when the program enable signal is at a high level; and generates a second selected word line voltage when the program enable signal is at a low level.

4. The word line voltage generation circuit according to claim 3, wherein, The unselected word line voltage generation circuit includes: A first transmission gate, the first control terminal of which is connected to the erase enable signal, the input terminal of the first transmission gate is connected to the buffer circuit, the second control terminal of the first transmission gate is respectively connected to the output terminal of a first inverter and the first control terminal of a second transmission gate, and the output terminal of the first transmission gate is connected to the output terminal of the second transmission gate; The second transmission gate has its second control terminal connected to an enable control signal, and the input terminal of the second transmission gate is grounded. A first inverter has its input terminal connected to the enable control signal.

5. The word line voltage generation circuit according to claim 4, characterized in that, The first transmission gate includes: A second NMOS transistor, with its gate connected to the erase enable signal. The drain of the second NMOS transistor is respectively connected to the source of a second PMOS transistor and the buffer circuit, and the source of the second NMOS transistor is respectively connected to the drain of the second PMOS transistor and the output terminal of the second transmission gate. The second PMOS transistor has its gate respectively connected to the output terminal of the first inverter and the first control terminal of the second transmission gate.

6. The word line voltage generating circuit according to claim 4, wherein The second transmission gate includes: A third NMOS transistor, with its gate respectively connected to the output terminal of the first inverter and the second control terminal of the first transmission gate. The source of the third NMOS transistor is respectively connected to the drain of a third PMOS transistor and the output terminal of the first transmission gate, and the drain of the third NMOS transistor is grounded. The third PMOS transistor has its gate respectively connected to the input terminal of the first inverter and the erase enable signal, and the source of the third PMOS transistor is grounded.

7. The word line voltage generation circuit according to claim 3, wherein The selected word line voltage generation circuit includes: A level shift circuit, with its first terminal connected to the program enable signal, its second terminal connected to a second power supply, its third terminal connected to the gate of a fourth PMOS transistor, and its fourth terminal connected to the gate of a fifth PMOS transistor. The fourth PMOS transistor has its source connected to the second power supply, and its drain connected to the drain of the fifth PMOS transistor. The fifth PMOS transistor has its source connected to the voltage source generation circuit.

8. A memory, characterized in that, It includes a word line voltage output circuit and the word line voltage generation circuit according to any one of claims 1 to 7. The word line voltage output circuit is connected to the word line voltage generation circuit, and the word line voltage output circuit is used to generate an output word line voltage based on the selected word line voltage and the unselected word line voltage.

9. The memory according to claim 8, wherein, The word line voltage output circuit includes: A sixth PMOS transistor, with its source respectively connected to the first terminal of the word line voltage generation circuit and the source of an eighth PMOS transistor. The drain of the sixth PMOS transistor is respectively connected to the drain of a fourth NMOS transistor, the drain of a fifth NMOS transistor, the gate of a seventh PMOS transistor, and the gate of a sixth NMOS transistor. The gate of the sixth PMOS transistor is respectively connected to the gate of the fifth NMOS transistor, the drain of the seventh PMOS transistor, the drain of the sixth NMOS transistor, the drain of a seventh NMOS transistor, the gate of the eighth PMOS transistor, and the gate of an eighth NMOS transistor. The seventh PMOS transistor has its source connected to one end of the word line voltage generation circuit. The eighth PMOS transistor has its drain respectively connected to the drain of the eighth NMOS transistor, the memory page, and the upper plate of a second capacitor. The fourth NMOS transistor has its source connected to the other end of the word line voltage generation circuit, and its gate connected to the row address signal. The fifth NMOS transistor has its source connected to the other end of the word line voltage generation circuit. The source of the sixth NMOS transistor is connected to the other end of the word line voltage generation circuit; The source of the seventh NMOS transistor is connected to the other end of the word line voltage generation circuit, and the gate of the seventh NMOS transistor is connected to the output end of the second inverter; The source of the eighth NMOS transistor is connected to the other end of the word line voltage generation circuit; The input end of the second inverter is connected to the row address signal; For the second capacitor, the lower plate is grounded.

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