Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, wherein a passivation layer is first formed, the passivation layer covers the side wall and top of the conductive layer and the semiconductor substrate, the passivation layer can protect the conductive layer and the semiconductor substrate, and prevent dust or water vapor, etc.; then, a sidewall material layer is formed on the passivation layer, the sidewall material layer covers the passivation layer, and then the sidewall material layer is etched to remove the sidewall material layer on the semiconductor substrate and the sidewall material layer on the top of the conductive layer, and the sidewall material layer on the sidewall of the conductive layer is retained to form a sidewall layer, the sidewall layer can play a role in supporting the conductive layer, and prevent the conductive layer from collapsing or tilting in a high temperature environment. Compared with the prior art, in the process of etching the passivation layer, the over-etching amount of the passivation layer is less, which can avoid damaging the conductive layer below the passivation layer, thereby avoiding plasma damage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor manufacturing technology, a pad structure is usually prepared on a wafer so as to realize the bonding of the wafer with other components based on the pad structure. In the process of preparing the pad structure, a conductive layer is usually formed first, and then a passivation layer is formed on the conductive layer, and the passivation layer is etched to form an opening to expose the conductive layer, and then the conductive layer is led out by filling the opening with a conductive material to form a pad structure.

[0003] In order to prevent the conductive layer from collapsing under high temperature environment, the thickness of the passivation layer on the side wall of the conductive layer needs to be greater than the thickness of the passivation layer on the top of the conductive layer to prevent the conductive layer from collapsing. The passivation layer is usually formed by first forming a thicker passivation layer around the conductive layer, and then thinning the passivation layer on the top of the conductive layer through a chemical mechanical polishing process. Due to the polishing characteristics of the chemical mechanical polishing process itself, after chemical mechanical polishing, the passivation layer on the top of the conductive layer is unevenly distributed (part of the passivation layer is thicker, and the other part of the passivation layer is thinner).

[0004] In the subsequent process of etching the passivation layer, a plasma process is usually used to etch the passivation layer. However, due to the non-uniformity of the passivation layer, the passivation layer in the thicker area will accumulate more plasma charges. The plasma charges generated during the etching process will be transferred to the gate of the device (located below the conductive layer) through the conductive layer, and a gate leakage current will be formed on the gate oxide layer between the gate and the substrate. When the accumulated charge exceeds a certain amount, this gate leakage current will damage the gate oxide layer, thereby seriously reducing the reliability and life of the device or even the entire chip. In addition, the accumulated plasma charge will cause an arc on the substrate surface in the subsequent process (for example, when a high voltage difference is formed between local areas), thereby breaking through the substrate surface, destroying the film layer on the substrate surface, and even causing device failure. Therefore, a new method for manufacturing a semiconductor device is needed to improve the plasma damage generated during the etching process of the passivation layer. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem of plasma damage and arc discharge damage to the substrate.

[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a semiconductor substrate, on which a plurality of discrete conductive layers are formed, and the semiconductor substrate is exposed between two adjacent conductive layers;

[0008] forming a passivation layer, the passivation layer covering the sidewall and top of the conductive layer and the semiconductor substrate, the thickness of the passivation layer on the sidewall of the conductive layer being the same as the thickness of the passivation layer on the top of the conductive layer;

[0009] forming a spacer material layer on the passivation layer, wherein the spacer material layer covers the passivation layer;

[0010] Etching the spacer material layer, removing the spacer material layer at the conductive top to expose the passivation layer at the conductive layer top, and removing the spacer material layer on the semiconductor substrate and retaining the spacer material layer at the conductive layer sidewall to form a spacer layer; and,

[0011] The passivation layer on top of the conductive layer is etched to form an opening exposing the conductive layer.

[0012] Optionally, in the method for manufacturing the semiconductor device, the passivation layer includes a first passivation layer and a second passivation layer covering the first passivation layer, and a material of the first passivation layer is different from a material of the second passivation layer.

[0013] Optionally, in the manufacturing method of the semiconductor device, the material of the first passivation layer is silicon oxide, and the first passivation layer is formed by plasma enhanced chemical vapor deposition; the material of the second passivation layer is silicon nitride and / or silicon nitride oxide, and the second passivation layer is formed by heat treatment.

[0014] Optionally, in the method for manufacturing a semiconductor device, the thickness of the first passivation layer is 0.8 μm to 1 μm, and the thickness of the second passivation layer is 0.25 μm to 0.35 μm.

[0015] Optionally, in the method for manufacturing the semiconductor device, the spacer material layer includes a first spacer material layer and a second spacer material layer, and the first spacer material layer and the second spacer material layer are made of different materials.

[0016] Optionally, in the manufacturing method of the semiconductor device, the material of the first sidewall material layer is silicon oxide, and the first sidewall material layer is formed by a low-pressure chemical vapor deposition process or an atomic layer deposition process; the material of the second sidewall material layer is silicon nitride, and the second sidewall material layer is formed by a low-pressure chemical vapor deposition process.

[0017] Optionally, in the method for manufacturing the semiconductor device, the thickness of the first spacer material layer is 1 μm to 1.5 μm, and the thickness of the second spacer material layer is 1 μm to 1.5 μm.

[0018] Optionally, in the method for manufacturing the semiconductor device, the method for etching the spacer material layer includes:

[0019] The first spacer material layer and the second spacer material layer are etched by a plasma etching process to remove the first spacer material layer and the second spacer material layer on the semiconductor substrate, and to remove the first spacer material layer and the second spacer material layer on the top of the conductive layer, and to retain the first spacer material layer on the side wall of the conductive layer to form a first spacer layer, and to retain the second spacer material layer on the side wall of the conductive layer to form a second spacer layer, wherein the spacer layer includes the first spacer layer and the second spacer layer.

[0020] Optionally, in the method for manufacturing the semiconductor device, the conductive layer is made of at least one of aluminum, copper, titanium, nickel, aluminum nitride, titanium nitride and nickel nitride.

[0021] Based on the same inventive concept, the present invention further provides a semiconductor device, comprising:

[0022] Semiconductor substrate;

[0023] A plurality of discrete conductive layers are formed on the semiconductor substrate and cover a portion of the semiconductor substrate;

[0024] a passivation layer, covering the sidewalls and top of the conductive layer and the semiconductor substrate, wherein the passivation layer has an opening exposing the conductive layer;

[0025] The sidewall layer covers the passivation layer on the sidewall of the conductive layer.

[0026] In the semiconductor device and the manufacturing method thereof provided by the present invention, a passivation layer is first formed, the passivation layer covers the side wall and the top of the conductive layer and the semiconductor substrate, and the passivation layer can protect the conductive layer and the semiconductor substrate from dust or water vapor, etc.; then, a sidewall material layer is formed on the passivation layer, and the sidewall material layer covers the passivation layer. Then, the sidewall material layer is etched to remove the sidewall material layer at the conductive top to expose the passivation layer at the top of the conductive layer, and to remove the sidewall material layer on the semiconductor substrate and retain the sidewall material layer on the sidewall of the conductive layer to form a sidewall layer. The sidewall layer can support the conductive layer to prevent the conductive layer from collapsing or tilting in a high temperature environment. Since the sidewall layer can support the conductive layer, it is not necessary to make the thickness of the passivation layer on the sidewall of the conductive layer greater than the thickness of the passivation layer on the top of the conductive layer, so there is no need to thin the passivation layer. Compared with the prior art, in the process of etching the passivation layer, the over-etching amount of the passivation layer is less, which can avoid damaging the conductive layer below the passivation layer, thereby avoiding plasma damage, and reducing the probability of arc discharge damaging the substrate, thereby improving the reliability of the device. In addition, in the process of etching the sidewall material layer, the passivation layer can be used as an etching stop layer to avoid over-etching and damaging the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0028] Figures 2 to 6 is a schematic diagram of a structure formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] The reference numerals are described as follows:

[0030] 100 - semiconductor substrate; 101 - conductive layer; 110 - passivation layer; 110a - opening; 111 - first passivation layer; 112 - second passivation layer; 120 - sidewall material layer; 120a - sidewall layer; 121 - first sidewall material layer; 121a - first sidewall layer; 122 - second sidewall material layer; 122a - second sidewall layer. DETAILED DESCRIPTION

[0031] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0032] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1As shown, this embodiment provides a method for manufacturing a semiconductor device, and the method for manufacturing a semiconductor device includes:

[0033] Step S1: providing a semiconductor substrate, on which a plurality of discrete conductive layers are formed, and the semiconductor substrate is exposed between two adjacent conductive layers;

[0034] Step S2: forming a passivation layer, wherein the passivation layer covers the sidewalls and the top of the conductive layer and the semiconductor substrate, and the thickness of the passivation layer on the sidewalls of the conductive layer is the same as the thickness of the passivation layer on the top of the conductive layer;

[0035] Step S3: forming a spacer material layer on the passivation layer, wherein the spacer material layer covers the passivation layer;

[0036] Step S4: etching the spacer material layer, removing the spacer material layer at the conductive top to expose the passivation layer at the conductive layer top, and removing the spacer material layer on the semiconductor substrate and retaining the spacer material layer at the conductive layer sidewall to form a spacer layer; and,

[0037] Step S5: etching the passivation layer on the top of the conductive layer to form an opening exposing the conductive layer.

[0038] Figures 2 to 6 FIG. 1 is a schematic diagram of a structure formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 2 to 6 The above steps are explained in more detail.

[0039] First, if Figure 2 As shown, step S1 is performed to provide a semiconductor substrate 100, on which a plurality of discrete conductive layers 101 are formed, and the semiconductor substrate 100 is exposed between two adjacent conductive layers 101. The semiconductor substrate 100 may be a silicon substrate. In this embodiment, the material of the conductive layer 101 may be aluminum. In other embodiments, the material of the conductive layer 101 may be one or a combination of at least two of copper, titanium, nickel, aluminum nitride, titanium nitride and nickel nitride. The conductive layer 101 may be formed by sputtering.

[0040] In this embodiment, the conductive layer may be formed by vacuum evaporation, sputtering or ion plating. Vacuum evaporation is to heat and evaporate the metal material to be evaporated in a vacuum chamber, so that the evaporated atoms or atomic groups condense on the semiconductor substrate 100 at a relatively low temperature to form the conductive layer 101. Sputtering is to use charged ions to obtain sufficient energy under the action of an electromagnetic field to bombard the surface of a solid target material (i.e., a conductive material). The plasma sputtered from the target surface is ejected toward the surface of the semiconductor substrate 100 with a certain kinetic energy to form the conductive layer 101 on the semiconductor substrate 100. Ion plating is to use gas discharge under vacuum conditions to partially ionize the gas or evaporated substance. While the gas ions or evaporated substance particles are bombarded, the evaporated substance or its reactant is deposited on the semiconductor substrate 100 to form the conductive layer 101.

[0041] Then, if Figure 3 As shown, step S2 is performed to form a passivation layer 110, the passivation layer 110 covers the sidewalls and the top of the conductive layer 101 and the semiconductor substrate 100, and the thickness a of the passivation layer 110 on the sidewalls of the conductive layer 101 is the same as the thickness b of the passivation layer 110 on the top of the conductive layer 101. The passivation layer 110 can protect the conductive layer 101 and the semiconductor substrate 100 from dust or water vapor.

[0042] In this embodiment, the passivation layer 110 includes a first passivation layer 111 and a second passivation layer 112 covering the first passivation layer 111, and the material of the first passivation layer 111 is different from the material of the second passivation layer 112. Among them, the material of the first passivation layer 111 is silicon oxide, and the first passivation layer 111 is formed by plasma enhanced chemical vapor deposition. The material of the second passivation layer 112 is silicon nitride and / or silicon oxynitride, and the second passivation layer 112 is formed by heat treatment. In this embodiment, the passivation layer 110 has better thermodynamic and mechanical properties than a single layer, and can absorb and offset the mechanical stress and thermal stress acting on the conductive layer 101 during the packaging process, ensuring that the various stresses generated during packaging will not cause mechanical damage to the conductive layer 101. However, the present invention is not limited to this, and those skilled in the art can select the material of the passivation layer 110 as needed.

[0043] In this embodiment, the thickness of the first passivation layer 111 is 0.8 μm to 1 μm, and the thickness of the second passivation layer 112 is 0.25 μm to 0.35 μm.

[0044] Then, if Figure 4As shown, step S3 is performed to form a spacer material layer 120 on the passivation layer 110, and the spacer material layer 120 covers the passivation layer 110. The spacer material layer 120 includes a first spacer material layer 121 and a second spacer material layer 122, and the first spacer material layer 121 and the second spacer material layer 122 are made of different materials. The thickness of the first spacer material layer is 1 μm to 1.5 μm, and the thickness of the second spacer material layer is 1 μm to 1.5 μm.

[0045] In this embodiment, the material of the first sidewall material layer 121 is silicon oxide, and the first sidewall material layer 121 is formed by a low-pressure chemical vapor deposition process or an atomic layer deposition process. The low-pressure chemical vapor deposition process refers to using tetraethyl orthosilicate (TEOS) in a process chamber of a low-pressure chemical vapor deposition machine at a low pressure temperature of 650°C to 750°C, preferably using a temperature of 650°C, so that the temperature of the low-pressure chemical vapor deposition process is lower than the melting point of the conductive layer 101 to avoid deformation of the conductive layer 101. The low-pressure chemical vapor deposition process thermally decomposes tetraethyl orthosilicate, and oxygen is added to the process chamber to decompose the gas and diffuse rapidly on the surface of the conductive layer 101, thereby forming the first sidewall material layer 121. The atomic layer deposition process is to form the first sidewall material layer 121 by alternately passing a gas-phase precursor into a reaction chamber in pulses and causing a gas-solid chemical adsorption reaction on the surface of the conductive layer 101. In this embodiment, the first sidewall material layer 121 formed by the low pressure chemical vapor deposition process is preferably used. The first sidewall material layer 121 formed by the low pressure chemical vapor deposition process has good uniformity and can provide a good process surface for the second sidewall material layer 122 .

[0046] The material of the second spacer material layer 122 is silicon nitride, and the second spacer material layer 122 is formed by a low-pressure chemical vapor deposition process. Specifically, under the conditions of reduced pressure and a temperature of 700°C to 750°C, dichlorosilane (SiCl2H2) and ammonia (NH3) are used to form the second spacer material layer 122. In the process of forming the second spacer material layer 122, the temperature used is preferably 700°C to reduce the deformation of the conductive layer 101. Since the conductive layer 101 is covered by the first spacer material layer 121, based on this, in the process of forming the second spacer material layer 122, the conductive layer 101 can be prevented from collapsing or tilting at high temperature.

[0047] Furthermore, in the present embodiment, the side wall material layer 120 adopts a stacked structure of a first side wall material layer 121 and a second side wall material layer 122, which has better supporting performance and better thermal insulation performance than a single-layer side wall material layer 120. In a high temperature environment (for example, an environment greater than the melting point of the conductive layer 101), it can isolate the conductive layer 101 from the external high temperature environment and reduce the deformation of the conductive layer 101 in the high temperature environment.

[0048] Then, if Figure 5 As shown, step S4 is performed to etch the spacer material layer 120, remove the spacer material layer 120 on the top of the conductive layer 101 to expose the passivation layer 110 on the top of the conductive layer 101, and remove the spacer material layer 120 on the semiconductor substrate 100, and retain the spacer material layer 120 on the side wall of the conductive layer 101 to form a spacer layer 120a. Specifically, the method for etching the spacer material layer 120 includes: etching the first spacer material layer 121 and the second spacer material layer 122 by a plasma etching process to remove the first spacer material layer 121 and the second spacer material layer 122 on the semiconductor substrate 100, and removing the first spacer material layer 121 and the second spacer material layer 122 on the top of the conductive layer 101, and retaining the first spacer material layer 121 on the side wall of the conductive layer 101 to form a first spacer layer 121a, and retaining the second spacer material layer 122 on the side wall of the conductive layer 101 to form a second spacer layer 122a, wherein the spacer layer 120a includes the first spacer layer 121a and the second spacer layer 122a. The spacer layer 120a can support the conductive layer to prevent the conductive layer from collapsing or tilting in a high temperature environment.

[0049] In this embodiment, the etching gas for etching the spacer material layer 120 may include, for example, carbon tetrafluoride (CF4), trifluoromethane (CHF3) and oxygen (O2).

[0050] Then, if Figure 6As shown, step S5 is performed to etch the passivation layer 110 on the top of the conductive layer 101 to form an opening 110a exposing the conductive layer 101. In this embodiment, since the sidewall layer 120 can support the conductive layer 101, it is not necessary to make the thickness of the passivation layer 110 on the sidewall of the conductive layer 101 greater than the thickness of the passivation layer 110 on the top of the conductive layer 101. After the passivation layer 110 is formed, it is not necessary to thin the passivation layer 110. Compared with the prior art, in the process of etching the passivation layer 110 on the top of the conductive layer 101, the over-etching amount of the passivation layer 110 is less, which can avoid damaging the conductive layer 101 below the passivation layer 110, thereby avoiding plasma damage, reducing the probability of arc discharge damaging the substrate, and improving the reliability of the device. In addition, during the etching process of the spacer material layer 120 , the passivation layer 110 can be used as an etching stop layer to stop the etching at the top surface of the passivation layer 110 , thereby avoiding over-etching and damaging the conductive layer 101 .

[0051] Specifically, the method for etching the passivation layer 110 includes: first, forming a patterned photoresist layer (not shown) on the passivation layer 110, wherein the patterned photoresist layer has a photoresist opening, and the photoresist opening is aligned with the conductive layer 101; then, using the patterned photoresist layer as a mask, etching the passivation layer 110 in the photoresist opening to form an opening, wherein the opening exposes the conductive layer, and then a conductive material can be filled in the opening to lead out the conductive layer to form a pad structure.

[0052] In this embodiment, the passivation layer 110 can be etched by a plasma etching process, and the etching gases used include carbon tetrafluoride (CF4), trifluoromethane (CHF3) and oxygen (O2), the flow rate of the carbon tetrafluoride is 100sccm~150sccm, the flow rate of the oxygen is 20sccm~40sccm, the flow rate of the trifluoromethane is 160sccm~200sccm, the pressure in the process chamber is 20mTorr~80mTorr, the RF power is 100W~500W, and the etching time is 10s~70s.

[0053] like Figure 6As shown, based on the same inventive concept, the present invention also provides a semiconductor device, the semiconductor device comprising: a semiconductor substrate 100; a plurality of discrete conductive layers 101 formed on the semiconductor substrate 100 and covering a portion of the semiconductor substrate 100; a passivation layer 110 covering the sidewalls and top of the conductive layer 101 and the semiconductor substrate 100; a sidewall layer 120a covering the passivation layer 110 located on the sidewalls of the conductive layer 101. The sidewall layer 120a can support the conductive layer 101 on both sides of the conductive layer 101 to prevent the conductive layer 101 from tilting, breaking and collapsing in a high temperature environment. In addition, the sidewall layer 120a can also achieve isolation between the conductive layers 101 and reduce leakage between the conductive layers 101. The spacer layer 120a includes a first spacer layer 121a and a second spacer layer 122a covering the first spacer layer 121a. The material of the first spacer layer 121a may be silicon oxide, and the material of the second spacer material layer 122 may be silicon nitride. Compared with the single-layer spacer layer 120a, it has better support performance and better heat insulation performance. In a high temperature environment (for example, an environment greater than the melting point of the conductive layer 101), it can isolate the conductive layer 101 from the external high temperature environment and reduce the deformation of the conductive layer 101 in the high temperature environment. The passivation layer 110 can play a role of sealing and insulation, and can isolate water vapor to prevent the internal structure of the semiconductor device from being contaminated.

[0054] In summary, in the semiconductor device and the manufacturing method thereof provided by the present invention, a passivation layer is first formed, the passivation layer covers the side walls and the top of the conductive layer and the semiconductor substrate, and the passivation layer can protect the conductive layer and the semiconductor substrate from dust or water vapor, etc.; then, a sidewall material layer is formed on the passivation layer, and the sidewall material layer covers the passivation layer. Then, the sidewall material layer is etched to remove the sidewall material layer on the semiconductor substrate and the sidewall material layer on the top of the conductive layer, and the sidewall material layer on the sidewall of the conductive layer is retained to form a sidewall layer. The sidewall layer can support the conductive layer to prevent the conductive layer from collapsing or tilting in a high temperature environment. Since the sidewall layer can support the conductive layer, it is not necessary to make the thickness of the passivation layer on the sidewall of the conductive layer greater than the thickness of the passivation layer on the top of the conductive layer, so there is no need to thin the passivation layer. Compared with the prior art, in the process of etching the passivation layer, the over-etching amount of the passivation layer is less, which can avoid damaging the conductive layer below the passivation layer, thereby avoiding plasma damage, and reducing the probability of arc discharge damaging the substrate, thereby improving the reliability of the device. In addition, in the process of etching the sidewall material layer, the passivation layer can be used as an etching stop layer to avoid over-etching and damaging the conductive layer.

[0055] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing the semiconductor device comprises: Providing a semiconductor substrate, on which a plurality of discrete conductive layers are formed, and the semiconductor substrate is exposed between two adjacent conductive layers; forming a passivation layer, the passivation layer covering the sidewall and the top of the conductive layer and the semiconductor substrate, the thickness of the passivation layer on the sidewall of the conductive layer being the same as the thickness of the passivation layer on the top of the conductive layer, wherein the passivation layer comprises a first passivation layer and a second passivation layer covering the first passivation layer, and the material of the first passivation layer is different from the material of the second passivation layer; forming a spacer material layer on the passivation layer, wherein the spacer material layer covers the passivation layer, and the spacer material layer includes a first spacer material layer and a second spacer material layer; Etching the spacer material layer, removing the spacer material layer at the conductive top to expose the passivation layer at the conductive layer top, and removing the spacer material layer on the semiconductor substrate and retaining the spacer material layer at the conductive layer sidewall to form a spacer layer, wherein the spacer layer includes a first spacer layer and a second spacer layer; and, The passivation layer on top of the conductive layer is etched to form an opening exposing the conductive layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first passivation layer is silicon oxide, and the first passivation layer is formed by plasma enhanced chemical vapor deposition; the material of the second passivation layer is silicon nitride and / or silicon oxynitride, and the second passivation layer is formed by heat treatment.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The thickness of the first passivation layer is 0.8 μm to 1 μm, and the thickness of the second passivation layer is 0.25 μm to 0.35 μm.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first sidewall material layer is silicon oxide, and the first sidewall material layer is formed by a low-pressure chemical vapor deposition process or an atomic layer deposition process; the material of the second sidewall material layer is silicon nitride, and the second sidewall material layer is formed by a low-pressure chemical vapor deposition process.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The thickness of the first spacer material layer is 1 μm to 1.5 μm, and the thickness of the second spacer material layer is 1 μm to 1.5 μm.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: The method for etching the sidewall material layer includes: The first spacer material layer and the second spacer material layer are etched by a plasma etching process to remove the first spacer material layer and the second spacer material layer on the semiconductor substrate, and to remove the first spacer material layer and the second spacer material layer on the top of the conductive layer, and to retain the first spacer material layer on the side wall of the conductive layer to form a first spacer layer, and to retain the second spacer material layer on the side wall of the conductive layer to form a second spacer layer, wherein the spacer layer includes the first spacer layer and the second spacer layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The conductive layer is made of at least one of aluminum, copper, titanium, nickel, aluminum nitride, titanium nitride and nickel nitride.

8. A semiconductor device, characterized in that: The semiconductor device comprises: Semiconductor substrate; A plurality of discrete conductive layers are formed on the semiconductor substrate and cover a portion of the semiconductor substrate; a passivation layer covering the sidewall and top of the conductive layer and the semiconductor substrate, wherein the passivation layer has an opening exposing the conductive layer, the passivation layer comprises a first passivation layer and a second passivation layer covering the first passivation layer, and the material of the first passivation layer is different from the material of the second passivation layer; The sidewall layer covers the passivation layer on the sidewall of the conductive layer, and the sidewall layer includes a first sidewall layer and a second sidewall layer.

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