Display device

Abstract

The embodiment of the present application provides a display device, including a display panel and a touch panel, wherein the touch panel is an organic flexible multi-layer covered surface structure; the display panel includes a display area and a non-display area, wherein the non-display area includes a first pin area, a second pin area and a pin connection area, wherein the pin connection area is provided with a connecting line connecting the pins in the first pin area and the second pin area, and the connecting line is covered by an inorganic insulating layer. In the display device provided in the embodiment of the present application, the connecting line is covered by an inorganic insulating layer, so during the etching and removal process of the organic FMLOC process section, even if there is metal residue in the gap of the connecting line, it will not cause a short circuit of the connecting line. Moreover, the inorganic insulating layer has good water and oxygen barrier properties, which can ensure the reliability of the connecting line in a high temperature and high humidity environment.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of display and touch control equipment, and in particular, to a display device. Background Art

[0002] Flexible Multi Layer On Cell (FMLOC) refers to a touch panel with a capacitive touch device made on the outside of the display panel thin film encapsulation layer. FMLOC can integrate the display structure and the touch structure together, and has the advantages of being thin and light, foldable, etc., and can meet the product requirements of flexible folding, narrow frame, etc. Organic FMLOC is a type of FMLOC, which includes a first organic layer, a first touch layer, a second organic layer, a second touch layer and an organic layer stacked.

[0003] The display panel includes a display area and a non-display area. The non-display area includes a first stitch area, a second stitch area, and a connection area between the first stitch area and the second stitch area. The connection area is provided with connection wiring of stitches in the first stitch area and the second stitch area.

[0004] In the related art, the connection wiring is located in the metal layer covered by the organic layer. Since the organic layer in the organic FMLOC and the organic layer in the display panel have poor adhesion, during the organic FMLOC process, the organic layer in the FMLOC process section and the organic layer in the display panel will have a peeling problem, so the organic layer in the organic FMLOC needs to be removed; however, during the removal process, the connection wiring will be affected, which will damage the reliability. Summary of the invention

[0005] In view of this, an object of the embodiments of the present application is to provide a display device.

[0006] A display device provided in an embodiment of the present application includes a display panel and a touch panel, wherein the touch panel is an organic flexible multi-layer covering surface structure;

[0007] The display panel includes a display area and a non-display area, the non-display area includes a first stitch area, a second stitch area and a stitch connection area, the stitch connection area is provided with a connecting wire connecting the stitches in the first stitch area and the second stitch area, and the connecting wire is covered by an inorganic insulating layer.

[0008] In the display device provided in the embodiment of the present application, the connection wiring is covered by the inorganic insulating layer, so during the etching and removal process of the organic FMLOC process section, even if there is metal remaining in the gap of the connection wiring, it will not cause the short circuit of the connection wiring. In addition, the inorganic insulating layer has good water and oxygen barrier properties, which can ensure the reliability of the connection wiring in a high temperature and high humidity environment.

[0009] In a possible implementation, the touch panel includes a first organic layer, a first touch layer, a second organic layer, a second touch layer, and a third organic layer stacked in a direction away from the display panel;

[0010] In the pin connection area, the first organic layer, the first touch layer, the second organic layer, the second touch layer and the third organic layer are all removed.

[0011] In a possible implementation manner, the first organic layer, the second organic layer, and the third organic layer are all made of negative photosensitive resin.

[0012] In a possible implementation manner, one of the first touch layer and the second touch layer is provided with a plurality of connection bridges, and the other is provided with a plurality of first touch electrodes arranged along a first direction, and a plurality of second touch electrodes arranged at intervals along a second direction perpendicular to the first direction;

[0013] Two first touch control electrodes adjacent to each other along the first direction are connected as one body, and two second touch control electrodes adjacent to each other along the second direction are connected to the connection bridge through via holes provided in the second organic layer.

[0014] In a possible implementation manner, the first touch control layer and the second touch control layer include at least one of indium tin oxide, a metal grid and nano silver wires.

[0015] In a possible implementation, the display device includes a control chip and a flexible circuit board, the first pin area is a binding area bound to the control chip, and the second pin area is a binding area bound to the flexible circuit board.

[0016] In a possible implementation, the inorganic insulating layer is a single-layer or multi-layer structure, including at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0017] In a possible implementation, the display panel includes a base substrate, and a barrier layer, an active layer, a first gate insulating layer, a gate layer, a second gate insulating layer, a first metal layer, an interlayer insulating layer, a first planarizing layer, a passivation layer, a second metal layer, a second planarizing layer, a pixel defining layer, and a thin film encapsulation layer stacked on a side of the base substrate close to the touch panel; the touch panel is disposed on the thin film encapsulation layer;

[0018] The passivation layer is an inorganic insulating layer. In the pin connection area, the connection wire is located in the first metal layer, and the passivation layer extends to the outside of the connection wire to cover the connection wire.

[0019] In a possible implementation manner, in the stitch connection region, the second planar layer is disposed on a side of the passivation layer away from the first metal layer.

[0020] In a possible embodiment, the display device includes a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode; the first electrode is arranged between the pixel defining layer and the second planar layer, and the second electrode is located on a side of the organic light-emitting layer away from the first electrode.

[0021] In a possible implementation, the display panel includes a thin film transistor connected to the first electrode, and the thin film transistor includes a gate, a source, and a drain;

[0022] The gate is located in the gate layer, the drain and the source are located in the first metal layer; the second metal layer includes an electrode connecting portion connecting the drain and the first electrode.

[0023] In a possible implementation, the display panel includes a scan line, a data line, and a power signal line connected to the thin film transistor, the scan line is located in the gate layer, and the data line and the power signal line are located in the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a pixel circuit in a display device provided in an embodiment of the present application;

[0027] Figure 3 A hierarchical schematic diagram of a display panel provided in an embodiment of the present application;

[0028] Figure 4 A hierarchical schematic diagram of a FMOLC provided in an embodiment of the present application;

[0029] Figure 5 A partial schematic diagram of a display panel in a non-display area provided in an embodiment of the present application;

[0030] Figure 6The cross section of the display device in the pin connection area in the related art Figure 1 ;

[0031] Figure 7 The cross section of the display device in the pin connection area in the related art Figure 2 ;

[0032] Figure 8 It is a cross-sectional view of the display device at the pin connection area in the embodiment of the present application.

[0033] Description of reference numerals:

[0034] 1-display panel, 2-display area, 3-non-display area, 4-pixel unit, 5-sub-pixel, 6-first electrode, 7-scan line, 8-data line, 9-thin film transistor, 10-blocking layer, 11-second gate insulating layer, 12-interlayer insulating layer, 13-first flat layer, 14-second flat layer, 15-pixel defining layer, 16-first inorganic encapsulation layer, 17-organic encapsulation layer, 18-second inorganic encapsulation layer, 19-thin film encapsulation layer, 20-second electrode, 21-organic light-emitting layer, 22-second metal layer, 23-passivation layer, 24-first metal layer, 25-first gate insulating layer, 26-gate layer, 27-active layer, 28-base substrate, 29-first organic layer, 30-first touch layer, 31-second organic layer, 32-second touch layer, 33-third organic layer;

[0035] 100: first stitch area, 200: stitch connection area, 300- second stitch area. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] An embodiment of the present application provides a display device, which includes a display panel and a touch panel.

[0038] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the display panel 1 includes a display area 2 (Active Area, referred to as AA area) and a non-display area 3 located outside the display area 2 .

[0039] The display area 2 is the area where the display panel 1 is used to realize display. The display panel 1 is provided with a plurality of pixel units 4 in the display area 2, and the plurality of pixel units 4 are arranged in an array to form a pixel array. Each pixel unit 4 includes a plurality of sub-pixels 5, and the sub-pixel 5 is a light-emitting device capable of emitting a single color. For example, the pixel unit 4 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel is a G sub-pixel capable of emitting green light, the second sub-pixel is an R sub-pixel capable of emitting red light, and the third sub-pixel is a B sub-pixel capable of emitting blue light. When the display panel 1 is displaying, color display is realized by controlling the light emission of various sub-pixels 5 in each pixel unit 4.

[0040] The pixel unit 4 can be OLED (Organic Light-Emitting Diode), QLED (Quantum Dot Light Emitting Diodes), Mini LED (sub-millimeter light-emitting diode) or Micro-LED (micro light-emitting diode). This article describes the pixel unit 4 as an OLED pixel unit as an example. The OLED pixel unit includes OLED sub-pixels that can emit different colors.

[0041] The OLED sub-pixel includes a first electrode, an organic light-emitting layer and a second electrode, wherein the organic light-emitting layer is located between the first electrode and the second electrode, and the light emission of the organic light-emitting layer can be realized by controlling the first electrode and the second electrode. The organic light-emitting layers corresponding to OLED sub-pixels of different colors are different. At least one of a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and / or an electron injection layer (EIL) can also be arranged between the first electrode and the second electrode to improve the light emission efficiency of the organic light-emitting layer.

[0042] In a display panel 1 having an OLED pixel unit, the display panel 1 includes a pixel circuit for controlling an OLED sub-pixel and a first electrode connected to the pixel circuit. Figure 2 A schematic diagram of a pixel circuit in a display device provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the pixel circuit includes a plurality of scan lines (Gate) 7 and a plurality of data lines (Data) 8 arranged in a cross manner, and also includes a plurality of thin film transistors (TFT) 9 corresponding to the OLED sub-pixels. The thin film transistor 9 includes a gate, a source and a drain, the drain of the thin film transistor 9 is connected to the first electrode 6 of the corresponding OLED sub-pixel, the gate of the thin film transistor 9 is connected to the scan line 7, and the source of the thin film transistor 9 is connected to the data line 8.

[0043] The scan lines 7 are arranged corresponding to the pixel rows in the pixel array, and the gate electrodes of the thin film transistors 9 of the pixel units 4 in the same pixel row are connected to the same scan line 7. The data lines 8 are arranged corresponding to the pixel columns in the pixel array, and the sources of the thin film transistors 9 of the pixel units 4 in the same pixel column are connected to the same data line 8.

[0044] Figure 3 A hierarchical schematic diagram of a display panel provided in an embodiment of the present application, such as Figure 3 As shown, the display panel 1 includes a base substrate 28, and a barrier layer (Buffer) 10, an active layer 27, a first gate insulating layer (GI) 25, a gate layer 26, a second gate insulating layer 11, an interlayer insulating layer (inter layer dielectric, abbreviated ILD) 12, a first metal layer 24, a first planarization layer 13 (Planarization, abbreviated PLN), a passivation layer (passivation, abbreviated PVX) 23, a second metal layer 22, a second planarization layer 14, a pixel definition layer 15 (Pixel Definition Layer, abbreviated PDL), OLED sub-pixels and a thin film encapsulation layer (Thin-Film Encapsulation, abbreviated TFE) 19 stacked on one side of the base substrate 28 along the direction close to the touch panel.

[0045] The base substrate 28 may be a rigid plate, such as a glass plate, a quartz plate or an acrylic plate; the base substrate 28 may also be a flexible substrate that can be bent, and the flexible substrate may be made of polymer materials such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyarylate (PAR) or fiberglass reinforced plastic (FRP). In this embodiment, the base substrate 28 is described by taking a flexible plate made of PI as an example.

[0046] The barrier layer 10 is disposed on the side of the base substrate 28 close to the touch panel, and is an inorganic insulating film layer. It can be made of a silicon-containing inorganic material, and can be a multi-layer or single-layer structure. The silicon-containing inorganic material can be at least one of silicon oxide SiO2, silicon nitride SiNx, and silicon oxynitride SiON. In this design, the material properties of the inorganic material are utilized to isolate the flexible substrate and the structure on the flexible substrate, reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the flexible substrate, and provide a flat surface.

[0047] The active layer 27 is arranged on the side of the barrier layer 10 away from the substrate 28, and can be made of amorphous silicon (Amorphous silicon, abbreviated as α-Si, also known as amorphous silicon), polycrystalline silicon (Polycrystalline silicon, abbreviated as Poly-Si), low-temperature polycrystalline silicon (Low-temperature polycrystalline silicon, LTPS), or metal oxide (such as indium gallium zinc oxide, abbreviated as IGZO) and other materials.

[0048] The first gate insulating layer 25 is disposed on the side of the active layer 27 away from the base substrate 28. The side of the first gate insulating layer 25 away from the base substrate 28 is provided with a gate layer 26, which includes a gate and a scanning line 7. The active layer 27 includes a channel region corresponding to the gate.

[0049] The second gate insulating layer 11 is disposed on the side of the gate layer 26 away from the base substrate 28, and the interlayer insulating layer 12 is disposed on the side of the second gate insulating layer away from the base substrate 28. The first metal layer 24 is disposed on the side of the interlayer insulating layer 12 away from the base substrate 28. The first planarizing layer 13 and the passivation layer 23 are disposed on the side of the first metal layer 24 away from the base substrate 28, and the second metal layer 22 is disposed on the side of the passivation layer 23 away from the base substrate 28.

[0050] The first metal layer 24 and the second metal layer 22 are metal layers at different heights. The source and drain in the thin film transistor 9, and the data line 8, the power signal line VDD and other signal lines in the display panel 1 can be selectively set in the first metal layer 24 or the second metal layer 22. For some signal lines, they can also be set in both the first metal layer 24 and the second metal layer 22. By routing in different metal layers, the influence of coupling capacitance on the signal can be reduced, which is conducive to adapting to the adaptation scene of high refresh rate.

[0051] In this embodiment, the first metal layer 24 is used to make the source and drain of the thin film transistor 9, and the second metal layer 22 is used to make signal lines such as the data line 8 and the power signal line VDD, and is used to connect with the first electrode 6 and the drain.

[0052] The second metal layer 22 is provided with a second flat layer 14 on a side away from the base substrate 28 . The second flat layer 14 has a flat surface on a side away from the base substrate 28 , and the flat surface facilitates the manufacturing and molding of the structure above it.

[0053] The pixel defining layer 15 is arranged on the side of the second flat layer 14 away from the flexible substrate, and has a pixel opening. The first electrode 6 in the OLED sub-pixel is arranged between the pixel defining layer 15 and the second flat layer 14, and is exposed through the pixel opening. The first electrode 6 is connected to the electrode connecting portion in the second metal layer 22 through a via hole, and the electrode connecting portion is used to connect the first electrode 6 and the drain. The organic light-emitting layer 21 is arranged in the pixel opening. The second electrode 20 is located on the side of the organic light-emitting layer 21 away from the first electrode 6.

[0054] In the above embodiment, the first gate insulating layer 25, the second gate insulating layer 11, the interlayer insulating layer 12 and the passivation layer 23 are all inorganic insulating film layers, which can be made of silicon-containing inorganic materials and can be a multi-layer or single-layer structure. The silicon-containing inorganic material can be at least one of silicon oxide SiO2, silicon nitride SiNx and silicon oxynitride SiON.

[0055] The thin film encapsulation layer 19 of the display panel 1 covers the side of the OLED pixel unit away from the base substrate 28, so as to achieve a sealed package for the OLED pixel unit. The thin film encapsulation layer 19 includes an organic encapsulation layer and an inorganic encapsulation layer stacked in layers, and the inorganic encapsulation layer is at least sealed and wrapped around the side of the organic encapsulation layer 17 away from the flexible substrate, that is, the outer side of the organic encapsulation layer.

[0056] The material of the inorganic encapsulation layer is made of silicon-containing inorganic material, and the silicon-containing inorganic material can be at least one of silicon oxide SiO2, silicon nitride SiNx and silicon oxynitride SiON. The material of the organic encapsulation layer can be polymers such as acrylic polymers and silicon-based polymers. The inorganic encapsulation layer has good water and oxygen barrier properties to prevent external water and oxygen from affecting the organic materials in the OLED pixel unit. The organic encapsulation layer 17 can absorb and disperse the stress between layers well, avoiding cracks in the dense inorganic encapsulation layer and reducing the barrier to water and oxygen.

[0057] Please refer to Figure 3 In this embodiment, the thin film encapsulation layer 19 includes a first inorganic encapsulation layer 16, an organic encapsulation layer 17 and a second inorganic encapsulation layer 18 stacked in a direction away from the base substrate 28. The first inorganic encapsulation layer 16 and the second inorganic encapsulation layer 18 are arranged on both sides of the organic encapsulation layer 17, and the organic encapsulation layer 17 is sealed and coated to give full play to the water-blocking performance of the inorganic encapsulation layer.

[0058] In order to meet the stress requirement of large-angle bending, one or more organic layers and inorganic layers may be added to the side of the thin film encapsulation layer 19 away from the base substrate 28 .

[0059] The touch panel in the display device is arranged on the outside of the thin film encapsulation layer 19, forming a flexible multi-layer on-cell (FMLOC) structure. FMLOC integrates the touch panel and the display panel 1 together, and has the advantages of being light, thin, and foldable, and can meet product requirements such as flexible folding and narrow bezels.

[0060] Figure 4 A schematic diagram of an FMLOC structure provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the FMLOC includes a first organic layer 29, a first touch layer 30, a second organic layer 31, a second touch layer 32 and a third organic layer 33 stacked in a direction away from the thin film encapsulation layer 19. In this embodiment, the first organic layer 29, the second organic layer 31 and the third organic layer 33 can all be made of negative photosensitive adhesive (OC adhesive).

[0061] The first touch layer 30, the second organic layer 31 and the second touch layer 32 form a mutual capacitance touch device. In a specific example, the first touch layer 30 includes a plurality of connection bridges, and the second touch layer 32 may include a plurality of first touch electrodes arranged along a first direction, and a plurality of second touch electrodes arranged at intervals along a second direction perpendicular to the first direction. Two adjacent first touch electrodes are connected as a whole, and two adjacent second touch electrodes are connected to the connection bridge through a via hole provided on the touch insulating layer, that is, the connection bridge connects two adjacent second touch electrodes.

[0062] In a possible implementation manner, the connection bridge may be provided in the second touch layer 32 , and correspondingly, the first touch electrode and the second touch electrode are provided in the first touch layer 30 .

[0063] The first touch layer 30 and the second touch layer 32 include at least one of indium tin oxide (ITO), a metal mesh, and nano silver wires.

[0064] The FMLOC is disposed outside the thin film encapsulation layer 19 , and the touch area having the mutual capacitive touch device may overlap with the display area 2 , or be slightly larger than the display area 2 .

[0065] Figure 5 A partial schematic diagram of a display panel in a non-display area provided in an embodiment of the present application, such as Figure 5 As shown, the non-display area includes a first stitch area 100, a second stitch area 300 and a stitch connection area 200. The first stitch area 100 and the second stitch area 300 are both provided with a plurality of stitches arranged side by side, and the stitch connection area 200 is provided with connection wiring of the stitches in the first stitch area 100 and the second stitch area 300.

[0066] In this embodiment, the display device adopts COP packaging, including a control chip and a flexible printed circuit (FPC), the first pin area 100 is a binding area bound to the control chip, and the second pin area 300 is a binding area bound to the flexible printed circuit.

[0067] In the pin connection area 200, the passivation layer 23 in the display panel 1 is retained, the first flat layer 13 is removed, the second flat layer 14 is retained, the pixel defining layer 15 is removed, and the second flat layer 14 is located outside away from the base substrate 28. The second flat layer 14 will be overetched once during the Descum dry etching process after PDL development.

[0068] Since the organic layer in the organic FMLOC has poor adhesion to the organic layer in the display panel 1, during the organic FMLOC process, the organic layer in the organic FMLOC process section may peel off from the organic layer in the display panel 1. Therefore, in order to avoid such peeling, the first organic layer 29, the second organic layer 31 and the second organic layer 32 are removed. In addition, since the pin connection area 200 is located outside the touch area, the first touch layer 30 and the second touch layer 32 in the touch panel are also removed.

[0069] That is to say, in the pin connection area 200, the process flow of the organic FMLOC is: the first organic layer 29 is removed by exposure and development, the first touch layer 30 is removed by dry etching, the second organic layer 31 is removed by exposure and development, the second touch layer 32 is removed by dry etching, and the third organic layer 33 is removed by exposure and development.

[0070] Figure 6 The cross section of the display device in the pin connection area in the related art Figure 1 ,like Figure 6 As shown, in the related art, the connection wires of the pin connection area 200 are made in the second metal layer 22, and the second flat layer 14 covers the outside of the connection wires. However, during the organic FMLOC process, the second flat layer 14 is also overetched, and multiple overetchings result in that only part of the second flat layer 14 remains in the gaps of the connection wires, and the second touch layer 32 is likely to remain in the gaps, resulting in short circuits of the connection wires. In addition, the surface of the connection wires is not protected, and the reliability is poor.

[0071] Figure 7 The cross section of the display device in the pin connection area in the related art Figure 1 ,like Figure 7 As shown, even if the thickness of the second planar layer 14 is increased to ensure that the second planar layer 14 can still maintain an ideal film thickness outside the connecting line after multiple overetchings, in this case, there is only the second planar layer 14 outside the connecting line, and the reliability is easily failed under high temperature and high humidity.

[0072] In view of this, in the display device provided in the embodiment of the present application, the connection wiring located in the pin connection area 200 is manufactured in the first metal layer 24 .

[0073] Figure 8 is a cross-sectional view of the display device in the pin connection area in the embodiment of the present application, such as Figure 8 As shown, in the pin connection area, the outside of the first metal layer 24 where the connection line is located is covered with a passivation layer 23 and a second flat layer 14. Therefore, in the organic FMLOC process section, even if the second flat layer 14 is overetched multiple times, due to the existence of the passivation layer 23, even if there is metal residue in the gap of the connection line, it will not cause the connection line to be shorted. Moreover, the passivation layer 23 is made of at least one of silicon oxide SiO2, silicon nitride SiNx and silicon oxynitride SiON, and has good water and oxygen barrier properties, which can ensure the reliability of the connection line in a high temperature and high humidity environment.

[0074] The above embodiment is described by taking the example of making the connection wiring in the first metal layer 24, but the application is not limited thereto. The outer side of the connection wiring is covered by an inorganic insulating layer to improve the above defects existing in the related art. The inorganic insulating layer covering the connection wiring can be a passivation layer, or it can be a part of other inorganic insulating layers in the display area extending to the pin wiring area; it can also be a separately provided inorganic insulating layer.

[0075] For example, the connecting wiring is made in the gate layer 26, and the outer side is covered with at least one inorganic insulating layer of the first gate insulating layer 25, the second gate insulating layer 11, the interlayer insulating layer 12, the passivation layer 23, the first inorganic encapsulation layer 16, and the second inorganic encapsulation layer 18.

[0076] In addition, in the above embodiment, the first pin area 100 is a binding area bound to the control chip, and the second pin area 300 is a binding area bound to the flexible circuit board. However, the embodiment of the present application is not limited thereto, for example, the first pin area can be a binding area, and the second pin area can be a test area with test pins.

[0077] In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0078] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0079] In addition, the technical features involved in the different embodiments of the present application described above can be combined with each other as long as they do not conflict with each other.

[0080] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. A display device, characterized in that: The display device comprises a display panel and a touch panel, wherein the touch panel is an organic flexible multi-layer covering surface structure; The display panel includes a display area and a non-display area, the non-display area includes a first stitch area, a second stitch area and a stitch connection area, the stitch connection area is provided with a connection line connecting stitches in the first stitch area and the second stitch area, and the connection line is covered by an inorganic insulating layer; The touch panel includes a first organic layer, a first touch layer, a second organic layer, a second touch layer and a third organic layer stacked in a direction away from the display panel; The pin connection area, the first organic layer, the first touch layer, the second organic layer, the second touch layer and the third organic layer are all removed.

2. The display device according to claim 1, characterized in that The first organic layer, the second organic layer and the third organic layer are all made of negative photosensitive resin.

3. The display device according to claim 1, characterized in that One of the first touch layer and the second touch layer is provided with a plurality of connection bridges, and the other is provided with a plurality of first touch electrodes arranged along a first direction, and a plurality of second touch electrodes arranged at intervals along a second direction perpendicular to the first direction; Two first touch control electrodes adjacent to each other along the first direction are connected as one body, and two second touch control electrodes adjacent to each other along the second direction are connected to the connection bridge through via holes provided in the second organic layer.

4. The display device according to claim 3, characterized in that: The first touch layer and the second touch layer include at least one of indium tin oxide, a metal grid and nano silver wires.

5. The display device according to claim 1, characterized in that The display device includes a control chip and a flexible circuit board. The first pin area is a binding area bound to the control chip, and the second pin area is a binding area bound to the flexible circuit board.

6. The display device according to claim 1, characterized in that: The inorganic insulating layer is a single-layer or multi-layer structure, and includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

7. The display device according to any one of claims 1 to 6, characterized in that: The display panel comprises a base substrate, and a barrier layer, an active layer, a first gate insulating layer, a gate layer, a second gate insulating layer, a first metal layer, an interlayer insulating layer, a first planarizing layer, a passivation layer, a second metal layer, a second planarizing layer, a pixel defining layer and a thin film encapsulation layer stacked on a side of the base substrate close to the touch panel; the touch panel is arranged on the thin film encapsulation layer; The passivation layer is an inorganic insulating layer. In the pin connection area, the connection wire is located in the first metal layer, and the passivation layer extends to the outside of the connection wire to cover the connection wire.

8. The display device according to claim 7, characterized in that: In the stitch connection area, the second planar layer is disposed on a side of the passivation layer away from the first metal layer.

9. The display device according to claim 7, characterized in that: The display device includes a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode; the first electrode is arranged between the pixel defining layer and the second flat layer, and the second electrode is located on a side of the organic light-emitting layer away from the first electrode.

10. The display device according to claim 9, characterized in that: The display panel includes a thin film transistor connected to the first electrode, and the thin film transistor includes a gate, a source and a drain; The gate is located in the gate layer, the drain and the source are located in the first metal layer; the second metal layer includes an electrode connecting portion connecting the drain and the first electrode.

11. The display device according to claim 10, characterized in that: The display panel includes a scan line, a data line and a power signal line connected to the thin film transistor, the scan line is located in the gate layer, and the data line and the power signal line are located in the second metal layer.

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