Memory exception detection method and device, storage medium, and electronic device

Abstract

Embodiments of the present application provide a memory exception detection method and device, a storage medium and an electronic device, the method comprising: in the case of starting a central processing unit (CPU), acquiring data transmitted on a low pin count (LPC) bus in the CPU; in the case of determining that abnormal data exists, recording a number of times that the abnormal data exists in a preset period in a register in a complex programmable logic device (CPLD), wherein the register is used to store the data transmitted on the LPC bus; and detecting whether memory in the CPU is abnormal based on the number of times that the abnormal data exists. Through the present application, the problem of detecting memory failure in the related art is solved, and the effect of accurately detecting whether memory is abnormal is achieved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and more specifically, to a method and apparatus for detecting memory anomalies, a storage medium, and an electronic device. Background Technology

[0002] Existing technical solutions use a Central Processing Unit (CPU) to monitor its peripheral configuration circuits. The CPU only generates the detection result type encoding signal during normal startup. Without memory inserted, the Basic Input / Output System (BIOS) cannot boot, resulting in an abnormal CPU startup and making memory fault detection impossible. Summary of the Invention

[0003] This invention provides a method and apparatus for detecting memory anomalies, a storage medium, and an electronic device, to at least solve the problem of detecting memory faults in related technologies.

[0004] According to an embodiment of the present invention, an anomaly detection method is provided, comprising: when a central processing unit (CPU) is started, acquiring data transmitted on the LPC bus of the CPU; when it is determined that abnormal data has occurred, recording the number of times the abnormal data exists in a register of a complex programmable logic device (CPLD) within a preset period, wherein the register is used to store data transmitted on the LPC bus; and detecting whether the memory in the CPU is abnormal based on the number of times the abnormal data exists.

[0005] According to another embodiment of the present invention, a memory anomaly detection device is provided, comprising: a first acquisition module, configured to acquire data transmitted on the LPC bus of the CPU when the CPU is started; a first recording module, configured to record the number of times the abnormal data exists in a register of a complex programmable logic device (CPLD) within a preset period when it is determined that abnormal data exists, wherein the register is used to store data transmitted on the LPC bus; and a first detection module, configured to detect whether the memory in the CPU is abnormal based on the number of times the abnormal data exists.

[0006] In an exemplary embodiment, the first acquisition module includes a first acquisition unit, configured to acquire the CPU startup data transmitted at a preset address in the LPC bus when the central processing unit (CPU) is started.

[0007] In an exemplary embodiment, the first recording module includes: a first determining unit, configured to determine that abnormal data has occurred if the data transmitted at a preset address on the LPC bus does not include the CPU's startup data; a first starting unit, configured to start monitoring of a register, wherein the register is used to store the data transmitted at the preset address on the LPC bus; and a first statistics unit, configured to count the number of times abnormal data occurs in the register within the preset period.

[0008] In an exemplary embodiment, the first recording module includes: a second determining unit, configured to determine that abnormal data has occurred when the data transmitted at a preset address in the LPC bus is preset data; a second starting unit, configured to start monitoring of the register, wherein the register is used to store the data transmitted at the preset address in the LPC bus; and a second statistics unit, configured to count the number of times the abnormal data occurs in the register within the preset period.

[0009] In an exemplary embodiment, the first detection module includes a third determining unit, configured to determine that the memory in the CPU is abnormal when the number of times abnormal data exists exceeds a preset threshold, and to issue an alarm message.

[0010] According to yet another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0011] According to yet another embodiment of the present invention, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0012] This invention acquires data transmitted on the LPC bus of the CPU when the CPU is powered on; upon determining that abnormal data has occurred, it records the number of times abnormal data exists in the registers of the Complex Programmable Logic Device (CPLD) within a preset period, where the registers store data transmitted on the LPC bus; and it detects whether memory in the CPU is malfunctioning based on the number of abnormal data occurrences. This achieves memory anomaly detection. Therefore, it solves the problem of memory fault detection in related technologies, achieving the effect of accurately detecting whether memory faults have occurred. Attached Figure Description

[0013] Figure 1 This is a hardware structure block diagram of a mobile terminal for a memory anomaly detection method according to an embodiment of the present invention.

[0014] Figure 2 This is a flowchart of a memory anomaly detection method according to an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of the system structure according to an embodiment of the present invention;

[0016] Figure 4 This is an overall flowchart according to an embodiment of the present invention;

[0017] Figure 5 This is a structural block diagram of a memory anomaly detection device according to an embodiment of the present invention. Detailed Implementation

[0018] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a memory anomaly detection method according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0021] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the memory anomaly detection method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0022] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0023] This embodiment provides a method for detecting memory anomalies. Figure 2 This is a flowchart of a memory anomaly detection method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0024] Step S202: When the central processing unit (CPU) is started, acquire the data transmitted on the LPC bus of the CPU bus controller.

[0025] Step S204: If abnormal data is determined to have occurred, record the number of times abnormal data exists in the registers of the complex programmable logic device (CPLD) within a preset period. The registers are used to store data transmitted on the LPC bus.

[0026] Step S206: Detect whether there is an anomaly in the memory of the CPU based on the number of times abnormal data exists.

[0027] The entity performing the above steps can be a CPLD, but is not limited to this.

[0028] In this embodiment, the data flow is monitored by an external circuit, eliminating the need for a full CPU startup. This eliminates the need for BIOS program checks, thus enabling memory detection alarms.

[0029] Through the above steps, data transmitted on the LPC bus of the CPU is acquired when the CPU is powered on. If abnormal data is detected, the number of times abnormal data appears in the registers of the Complex Programmable Logic Device (CPLD) within a preset period is recorded. These registers store data transmitted on the LPC bus. The number of abnormal data occurrences is used to detect whether memory in the CPU is malfunctioning. This achieves memory anomaly detection. Therefore, it solves the problem of memory fault detection in related technologies, achieving accurate detection of memory malfunctions.

[0030] In one exemplary embodiment, when the central processing unit (CPU) is started, acquiring data transmitted on the LPC bus of the CPU bus controller includes:

[0031] S11: When the central processing unit (CPU) is started, the CPU startup data is obtained from a preset address on the LPC bus.

[0032] In this embodiment, for example, during the CPU startup process, when there is normal memory, the 80Port data of the CPU startup process will be output at address 80 of the LPC bus.

[0033] In one exemplary embodiment, when abnormal data is determined to have occurred, the number of times abnormal data exists in the registers of a complex programmable logic device (CPLD) within a preset period is recorded, including:

[0034] S21, if the data transmitted at the preset address in the LPC bus does not include the CPU's startup data, it is determined that abnormal data has occurred;

[0035] S22, Start monitoring of the registers, where the registers are used to store data transferred at preset addresses in the LPC bus;

[0036] S23, within a preset period, count the number of times abnormal data appears in the register.

[0037] In this embodiment, for example, the CPLD monitors the data on address 80 of the LPC bus in real time (read-only), collects each data, stores it in a register, and determines whether it is the preset stop data and whether to trigger the corresponding action.

[0038] In one exemplary embodiment, when abnormal data is determined to have occurred, the number of times abnormal data exists in the registers of a complex programmable logic device (CPLD) within a preset period is recorded, including:

[0039] S31, if the data transmitted at the preset address in the LPC bus is the preset data, it is determined that abnormal data has occurred;

[0040] S32, start monitoring of the registers, where the registers are used to store data transferred at preset addresses in the LPC bus;

[0041] S33 counts the number of times abnormal data appears in the register within a preset period.

[0042] For example, if the collected data is the preset stop data, a judgment mechanism is triggered, that is, the register is read every certain period of time to check whether its value is still the preset stop data. If so, the counter is incremented by one.

[0043] In one exemplary embodiment, detecting memory anomalies in the CPU based on the amount of anomalous data includes:

[0044] S41, if the number of times abnormal data exists exceeds a preset threshold, determine that there is an abnormality in the memory of the CPU and issue an alarm message.

[0045] For example, an alarm message can be issued via a buzzer device.

[0046] The present invention will now be described in conjunction with specific embodiments:

[0047] This embodiment uses a CPLD or logic control unit to directly parse the LPC bus protocol, enabling it to detect no memory without requiring a full CPU startup. Simultaneously, because the CPU trains the memory, it can identify whether the memory is functioning correctly. It consists of a CPU, N memory modules, a CPLD or logic control unit, and a buzzer. Figure 3 As shown.

[0048] In this embodiment, as Figure 4 As shown, the process in this embodiment includes the following steps:

[0049] During the CPU startup process of S401, when normal memory is available, address 80 of the LPC bus will output 80Port data indicating the CPU startup process. When there is no memory or abnormal memory, no special 80Port data will be output, but it will stop at a fixed 80Port data.

[0050] The S402 CPLD monitors the data at address 80 of the LPC bus in real time (read-only), collects each data point, and stores it in a register.

[0051] S403, determine whether it is the preset stop data and whether the corresponding action is triggered. If yes, proceed to S405; otherwise, proceed to S404.

[0052] S404, continue collecting data.

[0053] S405 If the collected data is the preset stop data, a judgment mechanism is triggered, that is, the register is read once every certain period of time to determine whether its value is still the preset stop data.

[0054] S406, if so, increment the counter by one.

[0055] S407 If the counter count exceeds the preset value, the buzzer will sound an alarm; if the collected data is not the preset stop data, the judgment action will not be triggered.

[0056] In summary, this embodiment uses external circuitry to monitor the data flow, achieving memory-free detection alarms. It eliminates the need for a full CPU boot, eliminates the need for BIOS program checks, resulting in faster response and compatibility with more platforms.

[0057] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0058] This embodiment also provides a memory anomaly detection device, which is used to implement the above embodiments and preferred embodiments, and will not be repeated as already described. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0059] Figure 5 This is a structural block diagram of a memory anomaly detection device according to an embodiment of the present invention, as shown below. Figure 5 As shown, the device includes:

[0060] The first acquisition module 52 is used to acquire data transmitted on the LPC bus of the CPU when the central processing unit (CPU) is started.

[0061] The first recording module 54 is used to record the number of times abnormal data exists in the registers of the complex programmable logic device (CPLD) within a preset period when it is determined that abnormal data has occurred. The registers are used to store data transmitted on the LPC bus.

[0062] The first detection module 56 is used to detect whether there is an anomaly in the memory of the CPU based on the number of times abnormal data exists.

[0063] In one exemplary embodiment, the first acquisition module described above includes:

[0064] The first acquisition unit is used to acquire the CPU startup data transmitted at a preset address in the LPC bus when the central processing unit (CPU) is started.

[0065] In one exemplary embodiment, the first recording module described above includes:

[0066] The first determining unit is used to determine that abnormal data has occurred if the data transmitted at a preset address in the LPC bus does not include the CPU's startup data.

[0067] The first startup unit is used to start monitoring of the registers, wherein the registers are used to store data transmitted at a preset address in the LPC bus.

[0068] The first statistical unit is used to count the number of times abnormal data appears in the above-mentioned register within the above-mentioned preset period.

[0069] In one exemplary embodiment, the first recording module described above includes:

[0070] The second determining unit is used to determine that the above-mentioned abnormal data has occurred when the data transmitted at the preset address in the above-mentioned LPC bus is preset data.

[0071] The second startup unit is used to start monitoring of the above-mentioned registers, wherein the above-mentioned registers are used to store data transmitted at a preset address in the above-mentioned LPC bus;

[0072] The second statistical unit is used to count the number of times the above-mentioned abnormal data appears in the above-mentioned register within the above-mentioned preset period.

[0073] In one exemplary embodiment, the first detection module described above includes:

[0074] The third determining unit is used to determine that there is an anomaly in the memory of the CPU when the number of times abnormal data exists exceeds a preset threshold, and to issue an alarm message.

[0075] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0076] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0077] In this embodiment, the computer-readable storage medium described above may be configured to store a computer program for performing the above steps.

[0078] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0079] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0080] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0081] In one exemplary embodiment, the processor described above may be configured to perform the above steps via a computer program.

[0082] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0083] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for detecting memory anomalies, characterized in that, include: Before the central processing unit (CPU) is fully started, data transmitted on the LPC bus of the CPU is acquired. Acquiring data transmitted on the LPC bus of the CPU before the CPU is fully started includes: acquiring the CPU's startup data transmitted at a preset address on the LPC bus before the CPU is fully started. When abnormal data is detected, the number of times the abnormal data exists in the register of the complex programmable logic device (CPLD) within a preset period is recorded. The register is used to store data transmitted on the LPC bus, and the abnormal data includes preset stop data in the CPU's startup data. The CPU's memory is checked for abnormalities based on the number of times the abnormal data exists.

2. The method according to claim 1, characterized in that, When abnormal data is identified, the number of times the abnormal data exists in the registers of the complex programmable logic device (CPLD) within a preset period is recorded, including: If the data transmitted at the preset address in the LPC bus does not include the CPU's startup data, then the abnormal data is determined to have occurred. Start monitoring of the register, wherein the register is used to store data transmitted at a preset address in the LPC bus; Within the preset period, the number of times the abnormal data appears in the register is counted.

3. The method according to claim 1, characterized in that, When abnormal data is identified, the number of times the abnormal data exists in the registers of the complex programmable logic device (CPLD) within a preset period is recorded, including: If the data transmitted at the preset address in the LPC bus is preset data, it is determined that the abnormal data has occurred; Start monitoring of the register, wherein the register is used to store data transmitted at a preset address in the LPC bus; Within the preset period, the number of times the abnormal data appears in the register is counted.

4. The method according to any one of claims 1-3, characterized in that, Detecting memory anomalies in the CPU based on the quantity of the abnormal data includes: If the number of times the abnormal data exists exceeds a preset threshold, it is determined that the memory in the CPU is abnormal, and an alarm message is issued.

5. A memory anomaly detection device, characterized in that, include: The first acquisition module is used to acquire data transmitted on the LPC bus of the CPU before the CPU is fully started. The first recording module is used to record the number of times the abnormal data exists in the register of the complex programmable logic device (CPLD) within a preset period when it is determined that abnormal data has occurred. The register is used to store data transmitted on the LPC bus, and the abnormal data includes preset stop data in the CPU's startup data. The first detection module is used to detect whether there is an anomaly in the memory of the CPU based on the number of times the abnormal data exists. The device is also used to acquire the CPU startup data transmitted at a preset address in the LPC bus before the CPU is fully started.

6. The apparatus according to claim 5, characterized in that, The device further includes: N storage devices are used to store the data transmitted on the LPC bus, where N is a natural number greater than or equal to 1.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the method described in any one of claims 1 to 4.

8. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method described in any one of claims 1 to 4.

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