Memory cell sensing

Abstract

This application relates to memory cell sensing. A memory can include a controller configured to cause the memory to apply a boosted voltage level to each of a plurality of capacitances that are each connected to a respective node of a sensing circuit, selectively discharge each of the nodes through a respective memory cell selected for a sensing operation, measure a current demand of the plurality of capacitances when each of the nodes is connected to a respective memory cell, determine a de-boosted voltage level in response to the measured current demand, apply the de-boosted voltage level to each of the plurality of capacitances, and determine a respective data state of each of the plurality of memory cells when the de-boosted voltage level is applied to each of the plurality of capacitances.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to integrated circuits, and in particular, in one or more embodiments, the present disclosure relates to apparatuses and methods for memory cell programming. BACKGROUND

[0002] Memory, e.g., a memory device, is typically provided as internal devices, semiconductors, integrated circuits devices in computers or other electronic systems. There are many different types of memory including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has evolved as a popular nonvolatile memory source for various electronic applications. Flash memory typically uses a single transistor memory cell that allows high memory density, high reliability, and low power consumption. The change in threshold voltage (Vt) of the memory cell, by programming a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determines the data state (e.g., data value) of each memory cell. Common uses of flash memory and other nonvolatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical devices, vehicles, wireless devices, mobile telephones, and removable memory modules, and the use of nonvolatile memory is continually expanding.

[0004] NAND flash memory is a commonly used type of flash memory device, so named for the logical form in which the basic memory cell configuration is arranged. Typically, an array of memory cells for NAND flash memory is arranged such that the control gates of each memory cell in a row in the array are connected together to form an access line, e.g., a word line. Columns in the array include strings of memory cells (often referred to as NAND strings) connected together in series between a pair of select gates, e.g., between a source select transistor and a drain select transistor. Each source select transistor can be connected to a source, and each drain select transistor can be connected to a data line, e.g., a column bit line. Variations using more than one select gate between the string of memory cells and the source and / or between the string of memory cells and the data line are known.

[0005] When programming memory, memory cells can be programmed as what is commonly known as a single-level cell (SLC). An SLC can use a single memory cell to represent a single data digit (e.g., a bit). For example, in an SLC, a Vt of 2.5V or higher can indicate a programmable memory cell (e.g., representing logic 0), while a Vt of -0.5V or lower can indicate an eraseable memory cell (e.g., representing logic 1). Higher levels of storage capacity can be achieved by including multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and combinations thereof, where memory cells have multiple levels, allowing more data digits to be stored in each memory cell. For example, an MLC can be configured to store two data digits per memory cell, represented by four Vt ranges; a TLC can be configured to store three data digits per memory cell, represented by eight Vt ranges; a QLC can be configured to store four data digits per memory cell, represented by sixteen Vt ranges, and so on.

[0006] Sensing (e.g., reading or verifying) the data state of a memory cell typically involves detecting whether the memory cell is active in response to a specific voltage applied to a control gate, for example, by detecting whether the data line connected to the memory cell experiences a voltage level change caused by the current flowing through the memory cell. As memory operation progresses to represent additional data states per memory cell, the margin between adjacent Vt ranges can become smaller. If the Vt of the sensed memory cell shifts over time, this can lead to inaccurate determination of the data state of the sensed memory cell.

[0007] The threshold voltage of a memory cell can be shifted due to phenomena such as rapid charge loss (QCL). QCL is the decapsulation of electrons from the gate dielectric interface into the channel region of the memory cell and can cause a Vt shift shortly after the programming pulse. When the memory cell passes the verification operation, the programmed threshold voltage may appear higher due to the trapped charge in the gate dielectric. When the memory cell is read after the programming operation is complete, the Vt of the memory cell may be lower than the Vt obtained during the programming verification operation due to charge leakage from the gate dielectric into the channel region.

[0008] The threshold voltage of a memory cell can be further offset by accumulated charge loss over the years of its programmed data, which is, for example, the time between programming and reading the data and is referred to herein as the data lifetime. This charge loss becomes more pronounced as the data storage structure becomes smaller.

[0009] Furthermore, the threshold voltage of a memory cell can be shifted due to read interference. In read interference, the threshold voltage of a memory cell can shift in response to the voltage applied to the memory cell to facilitate access to a selected target memory cell for reading, for example, by increasing the threshold voltage of the memory cell. Summary of the Invention

[0010] One aspect of this disclosure provides a memory, comprising: a memory cell array; a plurality of sensing circuits, each of the plurality of sensing circuits including a corresponding capacitor of a plurality of capacitors, wherein each of the plurality of capacitors is connected to a corresponding node of a plurality of nodes, and wherein each of the plurality of nodes is selectively connected to a memory cell in the memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the following operations: apply a boost voltage level to each of the plurality of capacitors; and selectively access a memory cell in the plurality of memory cells of the memory cell array for sensing operations. Discharge each of the plurality of nodes, wherein each of the plurality of memory cells is connected to a corresponding node of the plurality of nodes; measure the current demand of the plurality of capacitors when each of the plurality of nodes is connected to a corresponding memory cell of the plurality of memory cells; isolate each of the plurality of nodes from the corresponding memory cell of the plurality of memory cells; determine a deboost voltage level in response to the measured current demand; apply the deboost voltage level to each of the plurality of capacitors; and determine the corresponding data state of each of the plurality of memory cells when the deboost voltage level is applied to each of the plurality of capacitors.

[0011] Another aspect of this disclosure provides a memory, comprising: a memory cell array; a plurality of sensing circuits, each of the plurality of sensing circuits including a corresponding capacitor of a plurality of capacitors, wherein each of the plurality of capacitors is connected to a corresponding node of a plurality of nodes, and wherein each of the plurality of nodes is selectively connected to a memory cell in the memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the following operations: apply a boost voltage level to each capacitor in a first subset of the plurality of capacitors and each capacitor in a second subset of the plurality of capacitors that is different from the first subset of the plurality of capacitors; selectively discharge each of the plurality of nodes by selecting a corresponding memory cell in the plurality of memory cells of the memory cell array for sensing operations, wherein each memory cell in the plurality of memory cells is connected to a memory cell in the memory cell array. The system comprises: a corresponding node among a plurality of nodes; when each of the plurality of nodes is connected to a corresponding memory cell among the plurality of memory cells, measuring a first current demand of a first subset of capacitors and measuring a second current demand of a second subset of capacitors; isolating each of the plurality of nodes from a corresponding memory cell among the plurality of memory cells; determining a first deboost voltage level in response to the measured first current demand and a second deboost voltage level in response to the measured second current demand; applying the first deboost voltage level to each capacitor in the first subset of capacitors and applying the second deboost voltage level to each capacitor in the second subset of capacitors; and determining a corresponding data state of each memory cell among the plurality of memory cells when the first deboost voltage level is applied to each capacitor in the first subset of capacitors and when the second deboost voltage level is applied to each capacitor in the second subset of capacitors.

[0012] Another aspect of this disclosure provides a memory, comprising: a memory cell array; a plurality of sensing circuits, each of the plurality of sensing circuits including a corresponding capacitor of a plurality of capacitors, wherein each capacitor of the plurality of capacitors is connected to a corresponding node of a plurality of nodes, and wherein each node of the plurality of nodes is selectively connected to a memory cell of the memory cell array; and a controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the following operations: apply a first boost voltage level to each capacitor in a first subset of the plurality of capacitors, and apply a second boost voltage level different from the first boost voltage level to each capacitor in a second subset of the plurality of capacitors different from the first subset of capacitors; by selecting the memory cell array for sensing operations Each memory cell in a plurality of memory cells selectively discharges each of the plurality of nodes, wherein each memory cell in the plurality of memory cells is connected to the corresponding node in the plurality of nodes; when each of the plurality of nodes is connected to the corresponding memory cell in the plurality of memory cells, a first current demand of a first subset of capacitors and a second current demand of a second subset of capacitors are measured; each of the plurality of nodes is isolated from the corresponding memory cell in the plurality of memory cells; a deboost voltage level is determined in response to the measured first current demand and the measured second current demand; the deboost voltage level is applied to each of the plurality of capacitors; and when the deboost voltage level is applied to each of the plurality of capacitors, a corresponding data state of each memory cell in the plurality of memory cells is determined. Attached Figure Description

[0013] Figure 1 This is a simplified block diagram of a memory according to an embodiment, which communicates with a processor as part of an electronic system.

[0014] Figures 2A-2C It can be used for reference. Figure 1 A schematic diagram of a portion of the memory cell array in the memory of the aforementioned type.

[0015] Figure 3 This is a conceptual diagram of the threshold voltage distribution of multiple memory cells.

[0016] Figures 4A-4C This is a conceptual diagram of the distribution of the adjacent threshold voltage.

[0017] Figure 5 This is a schematic diagram of a type of sensing circuit that can be used with various embodiments.

[0018] Figure 6This is a conceptual diagram of the current flowing through a memory cell in response to the application of a control gate voltage, which varies with a threshold voltage, according to an embodiment.

[0019] Figures 7A-7C According to an example of an embodiment Figures 4A-4C A conceptual diagram depicting the distribution of the nearest threshold voltage.

[0020] Figure 8 The timing diagram, based on an embodiment, generally depicts, for example... Figure 5 The voltage levels of each node in the sensing circuit depicted in the diagram at each stage of the sensing operation.

[0021] Figure 9 A flowchart depicting a method for operating a memory according to an embodiment. Detailed Implementation

[0022] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and in which specific embodiments are illustrated by way of description. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded in a limiting sense.

[0023] For example, as used herein, the term "semiconductor" can refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0024] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0025] This article should recognize that even when expected values ​​are equal, the variability and precision of industrial processing and operation can lead to differences from the expected values. These variability and precision typically depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then these values ​​are considered equal regardless of their actual results.

[0026] Figure 1 This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100 according to an embodiment, which communicates as part of a third device in the form of an electronic system with a second device in the form of a processor 130. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and so on. The processor 130 is, for example, a controller external to the memory device 100; it can be a memory controller or another external host device.

[0027] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access lines (often referred to as word lines), while memory cells in logical columns are typically selectively connected to the same data lines (often referred to as bit lines). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the image) can be programmed into one of at least two target data states.

[0028] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 100 and outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0029] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a group of memory cells in memory cell array 104, e.g., a reserved block of memory cells.

[0030] Control logic 116 can also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, as directed by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; new data from I / O control circuitry system 112 can then be latched in cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry system 112 for output to external processor 130; new data can then be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 can form a page buffer of memory device 100 (e.g., can form a portion thereof). The page buffer can further include sensing devices ( Figure 1 (Not shown in the image) is used to sense the data status of memory cells in memory cell array 104, for example, by sensing the status of data lines connected to the memory cells. Status register 122 can communicate with I / O control circuitry system 112 and control logic 116 to latch status information for output to processor 130.

[0031] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may also be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134, and outputs data to the processor 130 via I / O bus 134.

[0032] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then the commands can be written to command register 124. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then the addresses can be written to address register 114. Data can be received via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device at I / O control circuitry system 112, and then the data can be written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and the data can be written directly to data register 120. Data can also be output via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device. While references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via an external device (e.g., processor 130).

[0033] Those skilled in the art should understand that additional circuitry and signals can be provided, and Figure 1 The memory device 100 has been simplified. It should be recognized that the reference... Figure 1 The functionality of the described individual block components may not necessarily need to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be used to perform... Figure 1 The functionality can exceed that of a single block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0034] Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0035] Figure 2A It can be used for reference. Figure 1 A schematic diagram of a portion of a memory cell array 200A (e.g., a NAND memory array) of the aforementioned type of memory, for example, as part of memory cell array 104. Memory array 200A includes access lines (e.g., word lines) 2020 to 202... N And data lines (e.g., bit lines) 2040 to 204 M Access line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity (e.g., to form a p-well) or n-type conductivity (e.g., to form an n-well).

[0036] The memory array 200A can be arranged in rows (each row corresponds to access lines 202) and columns (each column corresponds to data lines 204). Each column can contain a string of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and further include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory and are often alternatively incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0037] The memory cells 208 of each NAND string 206 may be connected in series between select gate 210 (e.g., a field-effect transistor) and select gate 212 (e.g., a field-effect transistor), wherein the select gate 210 is, for example, select gate 2100 to 210. M One of them (e.g., a source-select transistor, often referred to as a select-gate-source transistor), wherein the select gate 212 is, for example, select gates 2120 to 212. MOne of them (for example, a drain-select transistor, often referred to as a select-gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0038] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0039] The drain of each select gate 212 can be connected to the data line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0040] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally flat structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the data line 204, and the data line can extend substantially parallel to the plane containing the common source 216.

[0041] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as Figure 2A As shown in the diagram. Data storage structure 234 may include conductive and dielectric structures, while control gate 236 is generally formed of one or more conductive materials. In some cases, memory cell 208 may further have defining source / drain (e.g., source) 230 and defining source / drain (e.g., drain) 232. Memory cells 208 connect their control gate 236 to (and in some cases form) access lines 202.

[0042] A column of memory cells 208 may be one or more NAND strings 206 selectively connected to a given data line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may, but need not, contain all memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given access line 202. For example, commonly connected to access line 202 N Memory cells 208, selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.), can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while being commonly connected to access line 202. N Memory cells 208, selectively connected to odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.), can be another physical page of memory cell 208 (e.g., odd-numbered memory cells). Although data lines 2043-2045 are... Figure 2A Although not explicitly depicted in the diagram, it is clear from the figure that the data lines 204 of the memory cell array 200A can be consecutively numbered from data line 2040 to data line 204. M Other groups of memory cells 208 commonly connected to a given access line 202 may also define physical pages of memory cells 208. For a given memory device, all memory cells commonly connected to a given access line may be considered physical pages of the memory cells. A portion of the physical page of a memory cell (e.g., the upper or lower page of the memory cell) that is read during a single read operation or programmed during a single programmable operation (in some embodiments, it may still be an entire row) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020-202.N All memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, reference to a memory cell page herein refers to a memory cell within a memory cell logical page.

[0043] Although discussed in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0044] Figure 2B It can be used for reference. Figure 1 Another schematic diagram of a portion of the memory cell array 200B in the memory of the aforementioned type, for example, as part of the memory cell array 104. Figure 2B The similar numbered elements in the text correspond to, for example, regarding... Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may have a vertical structure, which may include semiconductor pillars, a portion of which may serve as channel regions for the memory cells of the NAND string 206. The NAND string 206 may be selectively connected to data lines 2040-204 via select transistors 212 (e.g., which may be drain select transistors, commonly referred to as select gate drain). M And selectively connected to the common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of NAND strings 206 can be connected via select lines 2150-215. K Bias selectively activates specific select transistors 212, each located between NAND string 206 and data line 204, to connect to their respective data lines 204. Select transistors 210 can be activated by biasing select line 214. Each access line 202 can be connected to multiple rows of memory cells in memory array 200B. Multiple rows of memory cells that are commonly connected to each other via specific access lines 202 can be collectively referred to as a layer.

[0045] A three-dimensional NAND memory array 200B may be formed above a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used to access the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor structure due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0046] Figure 2C It can be used as a reference, for example, as part of memory cell array 104. Figure 1 Another schematic diagram of a portion of the memory cell array 200C in the memory of the aforementioned type. Figure 2C Elements with similar numbers in the middle correspond to about Figure 2A The provided description indicates that the memory cell array 200C may include a series-connected string of memory cells (e.g., a NAND string) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as shown below. Figure 2A As depicted herein. For example, a portion of memory cell array 200A may be a portion of memory cell array 200C. Figure 2C The NAND string is divided into 206 segments to form memory cell blocks 250, for example, memory cell blocks 2500-250. L Memory cell block 250 may be a group of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 that are associated with a single select line 215, such as select line 2150. The source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 are all from the same source. For example, each memory cell block 2500-250 L They can be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 may not be directly connected to memory cell blocks 2500-250 respectively. L Access lines 202 and select lines 214 and 215 for any other memory cell blocks.

[0047] Data cable 2040-204 MIt can be connected (e.g., selectively connected) to buffer section 240, which may be part of a data buffer for memory. Buffer section 240 may correspond to a memory plane (e.g., a set of memory cell blocks 2500-250). L ). Buffer section 240 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the image).

[0048] although Figure 2C Each memory cell block 250 is depicted with only one select line 215, but the memory cell block 250 may contain NAND strings 206 that are associated with more than one select line 215. For example, the select line 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2B Selection line 2151-215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 commonly associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to the buffer section 240 in response to its respective select line 215.

[0049] Figure 3 This is a conceptual diagram of the threshold voltage range for multiple memory cells. Figure 3 Examples are shown illustrating threshold voltage ranges and their distribution over a group of sixteen-level memory cells (commonly referred to as QLC memory cells). For instance, such memory cells can be programmed to operate within sixteen different threshold voltage ranges of 3300–3300. 15 One of the threshold voltages (Vt) is used, and each threshold voltage range is used to represent the data state corresponding to a four-bit mode. The threshold voltage range 3300 typically has a higher threshold voltage range than the other threshold voltage ranges 3301-330. 15 The large width is because the memory cells are generally all in a data state corresponding to the threshold voltage range of 3300, and then a subset of those memory cells are subsequently programmed to have a data state in the threshold voltage range of 3301-3300. 15 The threshold voltage is one of the values ​​in the range. Since programming operations are typically more incrementally controlled than erasing operations, these threshold voltages range from 3301 to 3301. 15 It can tend to have a more compact distribution.

[0050] Threshold voltage ranges: 3300, 3301, 3302, 3303, 3304, 3305, 3306, 3307, 3308, 3309, 330 10 330 11 330 12 330 13 330 14 and 330 15 Each can represent a corresponding data state, such as L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15. As an example, if the threshold voltage of the memory cell is within the first threshold voltage range 3300 of the sixteen threshold voltage ranges, then in this case, the memory cell can store data state L0 with the data value logic '1111', and is generally referred to as the erased state of the memory cell. If the threshold voltage is within the second threshold voltage range 3301 of the sixteen threshold voltage ranges, then in this case, the memory cell can store data state L1 with the data value logic '0111'. If the threshold voltage is within the third threshold voltage range 3302 of the sixteen threshold voltage ranges, then in this case, the memory cell can store data state L2 with the data value logic '0011', and so on. Table 1 provides one possible correspondence between data states and their corresponding logical data values. Other assignments from data states to logical data values ​​are known. As used herein, memory cells in the lowest data state (e.g., erased state or L0 data state) will be considered to be programmed into the lowest data state. For example, the information in Table 1 may be contained in trim register 128.

[0051] Table 1

[0052] Data state Logical data value L0 1111 L1 0111 L2 0011 L3 1011 L4 1001 L5 0001 L6 0101 L7 1101 L8 1100 L9 0100 L10 0000 L11 1000 L12 1010 L13 0010 L14 0110 L15 1110

[0053] As the size of memory cells decreases, the associated data storage structures typically become smaller. Furthermore, with more levels of data state stored within memory cells, distinguishing between data states can become more difficult.

[0054] Figures 4A-4CThis is a conceptual diagram of threshold voltage distribution. The threshold voltage of a memory cell can be shifted due to read interference and / or other phenomena such as rapid charge loss (QCL) and accumulated charge loss. In read interference, the threshold voltage of a memory cell can shift in response to the voltage applied to the memory cell to facilitate access to a selected target memory cell for sensing, for example, by increasing the threshold voltage of the memory cell. QCL is an electron decapsulation near the gate dielectric interface into the channel region of the memory cell and can cause an instantaneous Vt shift after a programming pulse. When the memory cell passes through a verification operation, the programmed threshold voltage may appear higher due to the trapped charge in the gate dielectric. When the memory cell is subsequently sensed, the memory cell may have a Vt lower than the Vt obtained during the programming verification operation due to charge leakage from the gate dielectric into the channel region. Accumulated charge loss can occur over the programmed data years, such as the time between the programmed data and the sensed data. This charge loss becomes more pronounced as the data storage structure becomes smaller. These phenomena make it more difficult to accurately determine the data state, because the threshold voltage of the memory cell may shift sufficiently to place it in a threshold voltage distribution of a data state that is different from the original target data state.

[0055] Figure 4A This is a conceptual diagram of the threshold voltage distribution after programming, for example, without net charge loss or net charge gain. Threshold voltage distribution 330 X and 330 X+1 It can represent any two adjacent threshold voltage distributions, which represent the data state to which a memory cell can be assigned, that is, for Figure 3 In an instance, X can have any integer value from 0 to 14. The threshold voltage distribution typically undergoes expansion after programming, which can lead to overlap in the threshold voltage distributions of memory cells programmed to the corresponding data states, such as threshold voltage distribution 330. X and 330 X+1 As depicted. Arrow 436 may represent a sensed voltage used to distinguish between these two data states; for example, a memory cell that is considered to be activated first in response to a voltage level corresponding to arrow 436 may be considered to be in threshold voltage distribution 330. X Inside. Ideally, the sensed voltage at the local minimum between two threshold voltage distributions (e.g. Figure 4A As shown, it is expected that the memory cells of the two adjacent threshold voltage distributions can be assigned to the correct data states most accurately.

[0056] Figure 4B The threshold voltage distribution shifted due to charge loss 330 X and 330 X+1The conceptual diagram shows that the charge loss can occur, for example, due to QCL and / or accumulated charge loss. In response to the charge loss, the threshold voltage distribution is 330. X and 330 X+1 Typically, the offset relative to the sensed voltage may be lower. When the sensed voltage is above the local minimum, the threshold voltage distribution can be accurately assigned. X Additional memory cells, but threshold voltage distribution 330 X+1 More memory cells may be incorrectly assigned. Figure 4C The threshold voltage distribution shifted due to charge gain 330 X and 330 X+1 The conceptual diagram shows that the charge gain could be caused, for example, by read interference. In response to the charge gain, the threshold voltage distribution is 330. X and 330 X+1 Typically, the deviation may be higher relative to the sensed voltage. When the sensed voltage is below the local minimum, the threshold voltage distribution can be accurately assigned. X+1 Additional memory cells, but threshold voltage distribution 330 X More memory cells may be incorrectly assigned. This competing phenomenon, with some raising the threshold voltage and others lowering it, can complicate reliable sensing of the data state throughout the lifetime of the memory device. Various embodiments seek to determine the data state of memory cells despite these variations in the threshold voltage distribution.

[0057] Sensing circuits are typically used in memory devices to perform sensing (e.g., read and / or verification) operations on each of one or more selected (e.g., target) memory cells within the memory device. The sensing operation can be a read operation, such as providing data output from a memory cell array, or a verification operation, such as verifying whether a programming pulse has successfully changed the threshold voltage of the target memory cell to indicate its desired data state. Figure 5 A sensing circuit 500 of a type that can be used with various embodiments is shown. The sensing circuit 500 is shown connected to a specific NAND string 206 via a specific data line 204, for example... Figure 2A This is shown in more detail below. It should be noted that... Figure 5 Selection transistors 210 and 212, which selectively connect the NAND string 206 to the source 216 and the data line 204, respectively, are not shown. Although the discussion pertains to the use of the sensing circuit 500 with the NAND string 206, other memory structures and architectures are also suitable for use with the sensing circuit 500, wherein a current path can be selectively formed between the data line 204 and the source 216 depending on the data state of the selected memory cell to be sensed.

[0058] As part of the sensing operation, for example, the pre-charging part of the sensing operation, the sensing circuit 500 can pre-charge the sensing node 540, TC node 574, and data line 204 by: biasing (e.g., driving) the signal line 542 to a specific voltage level sufficient to activate the transistor 544 (e.g., the voltage level of the control signal pbiasp) to activate the pre-charge transistor (e.g., a p-type field-effect transistor or pFET) 544; and biasing the signal line 548 to a specific voltage level sufficient to activate the transistor 546 (e.g., the voltage level of the control signal pbiasp) to activate the pre-charge transistor 544. The sensing circuit 500 is activated by biasing signal line 552 to a specific voltage level sufficient to activate transistor 550 (e.g., the voltage level of control signal blclamp2); and the isolation transistor 562 is activated by biasing signal line 564 to a specific voltage level sufficient to activate transistor 562 (e.g., the voltage level of control signal tc_iso). Control signals for the sensing circuit 500 may be provided by an internal controller (e.g., control logic 116) of the memory device 100. Such control signals (e.g., both voltage levels and timing) may be defined by sensing operations and distinguished from signals generated in response to performing sensing operations (e.g., voltage levels generated at output 566 of the sensing circuit 500 (e.g., output signal sa_out), voltage levels generated at sensing node 540, or voltage levels generated at tc node 562). Output 566 may have an initial logic high level during the pre-charge portion of the sensing operation and may be connected to the input of inverter 568 such that a transistor 570 (e.g., a pFET) whose control gate is connected to the output of inverter 568 may be activated. This connects sensing node 540, TC node 574, and data line 204 to voltage node 572 configured to receive voltage level Vreg2.

[0059] TC node 574 may be connected to one electrode of capacitor (e.g., capacitor) 576, the control gate of transistor (e.g., nFET) 578, and the source / drain of transistor (e.g., nFET) 580, which is configured to receive the control signal blc1 signal line 582. Transistor 580 may remain deactivated during sensing operation. Capacitor 576 may have its second electrode connected to the output of variable voltage node (e.g., voltage regulator) 584. Variable voltage node 584 may be further connected to one or more additional capacitors 576 of other sensing circuitry 500. Although capacitor 576 in Figure 5While depicted as a capacitor, it should be understood that in other instances, capacitor 576 may refer to a portion of a circuit (e.g., a sensing circuit) that has a capacitance (e.g., a predefined capacitance) and is configured to influence (e.g., capacitively influence) the voltage level of tc node 574 in response to an applied voltage from voltage node 584 (which may contain one or more active / passive elements).

[0060] A sensing enable transistor (e.g., an nFET) 586 may be connected between the source / drain of transistor 578 and the output 566 of sensing circuit 500, and its control gate may be connected to signal line 588 to receive a control signal senb. Transistor 578 may have its other source / drain connected to a voltage node (e.g., a reference potential node) 590. Voltage node 590 may be configured to receive a reference potential, such as ground, 0V, or a supply voltage Vss.

[0061] After precharging TC node 574 and data line 204, an additional part of the sensing operation can be performed to detect whether the precharged data line 204 and TC node 574 have discharged during the sensing operation, thereby determining the data state of the selected memory cell for sensing. Generally, after precharging TC node 574 and data line 204, data line 204 can then be selectively connected to source 216, depending on whether the selected memory cell for sensing is activated or deactivated in response to a sensing voltage applied to its control gate. Then, if current flows through NAND string 206, data line 204 and TC node 574 can discharge. If the voltage level of data line 204 is lower than the precharge voltage level due to the current flowing through NAND string 206, the voltage level of TC node 574 will similarly experience a decrease. If the voltage level of data line 204 remains at the precharge voltage level, for example when the selected memory cell for sensing remains deactivated, then the voltage level of TC node 574 can remain at its precharge (or boosted) voltage level. TC node 574 can then be isolated from data line 204, for example, by deactivating transistor 562 and / or transistor 546.

[0062] When transistor 586 is activated and the voltage level of TC node 574 is applied to the control gate of transistor 578, voltage node 590 can be selectively connected to output 566 based on the voltage level of TC node 574. Output 566 may have a specific logic level (e.g., logic high) before sensing. If the voltage level of voltage node 590 is applied to output 566 when transistor 586 is activated, its logic level can change, for example, from logic high to logic low, and if voltage node 590 remains isolated from output 566 when transistor 586 is activated, its logic level can remain at the specific logic level.

[0063] Various embodiments may utilize boosting and deboosting of TC node 574 during sensing operation. Boosting (e.g., capacitively coupling it to a first boost voltage level) and deboosting (e.g., capacitively coupling it to a lower second buck voltage level) of TC node 574 may be used, for example, to facilitate higher development overhead. By boosting TC node 574 before the sensing node development time, the voltage level of TC node 574 can be allowed to develop for a longer period without prematurely indicating current in data line 204. Subsequent deboosting of TC node 574 after isolation from data line 204 and NAND string 206 may allow the voltage level of TC node 574 to drop below the trigger point (e.g., threshold voltage) of transistor 578 to indicate detected current (e.g., a threshold level of the current).

[0064] The trigger point of the sensing circuit 500 may typically depend on the threshold voltage of the transistor 578. The sensing circuit 500 is typically configured to have a trigger point close to a pre-charge voltage level (e.g., a sensing threshold level), which may be established on the TC node 574 before sensing a selected memory cell. The trigger point may be a specific voltage level on the TC node 574, wherein the sensing circuit 500 outputs a first logic level indicating a first state of the TC node 574, for example, when the voltage level of the TC node 574 is equal to or higher than the trigger point. For example, when the voltage level of the TC node 574 is lower than the trigger point, the sensing circuit 500 may output a second logic level indicating a second state of the TC node 574. The state of the TC node 574 can be used to provide an indication of the data state of the sensed memory cell.

[0065] It should be noted that, compared to data lines corresponding to activated memory cells where the threshold voltage and the sensed voltage applied to their control gate are farther apart, data lines corresponding to activated memory cells where the threshold voltage and the sensed voltage applied to their control gate are expected to experience lower discharge levels and higher resulting voltage levels at tc node 574. This phenomenon can be expected to alter the current demand from capacitor 576 in response to the changing voltage levels at tc node 574.

[0066] Various embodiments use indications of the current demand of capacitor 576 during sensing operation to estimate conditions for the activation of memory cells that indicate a threshold voltage below a local minimum of two adjacent threshold voltage distributions and for the deactivation of memory cells that indicate a threshold voltage above a local minimum. By obtaining information about the offset value and direction of the threshold voltage distribution, decisions regarding deboosting conditions can be made.

[0067] Figure 6This is a conceptual diagram of the current flowing through a memory cell in response to an applied control gate voltage, varying with a threshold voltage, according to an embodiment. The current level of the memory cell may be represented by line 640. Vt_target may represent a target threshold voltage and may correspond to a voltage level applied to a selected access line for sensing operation of one or more memory cells connected to said access line. It may be necessary to consider memory cells with a threshold voltage less than Atarget as being deactivated in response to the application of a sensing voltage to their control gate. However, it should be noted that memory cells with a threshold voltage greater than Vt_target may be expected to experience some current, although less than the target current Atarget. Similarly, it may be expected that memory cells with a threshold voltage less than Vt_target may experience current greater than the target current level Atarget.

[0068] Referring to the sensing circuit 500, current above current level A0 can initially be supplied from capacitor 576, but can subsequently be supplied from voltage node 572. Current level A0 can depend on the voltage level applied to capacitor 576 by variable voltage node 584. Current below current level A0 occurring at threshold voltage level Vt0 can be supplied from capacitor 576 in response to the voltage level applied by variable voltage node 584. Line 642 can represent the steady-state current demand on variable voltage node 584, which varies with the threshold voltage level of the memory cell. As depicted, the steady-state current demand on variable voltage node 584 can be equal to the current level A0 at threshold voltage level Vt0, and can follow the current level of the memory cell to obtain a threshold voltage level above threshold voltage level Vt0.

[0069] Figures 7A-7C According to an example of an embodiment Figures 4A-4C A conceptual diagram depicting the distribution of the proximity threshold voltage. Threshold voltage distribution 330 X and 330 X+1 It can represent any two adjacent threshold voltage distributions, which represent the data state to which a memory cell can be assigned, that is, for Figure 3 For each instance, X can have any integer value from 0 to 14. Arrow 736 represents the target threshold voltage level Vt_target, and arrow 738 represents the threshold voltage level Vt0.

[0070] exist Figure 7A In the diagram, the shaded region 739a can be represented by the threshold voltage distribution 330. X and 330 X+1 The current supplied to the variable voltage nodes 584 of the memory cells, if these memory cells do not experience net charge gain or charge loss, then the threshold voltage distribution 330 X and 330 X+1The threshold voltage is between Vt0 and Vt_target. Figure 7B In the diagram, the shaded area 739b can represent the threshold voltage distribution 330. X and 330 X+1 The current supplied to the variable voltage nodes 584 of the memory cells determines the threshold voltage distribution 330 if these memory cells experience charge loss. X and 330 X+1 The threshold voltage is between Vt0 and Vt_target. And... Figure 7C In the diagram, the shaded area 739c represents the threshold voltage distribution 330. X and 330 X+1 The current supplied to the variable voltage nodes 584 of the memory cells, if these memory cells experience charge gain, then the threshold voltage distribution 330 X and 330 X+1 The threshold voltage is between Vt0 and Vt_target. For example... Figures 7A-7C As depicted, a memory cell experiencing charge loss may be expected to experience a lower current demand from its variable voltage node 584, relative to a memory cell that does not experience net charge loss or charge gain. Conversely, a memory cell experiencing charge gain may be expected to experience a higher current demand from its variable voltage node 584, relative to a memory cell that does not experience net charge loss or charge gain.

[0071] Assuming the magnitude of charge loss or charge gain is not too large, for example, at the point where the aforementioned relationship begins to reverse, the relative magnitude of current demand can be used to indicate the direction and magnitude of the threshold voltage offset. In response to determining the expected direction and magnitude of the threshold voltage offset, a deboost voltage level that can be expected to compensate for the detected threshold voltage offset can be determined. This may result in memory cells with threshold voltages above a local minimum between two adjacent threshold voltage distributions being considered deactivated, while memory cells with threshold voltages below a local minimum being considered activated. Alternatively or additionally, the relationship between the desired deboost voltage level and current demand can be expressed as a function, or stored in a lookup table located in memory or otherwise accessible to memory. Generally, a lower deboost voltage level can be applied in response to charge gain, while a higher deboost voltage level can be applied in response to charge loss.

[0072] Table 2 can be seen as an example of a lookup table for the deboost voltage level that varies with the measured current demand. In Table 2, Vdefault can represent the default deboost voltage level, which can be used, for example, if little or no threshold voltage offset is detected. The relationship between the various deboost voltage levels can be V1>V2>Vdefault>V3>V4. Although five rows of the lookup table are depicted in Table 2, fewer or more rows can be used.

[0073] Table 2

[0074] The boost voltage level varies with the measured current demand.

[0075]

[0076]

[0077] Figure 8 The timing diagram, based on an embodiment, generally depicts, for example... Figure 5 The voltage levels of each node of the sensing circuit 500 depicted in the diagram are shown at various stages of the sensing operation. (Reference) Figure 8 and 5 Trajectory 884 may represent the voltage level of the output of variable voltage node 584, trajectory 864 may represent the voltage level of the control signal tc_iso applied to the signal line 564 connected to the control gate of transistor 562, and trajectory 852 may represent the voltage level of the control signal blclamp2 applied to the signal line 552 connected to the control gate of transistor 550.

[0078] During the pre-charge and boost phases of the sensing operation, the voltage level of the control signal tc_iso (track 864) is sufficient to initially activate transistor 562, and the voltage level of the control signal blclamp2 (track 852) is sufficient to initially activate transistor 550. Then, the voltage level of the output of the variable voltage node 584 (track 884) can be increased from the initial voltage level 883 to the boost voltage level 885. The initial voltage level 883 can be a reference potential, such as ground, Vss, or 0V. At or near time t1, the voltage level of the control signal blclamp2 can be decreased.

[0079] At time t1, TC node 574 is allowed to develop, for example, selectively discharging based on whether the NAND string 206 connected to data line 204 conducts current, such as whether a selected memory cell conducts current. This can be referred to as the TC node development phase of the sensing operation. If the current level of the selected memory cell is higher than A0 ( Figure 6If the current level of the selected memory cell is below A0, then transistor 550 can be deactivated, and the memory cell current can be supplied by voltage node 584. At time t2, the control signal tc_iso can be decreased to deactivate transistor 562 during subsequent deboosting and disconnect tc node 574 from data line 204. After time t2, the voltage level of the output of variable voltage node 584 can be decreased (e.g., deboosted) to deboost voltage level 887, and the data value can be sensed and latched in a manner well understood in the art.

[0080] For various embodiments, the current demand of capacitor 576 corresponding to a set of sensing circuits for a selected group of memory cells to be sensed can be measured during time period 870. This may include measuring the current demand of one or more voltage nodes 584 connected to the set of sensing circuits. The set of sensing circuits may include each sensing circuit configured to sense the data state of selected memory cells to be sensed during sensing operation, or each sensing circuit configured to sense the data state of a selected subset of memory cells to be sensed during sensing operation. For example, a logical page of selected memory cells to be sensed during sensing operation may include 16K memory cells connected to selected access lines, with NAND strings of the selected access lines connected to 16K sensing circuits respectively. The measurement of current demand may be based on each voltage node of the capacitor connected to each of the 16K sensing circuits. It should be noted that a single voltage node may be connected to the capacitor of more than one sensing circuit.

[0081] The threshold voltage offset between logic pages of a memory cell can be variable due to factors such as different manufacturing conditions along the access line, different environmental conditions along the access line, and different programming conditions along the access line. Therefore, it may be beneficial to perform current demand measurements on a subset of selected memory cells used for sensing operations, which may be expected to experience similar or more similar threshold voltage offset levels. For example, the 16K memory cells of the logic page in the aforementioned example can be divided into four subsets, each with 4K memory cells. Each subset of memory cells can represent a group of consecutive memory cells along a selected access line. Variable voltage nodes typically correspond to only one subset of memory cells.

[0082] As previously mentioned, the threshold voltage level Vt0 may depend on the boost voltage level 885. For embodiments that determine the current requirements corresponding to a subset of memory cells for sensing operations, different boost voltage levels can be used to obtain additional information about the magnitude of any threshold voltage offset. For example, refer to... Figure 6Moving Vt0 changes the cell current level that can be supplied by the capacitor and therefore by the variable voltage node. By comparing the current demand for sensing a subset of memory cells using a first boost voltage level with the current demand for sensing a different subset of memory cells using a second boost voltage level different from the first boost voltage level, information indicating the number of memory cells between Vt0 for the first boost voltage level and Vt0 for the second boost voltage level can be determined. This information can better inform the adjustment amount of the boost voltage level.

[0083] Time period 870 may represent a time period extending from time t2 (e.g., when TC node 574 is isolated from data line 204) to a time prior to time t2. Time period 870 may represent the last 20% of the TC node development phase of the sensing operation. Alternatively, time period 870 may represent a time period less than the last 20% of the TC node development phase of the sensing operation.

[0084] The deboost voltage level 887 can be selected in response to a measurement of the current demand. If the current demand is determined to be within a predefined range, which may include a target current level, then the deboost voltage level 887 can be selected as a default value, which is selected in response to the desired operation of the sensing circuitry under the assumption that the memory cell does not experience net charge gain or charge loss. For current demands determined to be outside the predefined range, the deboost voltage level 887 can be selected to be higher or lower than the default value to compensate for detected threshold voltage offsets. Selecting the deboost voltage level 887 in response to a certain level of current demand may include selecting a voltage difference 889 in response to the level of current demand and adding the voltage difference 889 (e.g., the absolute value of the voltage difference 889) to an initial voltage level 883. Generally, a lower deboost voltage level (e.g., closer to the initial voltage level 883 than the default value) can be applied in response to charge gain, and a higher deboost voltage level (e.g., further away from the initial voltage level 883 than the default value) can be applied in response to charge loss.

[0085] Figure 9 A flowchart depicts a method for operating a memory according to an embodiment, such as during a sensing operation. The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller, such as control logic 116, to cause the memory (e.g., associated components of the memory) to perform the method.

[0086] At 901, a boost voltage level can be applied to each of the plurality of capacitors, each capacitor being connected to a corresponding node in the plurality of nodes. For example, during and as part of a sensing operation of a plurality of memory cells selected for sensing operation, the boost voltage level can be applied to capacitor 576 via variable voltage node 584. The plurality of memory cells may comprise each memory cell selected for sensing operation or all memory cells of a subset of memory cells selected for sensing operation. Each capacitor 576 can be connected to a corresponding TC node 574. At 903, each of the plurality of nodes can be selectively discharged via a corresponding memory cell of the plurality of memory cells selected for sensing operation and connected to the corresponding node in the plurality of nodes. For example, each TC node 574 can be selectively discharged to source 216 via a corresponding memory cell of a corresponding NAND string 206, depending on whether the memory cell is activated in response to a sensing voltage applied to its control gate, for example, depending on its data state. Typically, all remaining memory cells of each NAND string 206 can receive a pass voltage sufficient to activate these memory cells, regardless of their data state.

[0087] At 905, when each node is connected to its corresponding memory cell, the current demand of multiple capacitors can be measured. Measuring the current demand of the capacitors may include measuring the current demand of a voltage node (e.g., a variable voltage node) connected to one electrode of each capacitor, or it may include measuring the current demand of multiple voltage nodes (e.g., variable voltage nodes), each voltage node connected to one or more of the multiple capacitors, and summing those measured current demands. At 907, each of the multiple nodes can be isolated from its corresponding memory cell. For example, each tc node 574 can be isolated from its corresponding NAND string 206 by deactivating the corresponding transistor 562.

[0088] At position 909, the boost voltage level can be determined in response to the measured current demand. (See reference...) Figure 6 and 7AAs discussed in -7C, the current demand of capacitor 576 can be substantially determined by the threshold voltage level of the memory cell connected to it relative to the voltage level of the sensed voltage applied to its control gate. At 911, a deboost voltage level can be applied to each of the plurality of capacitors. At 913, when a deboost voltage level is applied to each of the plurality of capacitors, the data state of each of the plurality of memory cells can be determined. For example, if the voltage level of tc node 574 is below the trigger point of transistor 578 (e.g., below the threshold voltage), then transistor 578 can be deactivated. When transistor 586 is activated, the output 566 of the sensing circuit can remain isolated from voltage node 590 and thus remain in a logic high state, indicating that the memory cell is considered to be activated in response to the sensed voltage. Conversely, if the voltage level of tc node 574 is above the trigger point of transistor 578 (e.g., above the threshold voltage), then transistor 578 can be activated. When transistor 586 is activated, the output 566 of the sensing circuit can be connected to voltage node 590 and thus transitions to a logic low state, indicating that the memory cell is considered to be deactivated in response to the sensed voltage. It should be noted that various embodiments can help to more accurately determine the expected data state by using a default deboost voltage level, and can promote such increased accuracy without sacrificing read time.

[0089] in conclusion

[0090] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that any arrangement is expected to achieve the same purpose in lieu of the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory, comprising: Memory cell array; Multiple sensing circuits, each of the multiple sensing circuits including a corresponding capacitor of a plurality of capacitors, wherein each of the plurality of capacitors is connected to a corresponding node of a plurality of nodes, and wherein each of the plurality of nodes is selectively connected to a memory cell in the memory cell array. as well as A controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the following operations: Apply a boost voltage level to each of the plurality of capacitors; Each of the plurality of nodes is selectively discharged by selecting a corresponding memory cell from a plurality of memory cells in the memory cell array used for sensing operations, wherein each of the plurality of memory cells is connected to a corresponding node among the plurality of nodes; When each of the plurality of nodes is connected to a corresponding memory cell in the plurality of memory cells, the current demand of the plurality of capacitors is measured; Isolate each of the plurality of nodes from the corresponding memory unit of the plurality of memory units; The boost voltage level is determined in response to the measured current demand; Apply the deboost voltage level to each of the plurality of capacitors; as well as When the deboost voltage level is applied to each of the plurality of capacitors, the corresponding data state of each of the plurality of memory cells is determined.

2. The memory of claim 1, wherein the controller is configured to cause the memory to determine the deboost voltage level in response to the measured current demand before isolating each of the plurality of nodes from a corresponding memory cell of the plurality of memory cells.

3. The memory of claim 1, wherein the deboost voltage level is lower than the boost voltage level and higher than the reference potential.

4. The memory of claim 1, wherein the controller is configured to determine the deboost voltage level in response to the measured current demand, the controller is configured to cause the memory to select a value of the deboost voltage level from a lookup table.

5. The memory of claim 1, wherein the controller is configured to cause the memory to determine a deboost voltage level in response to the measured current demand, comprising the controller being configured to cause the memory to determine that the deboost voltage level is higher than a default voltage level in response to the measured current demand being lower than a threshold, and to determine that the deboost voltage level is lower than the default voltage level in response to the measured current demand being higher than the threshold.

6. The memory of claim 5, wherein the controller is configured to cause the memory to determine that the deboost voltage level is higher than the default voltage level in response to the measured current demand being lower than the threshold and to determine that the deboost voltage level is lower than the default voltage level in response to the measured current demand being higher than the threshold includes the controller being configured to cause the memory to determine that the deboost voltage level is higher than the default voltage level in response to the measured current demand being lower than a value range containing the threshold and to determine that the deboost voltage level is lower than the default voltage level in response to the measured current demand being higher than the value range containing the threshold.

7. The memory of claim 1, wherein the plurality of memory cells selected for the sensing operation includes all memory cells selected for the sensing operation.

8. The memory of claim 1, wherein the controller is configured to cause the memory to measure the current demand of the plurality of capacitors, the controller being configured to cause the memory to measure the current demand of one or more voltage nodes, each of the one or more voltage nodes being connected to a corresponding one or more capacitors of the plurality of capacitors.

9. The memory of claim 8, wherein the controller is configured to cause the memory to measure the current demand of one or more voltage nodes, including the controller being configured to cause the memory to measure a single voltage node connected to each of the plurality of capacitors.

10. The memory of claim 1, wherein the controller is configured to cause the memory to selectively discharge each of the plurality of nodes through a respective memory cell selected for the sensing operation, comprising the controller being configured to cause the memory to selectively discharge each of the plurality of nodes through a respective memory cell when a sensing voltage is applied to an access line of the memory connected to a respective control gate of each of the plurality of memory cells.

11. The memory of claim 10, wherein each of the plurality of memory cells is a memory cell of a corresponding serially connected string of memory cells in a plurality of serially connected strings of memory cells in the memory cell array.

12. The memory of claim 11, wherein the controller is configured to cause the memory to selectively discharge each of the plurality of nodes through a corresponding memory cell selected for the sensing operation, further comprising the controller being configured to cause the memory to selectively discharge each of the plurality of nodes through a corresponding memory cell when each of the plurality of cascaded memory cell strings is not activated by a memory cell selected for the sensing operation.

13. A memory comprising: Memory cell array; Multiple sensing circuits, each of the multiple sensing circuits including a corresponding capacitor of a plurality of capacitors, wherein each of the plurality of capacitors is connected to a corresponding node of a plurality of nodes, and wherein each of the plurality of nodes is selectively connected to a memory cell in the memory cell array. as well as A controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the following operations: A boost voltage level is applied to each capacitor in a first subset of the plurality of capacitors and to each capacitor in a second subset of the plurality of capacitors that is different from the first subset of the plurality of capacitors; Each of the plurality of nodes is selectively discharged by selecting a corresponding memory cell from a plurality of memory cells in the memory cell array used for sensing operations, wherein each of the plurality of memory cells is connected to a corresponding node among the plurality of nodes; When each of the plurality of nodes is connected to a corresponding memory cell in the plurality of memory cells, the first current demand of the first capacitor subset is measured and the second current demand of the second capacitor subset is measured. Isolate each of the plurality of nodes from the corresponding memory unit of the plurality of memory units; A first deboost voltage level is determined in response to a measured first current demand, and a second deboost voltage level is determined in response to a measured second current demand; The first deboost voltage level is applied to each capacitor in the first capacitor subset, and the second deboost voltage level is applied to each capacitor in the second capacitor subset; as well as When the first deboost voltage level is applied to each capacitor in the first capacitor subset and when the second deboost voltage level is applied to each capacitor in the second capacitor subset, the corresponding data state of each memory cell in the plurality of memory cells is determined.

14. The memory of claim 13, wherein the controller is further configured to cause the memory to perform the following operations: The boost voltage level is applied to each capacitor in a third subset of the plurality of capacitors, which is different from both the first and second subsets of capacitors. When each of the plurality of nodes is connected to a corresponding memory cell among the plurality of memory cells, the third current requirement of the third capacitor subset is measured; In response to the measured third current demand, the third deboost voltage level is determined; as well as Apply the third deboost voltage level to each capacitor in the third capacitor subset; The controller is configured to cause the memory to determine the corresponding data state of each of the plurality of memory cells when the first deboost voltage level is applied to each capacitor in the first capacitor subset and when the second deboost voltage level is applied to each capacitor in the second capacitor subset, including: the controller is configured to cause the memory to determine the corresponding data state of each of the plurality of memory cells when the first deboost voltage level is applied to each capacitor in the first capacitor subset, when the second deboost voltage level is applied to each capacitor in the second capacitor subset, and when the third deboost voltage level is applied to each capacitor in the third capacitor subset.

15. The memory of claim 13, wherein the union of the first subset of capacitors and the second subset of capacitors comprises each of the plurality of capacitors.

16. The memory of claim 13, wherein the first deboost voltage level and the second deboost voltage level are both lower than the boost voltage level.

17. The memory of claim 13, wherein the controller is configured to cause the memory to apply the boost voltage level to each capacitor in the first subset of capacitors and to each capacitor in the second subset of capacitors, comprising: The controller is configured to cause the memory to increase the voltage level applied to each capacitor in the first capacitor subset and each capacitor in the second capacitor subset from the initial voltage level to the boost voltage level.

18. The memory of claim 17, wherein the controller is configured to cause the memory to determine the first deboost voltage level in response to the measured first current demand and to determine the second deboost voltage level in response to the measured second current demand, comprising the controller being configured to cause the memory to perform the following operations: A first voltage difference is determined in response to the measured first current demand, and a second voltage difference is determined in response to the measured second current demand; and The first voltage difference is added to the initial voltage level to determine the first deboost voltage level, and the second voltage difference is added to the initial voltage level to determine the second deboost voltage level.

19. A memory comprising: Memory cell array; Multiple sensing circuits, each of the multiple sensing circuits including a corresponding capacitor of a plurality of capacitors, wherein each of the plurality of capacitors is connected to a corresponding node of a plurality of nodes, and wherein each of the plurality of nodes is selectively connected to a memory cell of the memory cell array; as well as A controller for accessing the memory cell array, wherein the controller is configured to cause the memory to perform the following operations: A first boost voltage level is applied to each capacitor in a first subset of the plurality of capacitors, and a second boost voltage level different from the first boost voltage level is applied to each capacitor in a second subset of the plurality of capacitors that is different from the first subset of the plurality of capacitors; Each of the plurality of nodes is selectively discharged by selecting a corresponding memory cell from a plurality of memory cells in the memory cell array used for sensing operations, wherein each of the plurality of memory cells is connected to a corresponding node among the plurality of nodes; When each of the plurality of nodes is connected to a corresponding memory cell in the plurality of memory cells, the first current demand of the first capacitor subset and the second current demand of the second capacitor subset are measured. Isolate each of the plurality of nodes from the corresponding memory unit of the plurality of memory units; The boost voltage level is determined in response to the measured first current demand and the measured second current demand; Apply the deboost voltage level to each of the plurality of capacitors; as well as When the deboost voltage level is applied to each of the plurality of capacitors, the corresponding data state of each of the plurality of memory cells is determined.

20. The memory of claim 19, wherein the union of the first subset of capacitors and the second subset of capacitors comprises less than all of the plurality of capacitors.

21. The memory of claim 19, wherein the controller is further configured to cause the memory to perform the following operations: Apply a third boost voltage level, different from the first boost voltage level and different from the second boost voltage level, to each capacitor in a third subset of capacitors that is different from the first subset of capacitors and different from the second subset of capacitors; as well as When each of the plurality of nodes is connected to a corresponding memory cell among the plurality of memory cells, the third current requirement of the third capacitor subset is measured; The controller is configured to cause the memory to determine the deboost voltage level in response to the measured first current demand and the measured second current demand, including the controller being configured to cause the memory to determine the deboost voltage level in response to the measured first current demand, the measured second current demand, and the measured third current demand.

22. The memory of claim 19, wherein the controller is configured to, in response to the measured first current demand and the measured second current demand, isolate each of the plurality of nodes from a corresponding memory cell of the plurality of memory cells before determining the deboost voltage level.

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