Disposal of reinforcing material structures

Abstract

A method of forming a semiconductor structure includes the steps of: pre-cleaning a surface of a substrate; forming an interface layer on the pre-cleaned surface of the substrate; depositing a high-k dielectric layer on the interface layer; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-k dielectric layer; and performing a post-nitridation anneal process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer.

Description

TECHNICAL FIELD

[0001] Various embodiments described herein relate generally to semiconductor device manufacturing, and more particularly, to systems and methods of forming a high-quality high-k dielectric material layer in a semiconductor structure. BACKGROUND

[0002] As metal-oxide-semiconductor field-effect transistors (MOSFETs) have been scaled down for achieving high device performance and low power consumption, the thickness of a conventional silicon dioxide (SiO2) gate dielectric has been reduced to its physical limit. Therefore, to achieve further scaling, replacing the silicon dioxide gate dielectric with a high-k dielectric material has been inevitable. Among various high-k dielectric materials, hafnium oxide (HfO2) has been applied since the 45 nm MOSFET technology node because hafnium oxide (HfO2) has a high dielectric constant and superior thermal stability on a silicon substrate. However, for further scaling of the equivalent oxide thickness (EOT) of the 32 nm MOSFET technology node and beyond, simply reducing the thickness of the high-k dielectric material layer is problematic because the leakage current through the high-k dielectric material layer increases.

[0003] Therefore, there is a need for systems and methods that can be used to form a thin (e.g., EOT less than 1 nm) high-k dielectric material layer having a chemical structure that can be controlled to ensure desired structural and electrical properties. SUMMARY

[0004] Various embodiments of the present disclosure provide a method of forming a semiconductor structure. The method includes the steps of: pre-cleaning a surface of a substrate; forming an interfacial layer on the pre-cleaned surface of the substrate; depositing a high-k dielectric layer on the interfacial layer; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-k dielectric layer; and performing a post-nitridation anneal process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer.

[0005] Various embodiments of the present disclosure also provide a method of forming a semiconductor structure. The method includes the steps of: pre-cleaning a surface of a substrate; depositing a high-k dielectric layer on the substrate; and performing a plasma nitridation process to insert nitrogen atoms in the deposited high-k dielectric layer.

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, and a system controller. The system controller is configured to: pre-clean a surface of a substrate in the first processing chamber; form an interface layer on the pre-cleaned surface of the substrate in the second processing chamber; deposit a high-k dielectric layer on the interface layer in the third processing chamber; expose the deposited high-k dielectric layer to a nitrogen plasma in the fourth processing chamber; and anneal the plasma-nitrided high-k dielectric layer in the fifth processing chamber. The substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, and the fifth processing chamber without breaking a vacuum environment in the processing system. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order that the foregoing and other features of the present disclosure can be understood in detail, a more particular description will be rendered by reference to certain embodiments thereof which are illustrated in the appended drawings. For purposes of explanation and as illustrated in the drawings, and as it is in the nature of examples to include only those parts pertinent to a complete understanding of the structure and operation thereof, those parts are shown in their most basic form.

[0008] Figure 1 is a schematic top view of an example multi-chamber processing system according to one embodiment.

[0009] Figure 2 is a process flow diagram of a method of forming a semiconductor structure according to one embodiment.

[0010] Figure 3A and Figure 3B is a schematic view of a semiconductor structure according to one embodiment.

[0011] For purposes of clarity, the same reference numbers will be used in the description of the drawings to indicate the same or similar elements. Aspects of one embodiment can be incorporated into other embodiments without further clarifying recitation. DETAILED DESCRIPTION

[0012] As gate structures shrink to smaller dimensions, new material structures are continually sought to provide improvements. The use of high-k dielectric materials increases the dielectric constant of the gate structure as compared to traditional gate structures that utilize materials such as silicon oxide. However, similar to silicon oxide, as the thickness of the gate structure decreases, the leakage current increases. For example, gate leakage increases as the effective oxide thickness decreases. Thus, the inverse relationship between gate leakage and effective oxide thickness can create a limit on the devices produced and transistor performance.

[0013] High-k dielectric materials can provide greater channel mobility as compared to silicon oxide of similar thickness. As the industry continues to seek lower effective oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also referred to as the "k value") of known high-k materials will reach a limit due to morphological characteristics. Conventional techniques have been directed to overcoming the inherent properties of high-k materials, which can set an upper limit on the k value, as well as subsequent device modifications to attempt to incorporate new films.

[0014] The various embodiments described herein provide systems and methods for improving the properties of high-k dielectric materials. By producing high-k dielectric materials that exhibit specific morphologies or grain structures, higher dielectric constants and improved device performance can be achieved. To control grain formation in exemplary devices, treatments can be performed to provide an activated substrate surface that is capable of inducing specific grain growth, as well as stabilization of the film after formation, which can result in higher dielectric constants.

[0015] Figure 1is a schematic top view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102; load lock chambers 104, 106; transfer chambers 108, 110 having respective transfer robots 112, 114; holding chambers 116, 118; and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, wafers in the processing system 100 can be processed in the various chambers and transferred between the various chambers without exposing the wafers to the ambient environment outside of the processing system 100 (e.g., such as an atmospheric environment that can exist in a fab). For example, the wafers can be processed in the various chambers and transferred between the various chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment between the various processes performed on the wafers in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some processing of wafers.

[0016] Examples of processing systems that can be suitably modified in light of the teachings provided herein include the CENTURA® and LYNX® systems, which can be commercially obtained from Applied Materials, Inc., located in Santa Clara, California, USA. Alternatively, An integrated processing system or other suitable processing system. It is contemplated that other processing systems, including those from other manufacturers, can be adapted to benefit from various aspects described herein.

[0017] In Figure 1 In the illustrated example, the factory interface 102 includes a docking station 140 and factory interface robots 142 to assist in transferring wafers. The docking station 140 is configured to receive one or more front opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally includes a blade 148 disposed on an end of the respective factory interface robot 142 configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0018] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 also has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. The ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be, for example, slit valve openings with slit valves for passing wafers therethrough by the transfer robot 112, 114 and for providing a seal between respective chambers to prevent gas passage between chambers. Typically, any port is open for passing a wafer therethrough. Otherwise, the port is closed.

[0019] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidically coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidically coupled to the various chambers. In operation, the factory interface robot 142 transfers a wafer from the FOUP 144 to the load lock chamber 104 or 106 through the port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low pressure or vacuum environment (which can include an inert gas). Thus, the pump down of the load lock chamber 104 or 106 facilitates the transfer of a wafer between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0020] With the wafer in the load lock chamber 104 or 106 that has been pumped down, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 154 or 156. The transfer robot 112 can then transfer the wafer to and / or between any of the processing chambers 120, 122 and the holding chambers 116, 118, transferring the wafer to the processing chambers 120, 122 for processing through the respective ports 162, 164, and to the holding chambers 116, 118 for holding to await further transfer through the respective ports 158, 160. Similarly, the transfer robot 114 can access a wafer in the holding chamber 116 or 118 through the port 166 or 168, and can transfer the wafer to and / or between any of the processing chambers 124, 126, 128, 130 and the holding chambers 116, 118, transferring the wafer to the processing chambers 124, 126, 128, 130 for processing through the respective ports 170, 172, 174, 176, and to the holding chambers 116, 118 for holding to await further transfer through the respective ports 166, 168. The transfer and holding of wafers within and between the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0021] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chamber for processing wafers. In some examples, the processing chamber 122 can be capable of performing a cleaning process, the processing chamber 120 can be capable of performing an etching process, and the processing chambers 124, 126, 128, 130 can be capable of performing respective epitaxial growth processes. The processing chamber 122 can be a SiCoNi TM pre-clean chamber. The processing chamber 120 can be a Selectra TM etch chamber.

[0022] A system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 190 can control operation of the processing system 100 using direct control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100, or by control of controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 is capable of effecting data gathering and feedback from the respective chambers to coordinate operation of the processing system 100.

[0023] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuits 196. The CPU 192 can be one of any form of a general purpose processor that can be used in an industrial setting. The memory 194, or non-transitory computer readable medium, is accessible by the CPU 192 and can be one or more of a number of memory devices, such as RAM, ROM, floppy disk, hard disk or any other form of digital storage. The support circuits 196 are coupled to the CPU 192 and can include cache, clock circuits, input / output subsystems, power supplies, and the like. Various methods disclosed herein can generally be implemented by the CPU 192 executing computer instruction code stored in the memory 194 (or memory of a particular process chamber) as a software routine, under control of the CPU 192. When the computer instruction code is executed by the CPU 192, the CPU 192 controls the chambers to perform processes according to the various methods.

[0024] Other processing systems can employ other configurations. For example, more or fewer processing chambers can be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and hold chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer hold chambers (e.g., no hold chambers) can be implemented as a transfer apparatus in a processing system.

[0025] Figure 2 is a process flow diagram of a method 200 of forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. Figure 3A and Figure 3B are cross-sectional views of portions of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that Figure 3A and Figure 3BOnly a partial schematic of semiconductor structure 300 is shown, as semiconductor structure 300 can include any number of transistor portions and additional material having aspects as shown. It should also be noted that while the method steps shown in Figure 2

[0026] Method 200 begins with a pre-cleaning process in block 210 to pre-clean the surface of substrate 302. The pre-cleaning process can include etching the surface of substrate 302 by a dry etching process or a wet etching process using an etching solution such as a Standard Clean 1 (SC1) etching solution including NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide), and H2O (water), or a dry etching process such as a SiConi TM a remote plasma assisted dry etching process in which the surface of substrate 302 is exposed to N2, NF3, and NH3 plasma byproducts. The pre-cleaning process can be performed in a pre-cleaning chamber such as processing chamber 122 or 120 shown in Figure 1

[0027] In block 220, an interface formation process is performed to form interface layer 304 on the pre-cleaned surface of substrate 302, as shown in Figure 3A The interface formation process can include an appropriate thermal oxidation process such as an enhanced in-situ steam generation (eISSG) process utilizing nitrous oxide (N2O) gas. Interface layer 304 formed in block 220 is a thin amorphous silicon oxide (SiO2) layer having a thickness between about and about , for example about ​​one or more monolayers of silicon oxide. In some embodiments, the interface layer 304 can be formed by an in-situ steam generation (ISSG) process using H2and O2gases or by a rapid thermal oxidation (RTO) process using NH3and O2gases. The interface layer 304 can serve as a nucleation layer for a high-k dielectric material layer to be deposited on the interface layer 304 and improve the quality of the interface between the substrate 302 and the high-k dielectric material layer (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current). The interface formation process can be performed in a processing chamber such as the processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1. Figure 1 The interface formation process in block 220 can be performed in a processing chamber such as the processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1.

[0028] In some embodiments, the interface formation process in block 220 is omitted and the interface layer 304 is not formed prior to deposition of the high-k dielectric material layer on the substrate 302. In this case, the interface layer 304 is formed by the thermal oxidation process in block 250 or block 290 described below, which thermally oxidizes the substrate 302 via the high-k dielectric material layer deposited on the substrate 302. The interface layer 304 formed by the thermal oxidation process in block 250 or block 290 can have a thickness between about 0.3 nm and about 1 nm, for example, a thickness of about 0.5 nm, which can be thick enough to ensure reliable device characteristics (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) and reduce atomic diffusion from the high-k dielectric material layer to the substrate 302.

[0029] In block 230, a deposition process is performed to deposit a high-k dielectric material layer on the exposed surface of the semiconductor structure 300 (i.e., on the interface layer 304 in the case that the interface layer 304 is formed in block 220, as Figure 3BAs shown, a high-κ dielectric layer 306 is deposited on substrate 302 without forming an interface layer 304 in box 220. The high-κ dielectric layer 306 can be formed of a high-κ dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (Y2O3), or aluminum oxide (Al2O3). The deposition process can include atomic layer deposition (ALD) in which metal-containing precursors and oxygen-containing precursors are alternately delivered to the exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged before the oxygen-containing precursor is delivered. The metal can be a transition metal such as hafnium (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb), or yttrium (Y), an alkaline earth metal such as strontium (Sr), or other metals such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal can be used. For example, the oxygen-containing precursor can be or contains water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen and oxygen-containing precursor, plasma-enhanced oxygen containing locally or remotely enhanced oxygen, or any other oxygen-containing material that can combine with the metal to form a layer of metal oxide on substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl4) and the oxidant is water (H2O) to form a hafnium dioxide (HfO2) layer. The ALD process can be performed at a temperature between about 200°C and about 400°C (e.g., about 270°C). As deposited by the ALD process, the high-κ dielectric layer 306 can be amorphous and has a dielectric content between about 200°C and 400°C. With the agreement The thickness between. It can be in, for example... Figure 1 The deposition process is performed in processing chambers such as processing chambers 120, 122, 124, 126, 128, or 130 shown.

[0030] In box 240, an optional post-deposition annealing process is performed to harden and densify the deposited high-κ dielectric layer 306. Crystallization of the deposited high-κ dielectric layer 306 may occur. This post-deposition annealing process may include a thermal annealing process performed in an inert environment (such as nitrogen (N2) and argon (Ar) environment) within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be...Figure 1 Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. This deposition post anneal process can harden and densify the interface layer 304 and the high-k dielectric layer 306 with a thermal method.

[0031] The deposition post anneal process can be performed at a temperature between about 5000C and about 8000C and a pressure between about 0.01 Torr and 10 Torr for a time between about 1 second and about 60 seconds.

[0032] In block 250, an optional re-oxidation process is performed in place of the deposition post anneal process in block 240 to thermally oxidize the substrate 302. The re-oxidation process can include a thermal anneal process in an oxygen (O2), nitrous oxide (N2O), and H2ambient performed in a rapid thermal processing (RTP) chamber, such as a RADOX® chamber available from Applied Materials, Inc. of Santa Clara, California. This RTP chamber can be a TM RADIANCE® chamber available from Applied Materials, Inc. of Santa Clara, California. This RTP chamber can be a Figure 1 Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The re-oxidation process in block 250 can thermally oxidize the underlying layers through the high-k dielectric layer 306, thus thickening the interface layer 304 to a thickness between about and about in the case where the interface layer 304 is formed in block 220, and forming the interface layer 304 in the substrate 302 near the interface with the high-k dielectric layer 306 in the case where the interface layer 304 is not formed in block 220.

[0033] The re-oxidation process can be performed at a temperature between about 4000C and about 9000C and a pressure between about 0.01 Torr and 100 Torr for a time between about 1 second and about 30 seconds.

[0034] In block 260, a plasma nitridation process is performed to insert nitrogen atoms into the voids and defects in the high-k dielectric layer 306. The plasma nitridation process can be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as a DPN chamber available from Applied Materials, Inc. of Santa Clara, California. This DPN chamber can be a Figure 1Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown. This plasma nitriding process exposes the high-κ dielectric layer 306 to nitrogen plasma, which allows nitrogen radicals, or nitrogen atoms, to be incorporated into the high-κ dielectric layer 306 throughout its entire thickness. During this plasma nitriding process, nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in this plasma process include nitrogen-containing gases, such as nitrogen (N2), ammonia (NH3), or mixtures of these gases. In one example, this nitrogen-containing gas is ammonia (NH3) mixed with about 3% to about 8% nitrogen (N2). As a result of nitrogen incorporation into the voids and defects of the deposited high-κ dielectric layer 306, the plasma nitriding process can maintain the thickness of the high-κ dielectric layer 306.

[0035] The nitriding process can be performed at a temperature between approximately 0°C and approximately 500°C for a time between approximately 10 seconds and approximately 300 seconds.

[0036] In block 270, an optional thermal nitriding process is performed to further insert nitrogen atoms into voids and defects in the plasma-nitrided high-k dielectric layer 306. This thermal nitriding process may include a thermal annealing process performed in an ammonia (NH3) environment within a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1 Any of the processing chambers 120, 122, 124, 126, 128 and 130 shown.

[0037] The thermal nitriding process can be performed at a temperature between approximately 700°C and approximately 900°C and a pressure between approximately 10 Torr and 740 Torr for a time between approximately 10 seconds and approximately 300 seconds.

[0038] In box 280, a post-nitriding annealing process is performed to passivate the remaining chemical bonds in the plasma-nitrided high-k dielectric layer 306. This post-nitriding annealing process may include a spike thermal annealing process performed in a nitrogen (N2) and argon (Ar) environment in a rapid thermal processing (RTP) chamber, such as a RADOX chamber available from Applied Materials, Inc., Santa Clara, California, USA. TM A chamber. This RTP chamber can be... Figure 1Any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The nitridation post anneal process can passivate metastable nitrogen bonds formed in the plasma nitridation process in block 240, and crystallization of the amorphous high-k dielectric layer 306 can occur.

[0039] The spike thermal anneal process can be performed at a temperature between about 700 °C and about 850 °C, and at a pressure between about 10 Torr and 740 Torr, for a time between about 1 second and about 30 seconds.

[0040] In block 290, instead of the nitridation post anneal process in block 280, a nitridation post anneal and reoxidation process is performed to simultaneously passivate remaining chemical bonds in the high-k dielectric layer 306 as in block 280 and thermally oxidize the substrate 302 as in block 250. The nitridation post anneal and reoxidation process in block 290 is the same as the reoxidation process in block 250. Therefore, details of the nitridation post anneal and reoxidation process in block 290 are omitted here.

[0041] In various embodiments described herein, systems and methods are provided to form a high quality thin layer of high-k dielectric material. The properties of such a high-k dielectric material layer can be well controlled. For example, the nitridation processes in blocks 260 and 270 can be controlled to provide a nitrogen incorporation in the high-k dielectric layer 306 between about 3 atomic % and about 20 atomic %, to achieve a higher k value than with higher nitrogen incorporation, and better structural stability than with lower nitrogen incorporation. The anneal processes in blocks 240, 270, 280, and 290 can also be controlled to provide grains in the high-k dielectric layer 306 having a size greater than about 10 A, to reduce leakage current flow through the high-k dielectric layer 306.

[0042] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.​

Claims

1. A method for forming a semiconductor structure, the method comprising the following steps: Forming a semiconductor structure includes: Pre-clean the surface of the substrate; An interface layer is formed on the pre-cleaned surface of the substrate; A high-κ dielectric layer is deposited on the interface layer; The substrate is annealed in an oxygen-containing environment to thermally oxidize the underlying layer via the high-κ dielectric layer and thus thicken the interface layer to a level between and The thickness between; A plasma nitriding process is performed to insert nitrogen atoms into the deposited high-κ dielectric layer; and A post-nitriding annealing process is performed to passivate the chemical bonds in the plasma-nitrided high-k dielectric layer.

2. The method of claim 1, wherein the step of forming the semiconductor structure is performed in a processing system without breaking the vacuum.

3. The method of claim 1, wherein The interface layer comprises silicon oxide (SiO2), and The steps for forming the interface layer include: The substrate is thermally oxidized using nitrous oxide (N2O) gas.

4. The method of claim 1, wherein the high-k dielectric layer comprises hafnium oxide (HfO2).

5. The method of claim 1, wherein the plasma nitriding process comprises: The deposited high-k dielectric layer was exposed to a nitrogen plasma using a mixture of nitrogen (N2) and ammonia (NH3).

6. The method of claim 1, wherein the post-nitriding annealing process comprises: The deposited high-κ dielectric layer was subjected to spike annealing at a temperature between 700°C and 850°C in a nitrogen (N2) and argon (Ar) environment.

7. A method for forming a semiconductor structure, the method comprising the following steps: Forming a semiconductor structure includes: Pre-clean the surface of the substrate; A high-κ dielectric layer is deposited on the substrate; A thermal annealing process is performed to thermally oxidize the substrate via the high-k dielectric layer and thus form a layer in the substrate near the interface with the high-k dielectric layer with a thickness between [missing information]. and The interface layer between; and A plasma nitriding process is performed to insert nitrogen atoms into the deposited high-k dielectric layer.

8. The method of claim 7, wherein the step of forming the semiconductor structure is performed in a processing system without breaking the vacuum.

9. The method of claim 7, wherein: The thermal annealing process includes thermally oxidizing the substrate at a temperature between 400°C and 900°C in an environment of oxygen (O2), nitrous oxide (N2O), and H2, wherein the interface layer comprises silicon oxide (SiO2).

10. The method of claim 7, wherein the high-k dielectric layer comprises hafnium oxide (HfO2).

11. The method of claim 7, wherein the plasma nitriding process comprises: The deposited high-k dielectric layer was exposed to a nitrogen plasma using a mixture of nitrogen (N2) and ammonia (NH3).

12. The method of claim 7, further comprising the following steps: Following the plasma nitriding process, a post-nitriding annealing process is performed to passivate the chemical bonds in the plasma-nitrided high-k dielectric layer.

13. The method of claim 12, wherein The hot annealing process includes: The high-κ dielectric layer is annealed at a temperature between 400°C and 900°C in an environment of oxygen (O2), nitrous oxide (N2O), and H2. and The nitriding annealing process includes: performing spike annealing on the plasma-nitrided high-k dielectric layer at a temperature between 700°C and 850°C in a nitrogen (N2) and argon (Ar) environment.

14. The method of claim 7, further comprising the following steps: Following the plasma nitriding process, a re-oxidation process is performed to passivate the remaining chemical bonds in the plasma-nitrided high-k dielectric layer and thermally oxidize the substrate.

15. The method of claim 14, wherein the re-oxidation process comprises: The high-κ dielectric layer is annealed at a temperature between 400°C and 900°C in an environment of oxygen (O2), nitrous oxide (N2O), and H2.

16. A processing system, comprising: First processing chamber; Second processing chamber; The third processing chamber; Fourth processing chamber; Fifth processing chamber; Sixth processing chamber; and System controller, the system controller being configured to: The surface of the substrate is pre-cleaned in the first processing chamber; In the second processing chamber, an interface layer is formed on the pre-cleaned surface of the substrate; In the third processing chamber, a high-k dielectric layer is deposited on the interface layer; In the fourth processing chamber, the substrate is annealed in an oxygen-containing environment to thermally oxidize the underlying layer via the high-k dielectric layer and thus thicken the interface layer to a depth between [missing information]. and The thickness between; In the fifth processing chamber, the deposited high-k dielectric layer is exposed to nitrogen plasma; and In the sixth processing chamber, the high-k dielectric layer after plasma nitriding is annealed. The substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, the fifth processing chamber, and the sixth processing chamber without disrupting the vacuum environment of the processing system.

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