Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, forming a material layer to be etched on the substrate, forming a plurality of mutually separated sacrificial layers on the material layer to be etched, and having a first opening between adjacent sacrificial layers; forming a sidewall material layer at the bottom of the first opening and the sidewall surface and the top surface of the sacrificial layer; forming a protective layer on the surface of the sidewall material layer; forming a first graphic layer on the protective layer, having a first graphic opening in the first graphic layer, and exposing one or more of the first openings in the first graphic opening; forming a barrier layer in the exposed first opening, the top surface of the barrier layer being lower than the top surface of the sacrificial layer; removing the protective layer; removing the sidewall material layer on the bottom surface of the first opening and the top surface of the sacrificial layer; removing the sacrificial layer, and forming a second opening between the remaining sidewall material layers. The present invention improves the stability and accuracy of graphic transfer, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e. the number of internal connection structures of each chip) is gradually increasing, while the geometric size (i.e. the minimum component size that can be produced using process steps) is gradually decreasing, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, as technology nodes continue to shrink, the performance of the resulting semiconductor structures is poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a material layer to be etched is formed; forming a plurality of mutually discrete sacrificial layers on the material layer to be etched, with a first opening between adjacent sacrificial layers; forming a sidewall material layer on the bottom surface and sidewall surface of the first opening, and the sidewall material layer covers the sidewall and top surface of the sacrificial layer; forming a protective layer on the surface of the sidewall material layer; forming a first patterned layer on the protective layer, with a first patterned opening in the first patterned layer, and the first patterned opening exposes one or more of the first openings; forming a blocking layer in the exposed first opening, with the top surface of the blocking layer being lower than the top surface of the sacrificial layer; removing the protective layer; removing the sidewall material layer on the bottom surface of the first opening and the top surface of the sacrificial layer; removing the sacrificial layer to form a second opening between the remaining sidewall material layers.

[0007] Optionally, the material of the protective layer is different from the material of the spacer material layer, and the material of the protective layer includes silicon nitride or silicon nitride oxide.

[0008] Optionally, the process of forming the protective layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0009] Optionally, the thickness of the protective layer is in the range of

[0010] Optionally, the barrier layer includes a low temperature oxide layer or an oxynitride layer.

[0011] Optionally, the step of forming a barrier layer in the exposed first opening includes: forming a barrier material layer in the exposed first opening, wherein the barrier material layer also covers the top surface of the first patterned layer; etching the barrier material layer until the top surface of the barrier material layer is lower than the top surface of the sacrificial layer to form a barrier layer.

[0012] Optionally, an etching selectivity ratio of the barrier material layer and the protective layer is greater than 6:1.

[0013] Optionally, the step of etching the barrier material layer includes: etching the barrier material layer for a first time until the top surface of the barrier material layer is flush with the top surface of the protective layer; and etching the barrier material layer for a second time until the top surface of the barrier material layer is lower than the top surface of the sacrificial layer.

[0014] Optionally, the first etching includes a dry etching process, and the process parameters of the first etching include: the etching atmosphere includes a mixed gas of C4F6 and O2, the power is 200 to 1000 watts, the pressure is 5 to 20 mTorr, the temperature is 30 to 50 degrees Celsius, and the time is 5 to 20 seconds.

[0015] Optionally, the second etching includes a dry etching process, and the process parameters of the second etching include: the etching atmosphere includes a mixed gas of CF4 and CHF3, the power is 900-1500 watts, the pressure is 5-20 mTorr, the temperature is 30-50 degrees Celsius, and the time is 5-10 seconds.

[0016] Optionally, the step of forming a plurality of mutually discrete sacrificial layers on the material layer to be etched includes: forming a sacrificial material layer on the material layer to be etched; forming a second patterned layer on the sacrificial material layer, the second patterned layer having a second patterned opening, the second patterned opening corresponding to the position and size of the first opening; using the second patterned layer as a mask, injecting doped ions into part of the sacrificial material layer; removing the sacrificial material layer injected with doped ions to form mutually discrete sacrificial layers; and removing the second patterned layer.

[0017] Optionally, the step of forming the first patterned layer includes: forming a first patterned material layer on the protective layer, and the first patterned material layer fills the first opening; forming a mask layer on the first patterned material layer, the mask layer having a mask opening, and the mask opening corresponds to the position and size of the first patterned opening; using the mask layer as a mask, etching the first patterned material layer until one or more of the first openings are exposed to form a first patterned layer; and removing the mask layer.

[0018] Optionally, the material of the first patterned layer includes a carbon-containing compound.

[0019] Optionally, the material of the sacrificial layer includes amorphous silicon, amorphous carbon or polycrystalline silicon.

[0020] Optionally, the material layer to be etched includes a single material layer or a multi-layer stacked material layer.

[0021] Optionally, the material of the spacer material layer includes titanium oxide, titanium nitride, silicon nitride, silicon oxide or silicon oxynitride.

[0022] Optionally, the process of forming the spacer material layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] A protective layer is formed on the surface of the sidewall material layer. In the subsequent process of forming a barrier layer, the sidewall material layer is protected from etching damage due to the presence of the protective layer, thereby obtaining a sidewall material layer with a complete morphology. When the material layer to be etched is subsequently etched using the sidewall material layer as a mask, it is beneficial to improve the integrity and accuracy of the pattern transfer, reduce the bridging between adjacent metal layers that are finally formed, and improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 8 is a schematic structural diagram of a method for forming a semiconductor structure in one embodiment;

[0026] Figures 9 to 18 It is a schematic structural diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, the performance of the current semiconductor structure is relatively poor. The reasons for the poor performance of the semiconductor structure are now analyzed in conjunction with specific drawings.

[0028] refer to Figure 1, providing a layer to be etched 100; forming a sacrificial layer 101 on the layer to be etched 100; forming a first patterned layer 102 on the sacrificial layer 101, wherein the first patterned layer 102 exposes a portion of the surface of the sacrificial layer 101; and performing ion implantation on the exposed sacrificial layer.

[0029] refer to Figure 2 , removing the first patterned layer 102; removing the sacrificial layer 101 into which ions have been implanted, and forming a first opening 103 in the remaining sacrificial layer 101, wherein the first opening 103 exposes the surface of the layer to be etched 100.

[0030] refer to Figure 3 A spacer material layer 104 is formed on the bottom and side wall surfaces of the first opening 103 , and the spacer material layer 104 covers the top and side wall surfaces of the sacrificial layer 101 .

[0031] refer to Figure 4 A second patterned layer 105 is formed on the spacer material layer 104 . The second patterned layer 105 has a second patterned opening 106 . The second patterned opening 106 exposes one or more of the first openings 103 .

[0032] refer to Figure 5 , a barrier material layer 107 is formed in the exposed first opening 103 , and the barrier material layer 107 also covers the top surface of the second patterned layer 105 .

[0033] refer to Figure 6 , the barrier material layer 107 is etched for the first time until the top surface of the barrier material layer 107 is flush with the top surface of the spacer material layer 104 .

[0034] refer to Figure 7 , performing a second etching on the remaining barrier material layer 107 until the top surface of the barrier material layer 107 is lower than the top surface of the sacrificial layer 101 , thereby forming a barrier layer 108 ; and removing the second patterned layer 105 .

[0035] refer to Figure 8 , removing the spacer material layer 104 on the bottom surface of the first opening 103 and the top surface of the sacrificial layer 101 ; removing the sacrificial layer 101 , and forming a second opening 109 in the remaining spacer material layer 104 .

[0036] The inventors have discovered that in the process of forming a semiconductor structure using the above-mentioned formation method, the material of the sidewall material layer 104 is generally titanium oxide, and the barrier material layer 107 is generally a low-temperature oxide layer. The etching selectivity of the sidewall material layer 104 and the barrier material layer 107 is not high. When the barrier material layer 107 is etched for the first time and the second time, it is easy to cause etching damage to the sidewall material layer 104 located on the side wall of the first opening 103, resulting in damage to the morphology of part of the sidewall material layer 104. After the sacrificial layer 101 is subsequently removed, when the layer to be etched 100 is etched using the remaining sidewall material layer 104 as a mask, the morphology of part of the sidewall material layer 104 is damaged, resulting in incomplete pattern transfer and low precision. In addition, when a first groove (not shown) corresponding to the first opening 103 and a second groove (not shown) corresponding to the second opening 109 are formed in the layer to be etched 100, the height of the layer to be etched 100 between the first groove and the second groove corresponding to the damaged sidewall material layer 104 is relatively short, resulting in insufficient isolation between the first groove and the second groove. When a metal layer is subsequently formed in the first groove and the second groove, bridging is likely to occur between the metal layers, which is not conducive to the performance of the semiconductor structure.

[0037] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, by forming a protective layer on the surface of the side wall material layer. In the etching process of forming the barrier layer, the etching has little effect on the protective layer, and since the protective layer protects the side wall material layer, the side wall material layer is prevented from being damaged during the etching process, thereby ensuring the morphology of the side wall material layer is intact. When the material layer to be etched is subsequently etched using the side wall material layer as a mask, it is beneficial to improve the integrity and accuracy of the graphic transfer, and reduce the bridging between adjacent metal layers finally formed, thereby improving the performance of the semiconductor structure.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 9 to 18 It is a schematic structural diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention.

[0040] refer to Fig. 9 , providing a substrate 200, on which a material layer 210 to be etched is formed.

[0041] The substrate 200 is used to provide a process platform for subsequent processes. In this embodiment, taking the formed semiconductor structure as a planar transistor as an example, the substrate 200 includes a substrate.

[0042] In this embodiment, the substrate is a silicon substrate; in other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0043] In other embodiments, when the formed semiconductor structure is a fin field effect transistor, the base 200 may correspondingly include a substrate and a fin protruding from the substrate.

[0044] The substrate 200 may further include other structures, such as a gate structure, a doped region, a shallow trench isolation structure, etc.

[0045] The material layer 210 to be etched may be a single material layer or a multi-layer stacked material layer, and may specifically include a dielectric material, a metal material, or a hard mask material.

[0046] In this embodiment, the material layer 210 to be etched is a multi-layer stacked material layer, including: a first material layer (not shown in the figure) located on the surface of the substrate 200 and a second material layer (not shown in the figure) located on the surface of the first material layer.

[0047] The material of the first material layer includes: a kth dielectric material (k is less than or equal to 3.9).

[0048] The second material layer is a hard mask layer, and the second material layer includes a single layer or a stack of multiple layers of a SiC layer, a SiN layer, a BD layer, a tetraethyl orthosilicate TEOS layer, and a TiN layer.

[0049] The function of the second material layer is that, on the one hand, it can serve as an etching stop layer, and on the other hand, the material of the second material layer is a hard mask layer material. In the subsequent etching process, the second material layer suffers less etching loss, and during the graphic transfer process, the stability of the graphic transfer is higher.

[0050] After forming the material layer 210 to be etched on the substrate 200 , a plurality of mutually separated sacrificial layers are formed on the material layer 210 , and a first opening is provided between adjacent sacrificial layers.

[0051] In this embodiment, the steps of forming the sacrificial layer specifically include:

[0052] refer to Fig.10 , forming a sacrificial material layer 220 on the material layer 210 to be etched.

[0053] In this embodiment, the sacrificial material layer 220 is used to subsequently form a separate sacrificial layer.

[0054] Subsequent processes include patterning the sacrificial material layer 220, so that the sacrificial material layer 220 has a higher etching selectivity with the material layer 210 to be etched, thereby achieving selective etching in subsequent processes. In this embodiment, the sacrificial material layer 220 and the material layer 210 to be etched are made of different materials.

[0055] The material of the sacrificial material layer 220 includes amorphous silicon, amorphous carbon or polysilicon. In this embodiment, the material of the sacrificial material layer 220 is amorphous silicon.

[0056] The process of forming the sacrificial material layer 220 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the sacrificial material layer 220 is a chemical vapor deposition process.

[0057] Continue to refer Fig.10 A second patterned layer 230 is formed on the sacrificial material layer 220 , wherein the second patterned layer 230 has a second patterned opening 231 , and the second patterned opening 231 defines the position and size of the first opening to be formed.

[0058] In this embodiment, the second patterned layer 230 is a patterned photoresist layer.

[0059] Continue to refer Fig.10 , using the second patterned layer 230 as a mask, implanting doping ions into a portion of the sacrificial material layer 220 .

[0060] In this embodiment, doping ions are specifically implanted into the sacrificial material layer 220 exposed by the second patterned opening 231 .

[0061] In the present embodiment, doping ions are injected into a portion of the sacrificial material layer 220, which is suitable for increasing the removal selectivity ratio between the sacrificial material layer 220 into which doped ions are not injected and the sacrificial material layer 220 into which doped ions are injected. This is beneficial for increasing the process window of the removal process when the sacrificial material layer 220 into which doped ions are injected is subsequently removed, thereby ensuring the graphic accuracy of the first opening formed subsequently.

[0062] The doping ions include carbon ions, boron ions, arsenic ions, gallium ions or indium ions. In this embodiment, the doping ions are boron ions.

[0063] In this embodiment, the process parameters for implanting doping ions include: implantation energy of 5 to 11 keV, implantation dose of 1E15 to 2E15 atoms / cm 2 .

[0064] refer to Fig.11, remove the sacrificial material layer 220 implanted with doped ions, and form a plurality of mutually discrete sacrificial layers 221 on the material layer 210 to be etched, with a first opening 241 between adjacent sacrificial layers 221, and the bottom of the first opening 241 exposes a portion of the top surface of the material layer 210 to be etched.

[0065] In this embodiment, the process for removing the sacrificial material layer 220 injected with doped ions is a dry etching process; the parameters of the dry etching process include: the etching atmosphere includes a mixed gas of Cl2, HBr, CF4 and O2, the etching power is 500~1000W, the pressure is 5~8 mTorr, the temperature is 30~50℃, and the time is 20~40s.

[0066] In this embodiment, after the sacrificial layer 221 is formed, an ashing process is used to remove the second patterned layer 230 .

[0067] refer to Fig.12 A spacer material layer 250 is formed on the bottom surface and side wall surface of the first opening 241 , and the spacer material layer 250 covers the top surface and side wall surface of the sacrificial layer 221 .

[0068] The process of forming the spacer material layer 250 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the spacer material layer 250 is formed by an atomic layer deposition process.

[0069] The atomic layer deposition process forms the sidewall material layer 250 with good thickness uniformity, so that the thickness of the sidewall material layer 250 located at the bottom surface and sidewall surface of the first opening 241 and the top surface of the sacrificial layer 221 are relatively consistent, which is beneficial for the subsequent etching of the sidewall material layer 250, and the material layer 210 to be etched at the bottom of the first opening 241 and the top surface of the sacrificial layer 221 are exposed simultaneously.

[0070] The material of the spacer material layer 250 includes titanium oxide, titanium nitride, silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, the material of the spacer material layer 250 is titanium oxide.

[0071] Continue to refer Fig.12 A protection layer 260 is formed on the surface of the spacer material layer 250 .

[0072] The process for forming the protective layer 260 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the protective layer 260 is formed by an atomic layer deposition process.

[0073] The atomic layer deposition process forms the protective layer 260 with good thickness uniformity, so that the thickness of the protective layer 260 located at the bottom and sidewall of the first opening 241 and the top of the sacrificial layer 221 is relatively consistent, which is conducive to more uniform coverage of the sidewall material layer 250 and better protection.

[0074] The material of the protective layer 260 is different from the material of the spacer material layer 250, and the material of the protective layer 260 includes silicon nitride or silicon nitride oxide. In this embodiment, the material of the protective layer 260 is silicon nitride.

[0075] The thickness of the protective layer 260 is in the range of If the thickness of the protective layer 260 is greater than It will increase the difficulty of the subsequent process of removing the protective layer 260, resulting in incomplete removal of the protective layer 260, which will affect the morphology of the pattern transfer; if the thickness of the protective layer 260 is less than In the subsequent process, the margin of the protection layer 260 being worn out is too small, resulting in the protection layer 260 being unable to protect the spacer material layer 250 after being worn out, causing etching damage to the spacer material layer 250 .

[0076] In this embodiment, the protective layer 260 completely covers the surface of the spacer material layer 250, and is used to protect the spacer material layer 250 from etching damage in subsequent processes; and the material of the protective layer 260 is different from that of the spacer material layer 250, so that the spacer material layer 250 will not be damaged when the protective layer 260 is subsequently removed. By forming the protective layer 260 on the surface of the spacer material layer 250, the integrity of the spacer material layer 250 in subsequent processes is ensured, which is conducive to improving the integrity and accuracy of pattern transfer, and further conducive to improving the performance of the semiconductor structure.

[0077] After the protective layer 260 is formed, a first patterned layer is formed on the protective layer 260 . The first patterned layer has first patterned openings therein. The first patterned openings expose one or more of the first openings 241 .

[0078] In this embodiment, the steps of forming the first patterned layer specifically include:

[0079] refer to Fig.13 , a first patterned material layer 270 is formed on the protection layer 260 , and the first patterned material layer 270 fills the first opening 241 .

[0080] In this embodiment, the material of the first patterned material layer 270 includes a carbon-containing compound.

[0081] In this embodiment, the material of the first patterned material layer 270 is different from that of the protective layer 260, and the etching selectivity ratio of the first patterned material layer 270 to the protective layer is greater than 10:1. When the first patterned material layer 270 is subsequently etched, etching damage to the protective layer 260 is avoided.

[0082] In this embodiment, the first patterned material layer 270 is formed by spin coating; in other embodiments, the first patterned material layer 270 may also be formed by chemical vapor deposition or atomic layer deposition.

[0083] Continue to refer Fig.13 A mask layer 280 is formed on the first patterned material layer 270 , wherein the mask layer 280 has a mask opening 281 therein, and the mask opening 281 defines the position and size of the first patterned opening to be formed.

[0084] The mask layer 280 includes a single-layer structure or a multi-layer structure. In this embodiment, the mask layer 280 is a double-layer structure, including a bottom anti-reflection layer 282 located on the surface of the first patterned material layer 270 , and a photoresist layer 283 located on the surface of the bottom anti-reflection layer 282 .

[0085] refer to Fig.14 , using the mask layer 280 as a mask, etching the first patterned material layer 270 until one or more first openings 241 are exposed, thereby forming a first patterned layer 271 , wherein the first patterned layer 271 has a first patterned opening 272 .

[0086] The position and number of the first openings 241 exposed by the first patterned opening 272 can be selected according to actual process requirements. In this embodiment, the exposure of one first opening 241 is taken as an example for description.

[0087] In this embodiment, in order to expand the process window, the first patterned opening 272 not only exposes the first opening 241 , but also exposes a portion of the surface of the protection layer 260 on both sides of the exposed first opening 241 .

[0088] In this embodiment, the process of etching the first patterned material layer 270 is dry etching.

[0089] In this embodiment, the dry etching process has a higher etching selectivity for the protective layer 260 and the first patterned material layer 270, that is, the etching rate of the dry etching process for the protective layer 260 is much lower than the etching rate of the first patterned material layer 270, so that when etching the first patterned material layer 270, the etching damage to the protective layer 260 is relatively small, thereby avoiding etching damage to the side wall material layer 250 covered by the protective layer 260.

[0090] refer to Fig.15 After forming the first patterned layer 271, the mask layer 280 is removed.

[0091] In this embodiment, an ashing process is used to remove the mask layer 280 .

[0092] Continue to refer Fig.15 , a barrier material layer 290 is formed in the exposed first opening 241 , and the barrier material layer 290 also covers the top surface of the first patterned layer 271 .

[0093] In this embodiment, the barrier material layer 290 is used to subsequently form a barrier layer.

[0094] In this embodiment, the barrier material layer 290 is a low temperature oxide layer, and the low temperature oxide includes silicon dioxide.

[0095] In other embodiments, the barrier material layer 290 may also be an oxynitride layer, and the oxynitride includes silicon oxynitride.

[0096] In this embodiment, the process of forming the barrier material layer 290 includes performing plasma enhanced chemical vapor deposition at a temperature below 400° C.

[0097] refer to Fig.16 , etching the barrier material layer 290 until the top surface of the barrier material layer 290 is lower than the top surface of the sacrificial layer 221 , thereby forming a barrier layer 291 .

[0098] The etching selectivity ratio of the blocking material layer 290 to the protection layer 260 is greater than 6:1. When the blocking material layer 290 is subsequently etched, the etching damage to the protection layer 260 is reduced, thereby avoiding etching damage to the sidewall material layer 250 .

[0099] It should be noted that, since the etching selectivity ratio of the blocking material layer 290 and the protective layer 260 needs to satisfy a condition greater than 6:1, in other embodiments, when the material of the protective layer 260 is silicon oxynitride, the blocking material layer 290 cannot be silicon oxynitride.

[0100] In this embodiment, the step of etching the blocking material layer 290 includes: etching the blocking material layer 290 for the first time until the top surface of the blocking material layer 290 is flush with the top surface of the protective layer 260; and then etching the blocking material layer 290 for the second time until the top surface of the blocking material layer 290 is lower than the top surface of the sacrificial layer 221, thereby forming a blocking layer 291.

[0101] In this embodiment, the first etching is used to open an etching process window to facilitate the subsequent second etching of the barrier material layer 290 in the first opening 241 .

[0102] In this embodiment, the first etching process and the second etching process are both dry etching processes, and the parameters of the first etching process include: the etching atmosphere includes a mixed gas of C4F6 and O2, the power is 200 to 1000 watts, the pressure is 5 to 20 mTorr, the temperature is 30 to 50 degrees Celsius, and the time is 5 to 20 seconds; the parameters of the second etching process include: the etching atmosphere includes a mixed gas of CF4 and CHF3, the power is 900 to 1500 watts, the pressure is 5 to 20 mTorr, the temperature is 30 to 50 degrees Celsius, and the time is 5 to 10 seconds.

[0103] In this embodiment, the function of the barrier layer 291 is that when the material layer to be etched is subsequently etched along the first opening 241 and the second opening as a mask to form the first groove and the second groove, since the barrier layer 291 is formed in part of the first opening 241, a barrier will be formed in the first groove corresponding to the first opening 241 having the barrier layer 291, and the barrier is used to cut off the metal layer formed in the first groove.

[0104] In this embodiment, when the blocking material layer 290 is etched, the first patterned layer 271 is also etched away simultaneously.

[0105] refer to Fig.17 , remove the protective layer 260.

[0106] In this embodiment, since the barrier layer 291 is formed in one of the first openings 241 and the process window of the sidewalls of the barrier layer 291 is small, part of the protective layer 260 on the bottom and sidewalls of the barrier layer 291 is retained during the removal of the protective layer 260 .

[0107] The process of removing the protective layer 260 includes a dry etching process and a wet etching process, or a combination of the two. In this embodiment, the dry etching process is used to remove the protective layer 260.

[0108] In this embodiment, the dry etching process has a higher etching selectivity ratio for the protective layer 260 and the side wall material layer 250, that is, the etching rate of the dry etching process for the side wall material layer 250 is much lower than the etching rate for the protective layer 260. Therefore, while removing the protective layer 260, the side wall material layer 250 is prevented from being damaged by etching, thereby ensuring the integrity of the pattern of the side wall material layer 250, which is beneficial to improving the stability of pattern transfer.

[0109] Continue to refer Fig.17, remove the spacer material layer 250 on the bottom surface of the first opening 241 and the top surface of the sacrificial layer 221 .

[0110] The process of removing the spacer material layer 250 on the bottom surface of the first opening 241 and the top surface of the sacrificial layer 221 includes a dry etching process and a wet etching process or a combination of the two.

[0111] In this embodiment, since the barrier layer 291 is formed in one of the first openings 241 , a portion of the spacer material layer 250 covered by the barrier layer 291 is retained during the process of removing the spacer material layer 250 on the bottom surface of the first opening 241 .

[0112] refer to Fig.18 , remove the sacrificial layer 221 and form a second opening 242 in the remaining spacer material layer 250 .

[0113] In this embodiment, a wet etching process is used to remove the sacrificial layer 221 , and parameters of the wet etching process include: the etching solution includes ammonia water.

[0114] The wet etching process has a high etching selectivity ratio for the side wall material layer 250 and the sacrificial layer 221, that is, the etching rate of the wet etching process for the side wall material layer 250 is much lower than the etching rate of the sacrificial layer 221. Therefore, the etching damage to the side wall material layer 250 is relatively small, ensuring that the sacrificial layer 221 is completely removed while the remaining side wall material layer 250 pattern remains intact, which is beneficial to improving the stability of pattern transfer.

[0115] In the present embodiment, since a protective layer 260 is formed on the side wall material layer 250, and the protective layer 260 has a high etching selectivity with the barrier layer 291 to be subsequently etched, the etching damage to the protective layer 260 is reduced during the subsequent etching to form the barrier layer 291, thereby preventing the side wall material layer 250 covered by the protective layer 260 from being etched damage, which is beneficial to ensuring the integrity of the morphology of the side wall material layer 250. When the material layer 210 to be etched is subsequently etched using the side wall material layer 250 as a mask, it is beneficial to improving the stability and accuracy of graphic transfer.

[0116] In this embodiment, after removing the sacrificial layer 221, the remaining side wall material layer 250 is used as a mask to remove the material layer 210 to be etched exposed by the first opening 241 and the second opening 242, and a first groove (not shown) corresponding to the first opening 241 and a second groove (not shown) corresponding to the second opening 242 are formed in the material layer 210 to be etched.

[0117] In this embodiment, the method further includes: forming a metal layer in the first trench and the second trench.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a material layer to be etched is formed; Forming a plurality of mutually separate sacrificial layers on the material layer to be etched, with a first opening between adjacent sacrificial layers; Forming a spacer material layer on the bottom surface and side wall surface of the first opening, wherein the spacer material layer covers the side wall and top surface of the sacrificial layer; forming a protective layer on the surface of the sidewall material layer, wherein the thickness of the protective layer is greater than or equal to 10 Å; forming a first patterned layer on the protective layer, wherein the first patterned layer has first patterned openings, and the first patterned openings expose one or more of the first openings; forming a barrier layer in the exposed first opening, wherein a top surface of the barrier layer is lower than a top surface of the sacrificial layer; removing the protective layer; Removing the spacer material layer on the bottom surface of the first opening and the top surface of the sacrificial layer; The sacrificial layer is removed, and a second opening is formed between the remaining spacer material layers.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protection layer includes silicon nitride or silicon nitride oxide.

3. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the protection layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

4. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the protective layer ranges from 10 to 30 Å.

5. The method for forming a semiconductor structure according to claim 1, wherein: The barrier layer includes a low temperature oxide layer or an oxynitride layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a barrier layer in the exposed first opening includes: forming a barrier material layer in the exposed first opening, wherein the barrier material layer also covers the top surface of the first patterned layer; etching the barrier material layer until the top surface of the barrier material layer is lower than the top surface of the sacrificial layer to form a barrier layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The etching selection ratio of the blocking material layer to the protective layer is greater than 6:

1.

8. The method for forming a semiconductor structure according to claim 6, wherein: The step of etching the barrier material layer includes: etching the barrier material layer for the first time until the top surface of the barrier material layer is flush with the top surface of the protective layer; etching the barrier material layer for the second time until the top surface of the barrier material layer is lower than the top surface of the sacrificial layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first etching includes a dry etching process, and the process parameters of the first etching include: the etching atmosphere includes a mixed gas of C4F6 and O2, the power is 200~1000 watts, the pressure is 5~20 mTorr, the temperature is 30~50 degrees Celsius, and the time is 5~20 seconds.

10. The method for forming a semiconductor structure according to claim 8, wherein: The second etching includes a dry etching process, and the process parameters of the second etching include: the etching atmosphere includes a mixed gas of CF4 and CHF3, the power is 900~1500 watts, the pressure is 5~20 mTorr, the temperature is 30~50 degrees Celsius, and the time is 5~10 seconds.

11. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a plurality of mutually discrete sacrificial layers on the material layer to be etched includes: forming a sacrificial material layer on the material layer to be etched; forming a second patterned layer on the sacrificial material layer, wherein the second patterned layer has a second patterned opening, and the second patterned opening corresponds to the position and size of the first opening; using the second patterned layer as a mask, injecting dopant ions into part of the sacrificial material layer; removing the sacrificial material layer injected with dopant ions to form mutually discrete sacrificial layers; and removing the second patterned layer.

12. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the first patterned layer include: forming a first patterned material layer on the protective layer, and the first patterned material layer fills the first opening; forming a mask layer on the first patterned material layer, the mask layer having a mask opening, and the mask opening corresponds to the position and size of the first patterned opening; using the mask layer as a mask, etching the first patterned material layer until one or more of the first openings are exposed to form a first patterned layer; and removing the mask layer.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first patterned layer includes a carbon-containing compound.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer includes amorphous silicon, amorphous carbon or polysilicon.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material layer to be etched includes a single material layer or a multi-layer stacked material layer.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the spacer material layer includes titanium oxide, titanium nitride, silicon nitride, silicon oxide or silicon oxynitride.

17. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the spacer material layer includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

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