Method for manufacturing a power semiconductor device with split gate structure

Abstract

A method of fabricating a power semiconductor device having a split gate structure provides forming a single or multi-layer epitaxial layer on a substrate; forming a trench through the epitaxial layer extending from a top surface of the epitaxial layer in a direction transverse to a vertical direction of the top surface; filling the trench with a dielectric region and a conductive shield plate element, the shield plate element including an upper portion protruding from the underlying dielectric region and a bottom portion extending inwardly vertically to the dielectric region; oxidizing the upper portion of the shield plate element to form an isolation region in the trench at the top surface of the epitaxial layer, the bottom portion of the shield plate element defining a bottom of the split gate structure; forming a gate oxide region on the dielectric region at an upper portion of the same trench on an inner surface of the trench; forming a top gate portion of the split gate structure transverse to the isolation region filling the trench at the top surface of the epitaxial layer. The method provides forming a sacrificial oxide region on the upper portion of the shield plate element prior to forming the gate oxide region and subsequent etching of the sacrificial oxide region.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for manufacturing a power semiconductor device, in particular, a field plate trench power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device. BACKGROUND

[0002] Field plate or shield gate (or split gate) trench (or vertical) power MOSFET devices are known, in which the gate conductive material, typically polysilicon, in the gate trench is split into multiple portions: one or more top portions formed at the channel region and acting as control gate; and one or more bottom portions formed at the drift region and capacitively shielding the top gate portions from the drain region.

[0003] The electrical characteristics of split gate trench power MOSFET devices, such as breakdown voltage BV DS , on-state resistance R ON , maximum drain current I DMAX and gate charge Q gd , Q gs are strongly related to the split gate biasing conditions, which determine the modulation of the electric potential in the drift region; in general, a proper biasing of the top and bottom portions of the split gate allows to optimize the switching performance of the power MOSFET device.

[0004] Figure 1 A known and exemplary split gate trench power MOSFET device 1 is shown, as disclosed for example in Kyoung II Na et al. in “Electrical Characteristics of Triple-Gate RSO Power MOSFET (TGRMOS) with Various Gate Configurations and Bias Conditions”, ETRI Journal, Vol. 35, No. 3, June 2013; in this case, the gate of the power MOSFET device 1 is split into three portions, two separate top portions and one bottom portion.

[0005] The power MOSFET device 1 comprises: a substrate 2 of heavily doped semiconductor material (for example, N + type); and an epitaxial layer 3 formed on the substrate 2, made of semiconductor material having the same type of conductivity as the substrate 2 and having a lighter doping (in this example, N - type).

[0006] Within a surface portion of the epitaxial layer 3, cells 5 of the power MOSFET device 1 are formed, each cell 5 comprising a body well 6 having a conductivity opposite to that of the epitaxial layer 3 (P-type in this example) and a source region 8 within the body well 6 having the same type of conductivity as the substrate 2 (N-type in this example). + The portion of the epitaxial layer 3 below the body well 6 represents the drift region of the power MOSFET device 1.

[0007] The power MOSFET device 1 further comprises a split gate structure 10 formed in a deep trench 12 extending vertically through the epitaxial layer 3, the deep trench 12 being in a portion of the same epitaxial layer 3 laterally arranged between the source region 8 and the body well 6 belonging to adjacent cells 5.

[0008] The split gate structure 10 comprises a bottom gate portion 13 acting as a shield or field plate, arranged in a lower portion of the trench 12 and extending centrally of the trench 12 and at a lower level than the body well 6, and, in this example, two separate top gate portions 14a, 14b arranged in a top portion of the trench 12 laterally to the respective source region 8 at the same level as the body well 6.

[0009] The bottom gate portion 12 is separated from the trench inner surface via a dielectric stack 15 formed by silicon oxide (SiO2), silicon nitride (SiN x ) and tetraethyl orthosilicate (TEOS) deposition; the top gate portions 14a, 14b are separated from each other and, in addition, from the trench inner surface via a dielectric region 15' made of silicon oxide in particular.

[0010] The power MOSFET device 1 further comprises a body / source metallization 16 formed on the epitaxial layer 3, separated from the top gate portions 14a, 14b by a top portion of the dielectric region 15' and contacting the source regions 8 and, in addition, contacting the body region 6 via a body contact 17, i.e. a highly doped region (P + -type) of the body well 6 arranged at the surface of the epitaxial layer 3; and a drain electrode 18 formed at the backside of the substrate 2, contacting the same substrate 2. A gate electrode arrangement, not shown here, is provided to contact the split gate structure 10 (top gate portions 14a, 14b and bottom gate portion 13 of the split gate structure 10).

[0011] The substrate 2 acts as a drain of the power MOSFET device 1 and the epitaxial layer 3 represents a surface extension of the substrate 2. The channel of each cell 5 is constituted by a portion of the respective body well 6 arranged laterally to the top gate portions 14a, 14b and is delimited on the one hand by a junction between the source region 8 and the body well 6 and on the other hand by a junction between the body well 6 and the drift region.

[0012] The gate electrode arrangement is capacitively coupled to the channel to modulate its conductivity type. In particular, by applying an appropriate voltage to the gate electrode arrangement, a reversal of the conductivity of the channel can be induced, thereby creating a conductive path for majority charge carriers between the source region 8 and the substrate 2 via the channel and the drift region. The resulting current is affected by the resistance of the channel and the drift region.

[0013] As previously discussed, the biasing of the split-gate structure 10 determines the modulation of the potential in the drift region, allowing optimization of the switching performance of the power device.

[0014] Now refer to Figures 2A-2F A conventional manufacturing process of a power MOSFET device 1 is discussed, with particular emphasis on the formation of the split gate structure 10 .

[0015] like Figure 2A As shown in FIG, the top surface of the epitaxial layer 3, which is designated here by 3a, is etched in order to form a deep trench 12, which extends vertically to the same top surface 3a.

[0016] Then, if Figure 2B As shown in FIG, silicon oxide (SiO 2 ), silicon nitride (SiN 2 ) and silicon nitride (SiO 2 ) are deposited above the top surface 3 a of the epitaxial layer 3 and inside the trench 12. x ) and tetraethyl orthosilicate (TEOS) dielectric stack 15 to cover the inner wall of the trench 12.

[0017] Then, if Figure 2C As shown in , a first conductive layer 20 of conductive material, in particular polysilicon, is formed over the epitaxial layer 3 and inside the trenches 12 , thereby completely filling the same trenches 12 (inwardly with respect to the dielectric stack 15 ).

[0018] Afterwards, if Figure 2D As shown in , the first conductive layer 20 and the dielectric stack 15 are etched back. Specifically, the first conductive layer 20 is etched back to remove it from the top surface 3a of the epitaxial layer 3, and a trench portion 20' thereof is left in the trench 12, the top end of which is at the level of the top surface 3a of the epitaxial layer 3 (the so-called "mesa level"); and the dielectric stack 15 is etched back to the channel length, that is, the depth below the top surface 3a in the trench 12, which corresponds to the desired length of the channel of the power MOSFET device 1.

[0019] Then, see Figure 2E, the process comprises a specific step of thermal oxidation (in particular via steam oxidation) of the upper part (the sidewalls of which are not covered by the dielectric stack 14) of the trench portion 20', which is completely oxidized so as to form the separation region 19 (used, in a subsequent step of the manufacturing process, for the separation of the top gate portions 14a, 14b of the split gate structure 10). The above-mentioned oxidation also defines the bottom gate portion 13 of the same split gate structure 10 (which corresponds to the remaining part of the trench portion 20') and forms the gate oxide region 15' of the power MOSFET device 1 at the sidewalls of the upper part of the trench 12.

[0020] Subsequently, as shown in Figure 2F , a second conductive layer 22 of electrically conductive material, in particular polysilicon, is deposited over the top surface 3a of the epitaxial layer 3, so as to define, within the upper part of the trench 12, the top gate portions 14a, 14b of the split gate structure 10, which are separated by the above-discussed separation region 19.

[0021] In a manner not shown in detail here, then, the manufacturing process continues with standard steps of implantation and metallization, so as to form (see also the previous Figure 1 ) the body region 6, the source region 8, the body contact 16 and the drain, source and gate metallizations (in particular the body / source metallization 16 and the drain electrode 18).

[0022] The Applicant has realized that the known manufacturing process discussed above, although generally satisfactory, presents some problems.

[0023] In particular, as previously discussed (see Figure 2E ), the gate oxide is formed simultaneously with the step of thermal oxidation of the upper part of the trench portion 20' of the first conductive layer 20. Since the characteristics of the gate oxide (in particular its thickness) determine the desired performance of the power MOSFET device 1, the height and width of the trench portion 20', which depend on the thickness of the gate oxide (based on the different oxidation rates of silicon and polysilicon), cannot exceed certain values; otherwise, the same trench portion 20' would not be completely oxidized and the desired separation between the top gate portions 14a, 14b of the split gate structure 10 cannot be guaranteed.

[0024] It follows that the characteristics of the gate oxide and of the above-mentioned trench portion 20' cannot be controlled independently, and therefore the characteristics of the bottom gate portion 13 of the split gate structure 10 cannot be controlled independently either.

[0025] Furthermore, during the etch-back of the first conductive layer 20 (see Figure 2D), it can prove difficult to ensure the desired height of the remaining trench portions 20', especially if CMP (Chemical Mechanical Polishing) is implemented. If the resulting height of the trench portions 20' is lower than the top surface 3a of the epitaxial layer 3 (i.e. the mesa level), it can not be possible to guarantee the separation between the top gate portions 14 of the split gate structure 10. Conversely, if the resulting height of the same trench portions 20' is higher than the top surface 3a of the epitaxial layer 3, undesired portions of the first conductive layer 20 can remain on the same top surface 3a of the epitaxial layer 3, again in contrast to what is desired. SUMMARY

[0026] It is therefore an object of the present application to provide a manufacturing method capable of solving the above-discussed problems that plague known manufacturing processes.

[0027] Therefore, according to the present application, there is provided a method for manufacturing a power semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0028] For a better understanding of the present application, a preferred embodiment thereof will now be described, by way of non-limiting example only, and with reference to the accompanying drawings, in which:

[0029] Figure 1 is a cross-sectional view of a known split-gate trench power MOSFET device;

[0030] Figures 2A-2F is a cross-sectional view of a known power MOSFET device in a subsequent step of the corresponding manufacturing process; and

[0031] Figures 3A-3K is a cross-sectional view of a power MOSFET device according to an embodiment of the present solution in a subsequent step of the manufacturing process. DETAILED DESCRIPTION

[0032] Reference will now be made to Figure 3A a method for manufacturing a power semiconductor device, in particular a power MOSFET device, for simplicity reference will be made to an exemplary unit cell of the device (however, it is apparent that what is shown and discussed applies to all cells of the power MOSFET device).

[0033] As Figure 3A shown in + , an epitaxial layer 23 has been formed on a substrate 22 of heavily doped semiconductor material (in the example, N - type) ; the epitaxial layer 23 is made of semiconductor material having the same type of conductivity as the substrate 22 and having a lighter doping (in the example, N

[0034] A masking oxide layer 24 is grown by wet oxidation on the top surface 23a of the epitaxial layer 23, followed by LPCVD deposition of a nitride layer 25, covering the same masking oxide layer 24.

[0035] Next, a deep trench 26 having a desired depth along the vertical direction (transversal to the top surface 23a of the epitaxial layer 23) is formed by silicon etching starting from the same top surface 23a.

[0036] Then, as shown in Figure 3B , a thick oxide layer 27 is thermally grown on the inner surface of the deep trench 26, followed by deposition of a highly doped N-type shield (or field plate) polysilicon layer 28 over the top surface 23a of the epitaxial layer 23. In particular, the shield polysilicon layer 28 completely fills the deep trench 26, being arranged inwardly with respect to the thick oxide layer 27. Moreover, the thick oxide layer can be a thermal oxide layer, a CVD oxide layer (CVD: Chemical Vapor Deposition) or a mixed oxide layer composed of both.

[0037] As shown in Figure 3C , the surface of the shield polysilicon layer 28 is planarized by a CMP process and etched back to a desired depth, so that a shield plate (or field plate) element 28' vertically extends inside the deep trench 26 in the center of the deep trench.

[0038] In particular, the level of the etched-back shield polysilicon layer 28 (i.e. the top level of the upper portion of the shield plate element 28') can be controlled to be at the same level as the top surface 23a of the epitaxial layer 23 (as shown in Figure 3C ), or, in a manner not shown here, at a level lower than the top surface 23a of the epitaxial layer 23; in any case, the etched-back shield polysilicon layer 28 is etched back to a level not higher than the top surface 23a.

[0039] As will be discussed below, depending on the level of the etched-back shield polysilicon layer 28, either a single top gate portion or two separate top gate portions can be defined in the split gate structure of the power MOSFET device.

[0040] Subsequently, as shown in Figure 3D , the masking oxide layer 24 and the nitride layer 25 are removed by a wet etching process.

[0041] Next, the thick oxide layer 27 in the deep trench 26 is wet etched to a desired depth lower than the level of the top surface 23a of the epitaxial layer 23, to allow the formation of a top gate portion of the split gate structure of the power MOSFET device in a subsequent process step (as will be discussed below); the desired depth will correspond to the channel length of the power semiconductor device.

[0042] According to a particular aspect of the present solution, asFigure 3E The upper portion of the shield plate element 28' (projecting from the underlying thick oxide layer 27) is then partially oxidized, in the example, using a wet oxidation process to form a sacrificial oxide ("SacOx") region 29 covering the remaining portion of the same upper portion of the shield plate element 28'; however, it is noted that the sacrificial oxidation can cause the complete oxidation of the upper portion of the shield plate element 28'.

[0043] The sacrificial oxide region 29 also grows on the inner walls of the deep trench 26, at the top of the same deep trench 26 (it is noted that the sacrificial oxide grows faster in the polysilicon of the upper portion of the shield plate element 28' than in the silicon of the epitaxial layer 23).

[0044] As Figure 3F The grown sacrificial oxide region 29 is then wet-etched to be completely removed from the inner walls of the deep trench 26, and in the example shown, from the remaining portion of the upper portion of the shield plate element 28'.

[0045] It is noted that this step reduces the thickness (or width) of the upper portion of the shield plate element 28' (in the direction parallel to the top surface 23a) before the subsequent gate oxidation step, ensuring that the complete oxidation of the same upper portion occurs later on (in other words, this step ensures that a critical lower limit thickness of the upper portion of the shield plate element 28' is reached in any case, allowing it to be completely oxidized in the following process steps). Next, as Figure 3G A gate insulating film of a desired (or target) thickness is formed using a dry oxidation process, as shown in

[0046] It is noted that, as previously discussed, the upper portion of the shield plate element 28' can have already been completely oxidized during the sacrificial oxidation process; in this case, the dry oxidation process contributes to the definition of the dielectric separation region 31.

[0047] Advantageously, the step of growing and subsequent removal of the sacrificial oxide ensures the complete oxidation of the upper portion of the shield plate element 28' independently of the thickness of the gate film (i.e., the thickness of the gate oxide region 30 can be controlled in a separate and independent manner).

[0048] Then, gate N-type polysilicon is deposited in the free upper part of the deep trench 26. An N-type doped gate polysilicon layer is deposited over the epitaxial layer 23, in particular, filling the upper part of the deep trench 26. Then, the gate polysilicon layer is planarized by a CMP process and etched back to the desired depth, as shown in Figure 3H in particular, etched back until it is recessed to a level slightly below the top surface 23a of the epitaxial layer 23, so as to form a top gate portion 34 of the split gate structure, here denoted with 36 (also including the shield plate 32 discussed above). In particular, the top gate portion 34 is arranged laterally to the dielectric separation region 31, in this case, the top gate portion 34 is dielectrically separated by the same dielectric separation region 31 and the top gate portion 34 is arranged at the side of the gate oxide region 30.

[0049] Then, oxidation of the top gate portion 34 of the split gate structure 36 is performed, as shown in Figure 3I a top oxide region 38 is formed on the same top gate portion 34.

[0050] Then, the process continues with standard steps for the fabrication of a power MOSFET device, in particular, as shown in Figure 3J the steps of source and channel implantation are continued.

[0051] In particular, a body region 40 is formed in the epitaxial layer 23 laterally to the top gate portion 34 of the split gate structure 36, whereby the same body region 40 is separated by the gate oxide region 30. In the body region 40, at the top surface 23a of the epitaxial layer 23, a source region 42 is formed having an N + type doping.

[0052] Subsequently, as shown in Figure 3K a dielectric layer 44 is deposited over the top surface 23a of the epitaxial layer 23. Then, the same dielectric layer 44 and an underlying portion of the source region 42 are etched to form a contact opening 45, and then a body contact 46 is formed in the body region 40 through the contact opening 45.

[0053] Subsequently, a drain, source, and gate metallization is formed in a manner known per se, which is not shown in detail here.

[0054] The advantages of the proposed solution are clear from the foregoing description.

[0055] In particular, it is again emphasized that the height and width of the upper part of the shield plate element 28' and the thickness of the sacrificial oxide region 29 (see Figure 3D and 3E) to realize two connected top gate portions 34 (i.e. where the upper portion of the shield plate element 28' and the subsequently formed dielectric separation region 31 are manufactured below the top surface 23a of the epitaxial layer 23, so-called mesa level) or two separated top gate portions 34 (i.e. where the upper portion of the shield plate element 28' and the subsequently formed dielectric separation region 31 are manufactured at the same level of the top surface 23a of the epitaxial layer 23).

[0056] Furthermore, regardless of the thickness of the upper portion of the shield plate element 28', the thickness of the gate oxide (i.e. the thickness of the gate oxide region 30) can be controlled to a target thickness; this approach provides additional degrees of freedom for the design of split-gate trench power MOSFET devices according to the requirements of the specific application.

[0057] Additionally, in the manufacturing approach discussed, contrary to the prior art solutions, the step of etching back of the shield polysilicon layer 28 (to define the top level of the upper portion of the shield plate element 28') does not represent a critical step, since the separation of the top gate portions 34 of the split-gate structure 36 is ensured subsequently through subsequent steps of the manufacturing process (in particular, through the full oxidation of the upper portion of the shield plate element 28' after the deposition and removal of the sacrificial oxide thereof). Therefore, the etching back of the shield polysilicon layer 28 can be performed at a level not higher than the level of the top surface 23a of the epitaxial layer 23, so that it is ensured that, subsequently, no portion of the gate polysilicon layer remains on the same top surface 23a.

[0058] In general, the proposed solution allows to realize low gate-source charge Qgs field plate trench power semiconductor devices.

[0059] Finally, it is clear that modifications and / or changes can be made to what has been described and shown herein, without thereby departing from the scope of the application as defined by the annexed claims.

[0060] In particular, it is again emphasized that, using the same manufacturing approach, a single top gate portion (instead of two separated top gate portions as shown in the embodiments) can be realized, simply by adjusting the level of the upper portion of the shield plate element 28' and of the subsequently formed dielectric separation region 31 below the top surface 23a of the epitaxial layer 23.

[0061] Furthermore, it is emphasized that the disclosed manufacturing process can be used for manufacturing other semiconductor power devices, for example IGBT devices, where the emitter-gate charge can be reduced.

Claims

1. A method for manufacturing a power semiconductor device having a split gate structure (36), the method comprising: forming a single or multiple epitaxial layers (23) on a substrate (22); forming a trench (26) passing through the epitaxial layer (23), wherein the trench (26) extends from a top surface (23a) of the epitaxial layer (23) in a vertical direction transverse to the top surface (23a); filling the trench (26) with a dielectric region (27) and a conductive shielding plate element (28'), the shielding plate element (28') including an upper portion protruding from the underlying dielectric region (27) and a bottom portion extending vertically inwardly relative to the dielectric region (27); Partially oxidizing the upper portion of the shield plate element (28') to form a sacrificial oxide region (29), and etching the sacrificial oxide region (29) to reduce the thickness of the upper portion of the shield plate element (28') so that the upper portion of the shield plate element (28') is fully oxidized during a subsequent oxidation; oxidizing the upper portion of the shielding plate element (28') to form a separation region (31) at the top surface (23a) of the epitaxial layer (23), the bottom portion of the shielding plate element (28') defining a bottom of the split gate structure (36) of the power semiconductor device; forming a gate oxide region (30) on an inner surface of the trench (26), at an upper portion of the trench (26), above the dielectric region (27), forming a top gate portion (34) of the split gate structure (36), the top gate portion (34) filling the trench (26) at the top surface (23a) of the epitaxial layer (23), the top gate portion (34) being lateral to the separation region (31), Characterized in that reducing the thickness of the upper portion of the shielding plate element (28') includes reaching a critical lower thickness of the upper portion of the shielding plate element (28'), thereby allowing the upper portion of the shielding plate element (28') to be fully oxidized during a subsequent oxidation.

2. The method according to claim 1, wherein Etching the sacrificial oxide region (29) includes removing the grown sacrificial oxide region (29) from the upper portion of the shield plate element (28') such that a remaining portion of the upper portion of the shield plate element (28') protrudes from the underlying dielectric region (27).

3. The method according to claim 1 or 2, wherein: Forming the gate oxide region (30) occurs simultaneously with fully oxidizing the upper portion of the shield plate element (28') to form the separation region (31).

4. The method according to claim 1 or 2, wherein: A wet oxidation process is used to form the sacrificial oxide region (29); a wet etching process is used to subsequently etch the sacrificial oxide region (29); and a dry oxidation process is used to form the gate oxide region (30) and oxidize the upper portion of the shield plate element (28').

5. The method according to claim 1 or 2, wherein: Filling the trench (26) with a dielectric region (27) and a conductive shield plate element (28') comprises: growing an oxide layer on the inner surface of the trench (26); Depositing a shielding polysilicon layer (28) above the top surface (23a) of the epitaxial layer (23), wherein the shielding polysilicon layer (28) fills the trench (26), and the shielding polysilicon layer (28) is inside the oxide layer; Etching back the shield polysilicon layer (28) to leave the shield plate element (28') extending vertically within the trench (26); and The oxide layer in the trench (26) is etched back to a desired depth below the level of the top surface (23a) of the epitaxial layer (23), thereby leaving an upper portion of the trench (26) blank, the desired depth corresponding to the channel length of the power semiconductor device.

6. The method according to claim 5, wherein: The level of the etched-back shield polysilicon layer (28) is controlled to be no higher than the level of the top surface (23a) of the epitaxial layer (23).

7. The method according to claim 6, wherein: The level of the etched-back shield polysilicon layer (28) is controlled to be at the same level as the top surface (23a) of the epitaxial layer (23).

8. The method according to claim 6, wherein: The level of the etched-back shield polysilicon layer (28) is controlled to be at a level lower than the top surface (23a) of the epitaxial layer (23).

9. The method of any one of the preceding claims, wherein forming the top gate portion (34) of the split gate structure (36) comprises: Depositing a gate polysilicon layer (33) above the top surface (23a) of the epitaxial layer (23), wherein the gate polysilicon layer (33) fills an upper portion of the trench (26), and the gate polysilicon layer (33) is above the dielectric region (27); The gate polysilicon layer (33) is etched back until the gate polysilicon layer (33) is recessed to a level below the top surface (23a) of the epitaxial layer (23) to form the top gate portion (34) of the split gate structure (36) arranged transversely to the separation region (31).

10. The method according to claim 9, wherein: The top gate portion (34) of the split gate structure (36) is dielectrically separated by the separation region (31).

11. A method according to any one of the preceding claims, wherein The power semiconductor device is a field plate trench power MOSFET device.

12. The method according to claim 11, wherein The substrate (22) is made of a heavily doped semiconductor material, and the epitaxial layer (23) has the same first conductivity type as the substrate (22) and has a lighter doping; the method further comprises: forming a body region (40) in the epitaxial layer (23), the body region having a second conductivity type opposite to the first conductivity type, lateral to the top gate portion (34) of the split gate structure (36), and separated from the top gate portion (34) by a gate oxide region (30); A source region (42) having the first conductivity type is formed in the body region (40) at the top surface (23a) of the epitaxial layer (23).

13. The method according to claim 12, further comprising: depositing a dielectric layer (44) over the top surface (23a) of the epitaxial layer (23); as well as A lower portion of the source region (42) and the dielectric layer (44) are etched to form a contact opening (45), and then a body contact (46) is formed in the body region (40) through the contact opening.

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