Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The semiconductor structure includes: a dielectric wall penetrating a first channel layer and a first gate at the junction of a first region and a second region; a blocking wall located at one lateral end of the top of the dielectric wall, with the projection of the blocking wall on the substrate falling within the projection of the dielectric wall on the substrate; and a second gate located on the side of the blocking wall between the first gate and the dielectric wall, exposing the top of the blocking wall. This allows the blocking wall to electrically isolate the second gate while occupying a smaller planar area of ​​the semiconductor structure, resulting in higher integration density. Furthermore, because the blocking wall is located at the top of the dielectric wall, the distance between the blocking wall and the channel is greater during semiconductor structure operation, reducing the likelihood of the blocking wall generating stress on the channel. This makes it easier to meet process requirements for the carrier migration rate in the channel, thus improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. In order to adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects.

[0004] With the development of semiconductor technology, in order to improve the integration of semiconductor structures and reduce the spacing between transistors, Forksheet transistors were proposed. They are the choice after FinFET and fully enclosed transistors, and are separated by dielectric walls due to their complex double-sided fin structure.

[0005] When working with highly integrated Forksheet structures, reducing the impact of the back-end structure on the carrier migration rate in the channel, so that the carrier migration rate meets the working requirements, is crucial to improving the performance of the Forksheet. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which, while satisfying the high integration of the semiconductor structure, ensures that the carrier migration rate of the channel meets the process requirements and optimizes the electrical performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a first region and a second region; one or more first channel layers, spaced apart and suspended on the substrate along the normal direction of the substrate surface; a first gate located on the substrate, and the first gate completely surrounding the first channel layers; a dielectric wall penetrating the first channel layer and the first gate at the junction of the first region and the second region, with its extension direction parallel to the substrate surface and perpendicular to the dielectric wall being laterally oriented; a blocking wall located at one laterally oriented end of the top of the dielectric wall, the projection of the blocking wall on the substrate being located within the projection of the dielectric wall on the substrate; and a second gate located on the side of the blocking wall, between the first gate and the dielectric wall, and exposing the top of the blocking wall.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including adjacent first and second regions, the substrate including: a substrate; one or more first channel layers, spaced apart and suspended on the substrate along the normal direction of the substrate surface; a first gate structure completely surrounding the first channel layers; an initial dielectric wall penetrating the first channel layer and the first gate structure at the junction of the first and second regions; etching a portion of the thickness of the first gate structure to form a second gate structure, the second gate structure completely surrounding the first channel layer and exposing a portion of the sidewall of the initial dielectric wall; etching a portion of the thickness of the initial dielectric wall of the second gate structure, exposing the remaining initial dielectric wall of the second gate structure as a blocking wall, with the lateral direction parallel to the substrate surface and perpendicular to the extension direction of the initial dielectric wall as the lateral direction, exposing the remaining initial dielectric wall of the second gate structure as a dielectric wall; forming a third gate structure on the second gate structure, the third gate structure exposing the top of the blocking wall.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure provided by this invention, a dielectric wall penetrates the first channel layer and the first gate at the junction of the first and second regions. A blocking wall is located at one end of the top of the dielectric wall, and the projection of the blocking wall on the substrate lies within the projection of the dielectric wall on the substrate. The second gate is located on the side of the blocking wall, between the first gate and the dielectric wall, and exposes the top of the blocking wall. Thus, while electrically isolating the second gate, the blocking wall occupies a small planar area in the semiconductor structure, resulting in a high integration density. Furthermore, because the blocking wall is located at the top of the dielectric wall, the distance between the blocking wall and the channel is relatively large during semiconductor structure operation. The blocking wall is less likely to generate stress on the channel, making it easier for the carrier migration rate in the channel to meet process requirements, which is beneficial for improving the electrical performance of the semiconductor structure.

[0011] In an optional embodiment, the dielectric wall includes a first end and a second end that are laterally opposite each other, and the blocking wall is located at the first end of the dielectric wall. The semiconductor structure further includes a contact plug located on top of the second gate on the side of the second end away from the first end. Since the projection of the blocking wall on the substrate is located in the projection of the dielectric wall on the substrate, the blocking wall is biased at the first end of the dielectric wall, which is beneficial to increase the process space for the contact between the second gate and the contact plug, optimize the semiconductor structure formation process, and improve the electrical performance of the semiconductor structure.

[0012] In the semiconductor structure formation method provided by this invention, the second gate structure exposes a portion of the sidewall of the initial dielectric wall, and a portion of the thickness of one lateral end of the initial dielectric wall is etched to expose the remaining initial dielectric wall of the second gate structure as a blocking wall. A third gate structure is formed on the second gate structure, with the top of the blocking wall exposed. The blocking wall is formed by etching the initial dielectric wall, meaning it is located only directly above the dielectric wall. While electrically isolating the third gate structure, the blocking wall occupies a smaller planar area in the semiconductor structure, resulting in higher integration density. Furthermore, because the blocking wall is formed by etching the initial dielectric wall of the second gate structure, the second gate structure is less susceptible to damage. During semiconductor structure operation, the second and third gate structures can effectively control the opening and closing of the channel, which is beneficial for improving the uniformity and electrical performance of the semiconductor structure. In addition, since the blocking wall is located at the top of the dielectric wall, it is less likely to generate stress on the channel during semiconductor structure operation, making it easier for the carrier migration rate in the channel to meet process requirements, thus improving the electrical performance of the semiconductor structure.

[0013] In an optional embodiment, during the step of forming the blocking wall, the dielectric wall includes a first end and a second end that are laterally opposite, with the blocking wall located at the first end of the dielectric wall. The method for forming the semiconductor structure further includes forming a contact plug on the top of the third gate structure on the side of the second end opposite to the first end. The blocking wall is formed by etching a portion of the thickness of the initial dielectric wall at the lateral end of the second gate structure. Correspondingly, the blocking wall is biased at the first end of the dielectric wall, which helps to increase the process space for the contact between the third gate structure and the contact plug, optimize the semiconductor structure formation process, and improve the electrical performance of the semiconductor structure. Attached Figure Description

[0014] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] Figure 6 This is a schematic diagram of the first embodiment of the semiconductor structure of the present invention;

[0016] Figure 7 This is a schematic diagram of the second embodiment of the semiconductor structure of the present invention;

[0017] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0018] Figures 15 to 17 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0019] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0020] refer to Figures 1 to 5 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0021] like Figure 1As shown, a substrate is provided, the substrate including adjacent first region I, second region II, third region III and fourth region IV, the substrate including substrate 1; fins 9, disposed on the substrate 1; one or more channel layers 2, suspended at intervals on the substrate 1 along the normal direction of the surface of the substrate 1; initial dielectric wall 3, penetrating the channel layer 2 at the junction of the first region I and the second region II, and penetrating the channel layer 2 at the junction of the third region III and the fourth region IV; work function layer 10, completely surrounding the channel layer 2; source and drain doped layers (not shown in the figure), located in the channel layer 2 on both sides of the pseudo-gate structure 4.

[0022] like Figure 2 As shown, the initial dielectric wall 3 with a partial thickness is etched to form the dielectric wall 5.

[0023] like Figure 3 As shown, after the dielectric wall 5 is formed, a metal gate layer 7 is formed surrounding the work function layer 10, and the metal gate layer 7 and the work function layer 10 serve as a gate structure.

[0024] like Figure 4 As shown, with the extension direction of the gate structure perpendicular to the lateral direction, the gate structure at the junction of the first region I and the second region II is etched to form a groove 6, which exposes a portion of the dielectric wall 5 in a lateral dimension.

[0025] like Figure 5 As shown, a blocking layer 8 is formed in the groove 6.

[0026] With the development of semiconductor technology, the size of semiconductor structures is becoming smaller and the integration density is becoming higher. During the formation of the groove 6, the overlay error of the groove 6 has a significant impact on the performance of the semiconductor structure. Due to the overlay error, the groove 6 is not easily formed directly above the dielectric wall 5. Consequently, the top of the dielectric wall 5 cannot be used as the etching stop position during the formation of the groove 6, and the metal gate layer 72 and work function layer 10 on one side of the dielectric layer 5 are easily etched, exposing the channel layer 2. Because the work function layer 10 is damaged, it cannot effectively regulate the threshold voltage of the transistor in the first region I during semiconductor structure operation, resulting in poor uniformity of semiconductor structure performance. Furthermore, because the groove 6 exposes the channel layer 2, the blocking layer 8 is formed in the groove 6. During semiconductor structure operation, the blocking layer 8 is prone to compressing the channel, causing the stress in the channel to deviate from the design, and the carrier migration rate in the channel to fail to meet process requirements, resulting in poor electrical performance of the semiconductor structure.

[0027] To address the technical issues, the semiconductor structure provided in this invention features a dielectric wall that penetrates the first channel layer and the first gate at the junction of the first and second regions. A blocking wall is located at one end of the top of the dielectric wall, and its projection onto the substrate falls within the projection of the dielectric wall onto the substrate. This results in a smaller planar area occupied by the blocking wall in the semiconductor structure, leading to higher integration density. Furthermore, because the blocking wall is located at the top of the dielectric wall, the distance between the blocking wall and the channel is greater during semiconductor operation. This reduces the likelihood of the blocking wall generating stress on the channel, making it easier to meet process requirements for carrier migration rates in the channel, thus improving the electrical performance of the semiconductor structure.

[0028] In the semiconductor structure formation method provided by this invention, the second gate structure exposes a portion of the sidewall of the initial dielectric wall, a portion of the thickness of one lateral end of the initial dielectric wall is etched, exposing the remaining initial dielectric wall of the second gate structure as a blocking wall, and a third gate structure is formed on the second gate structure, with the third gate structure exposing the top of the blocking wall. The blocking wall is formed by etching the initial dielectric wall, meaning it is located only directly above the dielectric wall. The blocking wall occupies a small planar area, resulting in higher integration density of the semiconductor structure. Furthermore, because the blocking wall is formed by etching the initial dielectric wall exposing the second gate structure, the second gate structure is less susceptible to damage. During semiconductor structure operation, the second and third gate structures can effectively control the channel, which is beneficial for improving the uniformity and electrical performance of the semiconductor structure. In addition, since the blocking wall is located at the top of the dielectric wall, it is less likely to generate stress on the channel during semiconductor structure operation, making it easier for the carrier migration rate in the channel to meet process requirements, thus improving the electrical performance of the semiconductor structure.

[0029] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] This invention provides a semiconductor structure. (See reference...) Figure 6 The diagram shows a schematic diagram of the first embodiment of the semiconductor structure of the present invention.

[0031] The semiconductor structure includes: a substrate 300, the substrate 300 including a first region I and a second region II; one or more first channel layers 301, spaced apart and suspended on the substrate 300 along the normal direction of the surface of the substrate 300; a first gate 307, located on the substrate 300, and the first gate 307 completely surrounds the first channel layers 301; a dielectric wall 308, penetrating the first channel layer 301 and the first gate 307 at the junction of the first region I and the second region II, with its extension direction parallel to the surface of the substrate 300 and perpendicular to the extension direction of the dielectric wall 308 being laterally oriented; a blocking wall 309, located at one laterally oriented end of the top of the dielectric wall 308, the projection of the blocking wall 309 on the substrate 300 being located in the projection of the dielectric wall 308 on the substrate 300; and a second gate 314, located on the first gate 307 and the dielectric wall 308 on the side of the blocking wall 309, and exposing the top of the blocking wall 309.

[0032] In the semiconductor structure provided by this embodiment of the invention, a dielectric wall 308 penetrates the first channel layer 301 and the first gate 307 at the junction of the first region I and the second region II. A blocking wall 309 is located at one end of the top of the dielectric wall 308, and the projection of the blocking wall 309 on the substrate 300 is located in the projection of the dielectric wall 308 on the substrate 300. A second gate 314 is located on the side of the blocking wall 309, on the first gate 307 and the dielectric wall 308, and exposes the top of the blocking wall 309. Thus, while electrically isolating the second gate 314, the blocking wall 309 occupies a small planar area of ​​the semiconductor structure, resulting in a high integration density of the semiconductor structure. In addition, because the blocking wall 309 is located on top of the dielectric wall 308, the distance between the blocking wall 309 and the channel is relatively large when the semiconductor structure is working. The blocking wall 309 is less likely to generate stress on the channel, making it easier for the carrier migration rate in the channel to meet the process requirements, which is beneficial to improving the electrical performance of the semiconductor structure.

[0033] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conduction types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor).

[0034] In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0035] When the semiconductor structure is in operation, the first channel layer 301 is used as a channel region.

[0036] In this embodiment, the material of the first channel layer 301 is silicon; in other embodiments, the material of the first channel layer may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials.

[0037] It should be noted that the plurality of first channel layers 301 are spaced apart in the normal direction of the surface of the substrate 300.

[0038] When the semiconductor structure is in operation, the first gate 307 and the second gate 314 jointly control the opening and closing of the channel.

[0039] In this embodiment, the first gate 307 includes a work function layer 310 located on the surface of the first channel layer 301 and a metal gate layer 312 surrounding the work function layer 310.

[0040] When the semiconductor structure is in operation, the work function layer 310 is used to control the threshold voltage of the semiconductor structure, and the metal gate layer 312 is used to control the opening and closing of the channel.

[0041] It should be noted that in this embodiment, the work function layer 310 is relatively thick, filling the region between the first channel layer 301 and the first channel layer 301. During semiconductor structure operation, this allows the work function layer 310 to more precisely adjust the threshold voltage of the first-type transistor in the first region I. In other embodiments, the work function layer is thinner, and an initial metal gate layer is formed between the work function layers along the normal direction of the substrate surface.

[0042] The semiconductor structure further includes: source and drain doped layers (not shown in the figure), and a plurality of first channel layers 301 penetrating both sides of the first gate 307.

[0043] When the semiconductor structure is in operation, the source and drain doped layers are used to provide stress to the channel and improve the migration rate of charge carriers in the channel.

[0044] Specifically, the first source / drain doped layer is located in the first region I, and the second source / drain doped layer is located in the second region II.

[0045] The first type of transistor is a PMOS, and the first source / drain doped layer serves as the source and drain of the PMOS. During operation of the semiconductor structure, the first source / drain doped layer applies compressive stress to the channel, which increases the hole mobility. The second type of transistor is an NMOS, and the second source / drain doped layer serves as the source and drain of the NMOS. During operation of the semiconductor structure, the second source / drain doped layer applies tensile stress to the channel, which increases the electron mobility.

[0046] The dielectric wall 308 is used to electrically isolate the first channel layer 301 and the first gate 307 of the first region I from the first channel layer 301 and the first gate 307 of the second region II.

[0047] In this embodiment, the dielectric wall 308 is formed on the substrate 300 at the junction of the first region I and the second region II, with the direction parallel to the surface of the substrate 300 and perpendicular to the extension direction of the dielectric wall 308 as the lateral direction. This means that there is no need to reserve too much lateral dimension between the first type transistor and the second type transistor, which can improve the utilization rate of the substrate 300 plane, and the semiconductor structure has a high degree of integration, which is beneficial to reducing the energy consumption of the semiconductor structure.

[0048] In this embodiment, the dielectric wall 308 is made of a low-k dielectric material. (A low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9). Low-k dielectric materials have excellent insulation properties, and when the semiconductor structure is working, the capacitive coupling effect between the first gate in the first type transistor and the first gate in the second type transistor is weak, which is beneficial to improving the electrical performance of the semiconductor structure.

[0049] Specifically, the dielectric wall 308 is made of one or more of the following materials: SiON, SiBCN, SiCN, carbon-doped SiN, and oxygen-doped SiN. In this embodiment, the dielectric wall 308 is made of carbon-doped SiN and oxygen-doped SiN.

[0050] It should be noted that the lateral dimension of the dielectric wall 308 should not be too large or too small. If the lateral dimension of the dielectric wall 308 is too large, the area occupied by the dielectric wall 308 on the substrate 300 of the semiconductor structure will be too large, which is not conducive to improving the integration density of the semiconductor structure. Consequently, the energy consumption of the semiconductor structure will not be easily reduced during operation. If the lateral dimension of the dielectric wall 308 is too small, the dielectric wall 308 cannot effectively electrically isolate the first gate 307 of the first type transistor and the first gate 307 of the second type transistor. Leakage current is likely to exist between the first gate 307 of the first type transistor and the first gate 307 of the second type transistor, resulting in poor electrical performance of the semiconductor structure.

[0051] It should be noted that the dielectric wall 308 penetrates the first channel layer 301 and the first gate 307 at the junction of the first region I and the second region II. The dielectric wall 308 makes it difficult for the first source / drain doped layer and the second source / drain doped layer to bridge, which is beneficial to improving the electrical performance of the semiconductor structure.

[0052] It should be noted that the dielectric wall 308 includes a first end e and a second end f that are laterally opposite.

[0053] When the semiconductor structure is in operation, the second gate 314 and the first gate 307 are used to control the opening and closing of the channel.

[0054] Specifically, the material of the second gate 314 includes one or more of W, Co, and Ru. In this embodiment, the material of the second gate 314 includes W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure.

[0055] The semiconductor structure further includes a contact plug 315 located on top of the second gate 314 on the side of the second end f opposite to the first end e.

[0056] The contact plug 315 is used to connect the second gate 314 to the subsequent interconnect structure, that is, to connect the second gate 314 and the first gate 307 together to the subsequent interconnect structure.

[0057] In this embodiment, the contact plug 315 is made of a conductive material. Specifically, the contact plug 315 includes one or more of W, Co, and Ru. In this embodiment, the contact plug 315 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0058] A blocking wall 309 is used to electrically isolate the second gate 314 located on its lateral sides. Compared to the case where the blocking wall is in contact with the first channel layer, the blocking wall 309 is located on top of the dielectric wall 308. During semiconductor structure operation, the blocking wall 309 is less likely to generate stress on the channel, making it easier for the carrier migration rate in the channel to meet process requirements, which is beneficial to improving the electrical performance of the semiconductor structure. The blocking wall 309 and the dielectric wall 308 together are used to electrically isolate the first gate 307 and the second gate 314.

[0059] In this embodiment, the material of the blocking wall 309 is a low-k dielectric material. (Low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9). Low-k dielectric materials have excellent insulation properties. When the semiconductor structure is working, the capacitive coupling effect between the second gate 314 in the first type transistor and the second gate 314 in the second type transistor is weak, which is beneficial to improving the electrical performance of the semiconductor structure.

[0060] Specifically, the material of the barrier wall 309 includes one or more of SiON, SiBCN, SiCN, carbon-doped SiN, and oxygen-doped SiN. In this embodiment, the material of the barrier wall 309 includes carbon-doped SiN and oxygen-doped SiN.

[0061] It should be noted that the blocking wall 309 is located at one of the top transverse ends of the dielectric wall 308. The projection of the blocking wall 309 on the substrate 300 lies within the projection of the dielectric wall 308 on the substrate 300. Furthermore, in the direction perpendicular to the normal to the surface of the substrate 300, one transverse sidewall of the blocking wall 309 is flush with one transverse sidewall of the dielectric wall 308. In other words, the blocking wall 309 is offset at the top of the dielectric wall 308 and is not directly above the first gate 307. This increases the connection process window between the contact plug 315 and the second gate 314, while also increasing the contact area between the first gate 307 and the second gate 314, which is beneficial for improving the current characteristics of the semiconductor structure.

[0062] Specifically, the blocking wall 309 is located at the first end e of the dielectric wall 308 in the transverse direction.

[0063] In this embodiment, the first end e is located in the first region I, and the second end f is located in the second region II. Correspondingly, the blocking wall 309 is biased onto the first end e laterally of the dielectric wall 308, increasing the contact process window between the contact plug 315 and the second gate 314 of the second region II, optimizing the semiconductor structure formation process, and improving the electrical performance of the semiconductor structure. In other embodiments, the blocking wall may also be biased onto the second end laterally of the dielectric wall, increasing the contact process window between the contact plug and the third gate structure of the first region I, optimizing the semiconductor structure formation process, and improving the electrical performance of the semiconductor structure.

[0064] It should be noted that the lateral dimension of the blocking wall 309 should not be too large or too small. If the lateral dimension of the blocking wall 309 is too large, the area occupied by the blocking wall 309 in the lateral direction will be too large, and the area occupied by the second gate 314 in the lateral direction will be too small. The process window for contacting the contact plug 315 with the second gate 314 in the second region II will be small. During the formation of the contact plug 315, even a small overlay error can easily cause the contact plug 315 to be formed on the blocking wall 309, resulting in a high contact resistance between the contact plug 315 and the second gate 314, leading to poor electrical performance of the semiconductor structure. If the lateral dimension of the blocking wall 309 is too small, the blocking wall 309 cannot effectively electrically isolate the second gate 314 in the first type transistor from the second type transistor, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral dimension of the blocking wall 309 is 14 nanometers to 20 nanometers.

[0065] The semiconductor structure further includes a dielectric layer 316 located on the second gate 314 on the side of the contact plug 315.

[0066] The dielectric layer 316 is used to electrically isolate the contact plug 315. In this embodiment, the dielectric layer 316 is an insulating material. Specifically, in this embodiment, the material of the dielectric layer 316 is silicon oxide.

[0067] The semiconductor structure further includes a fin 302 located between the substrate 300 and the first channel layer 301.

[0068] In this embodiment, the material of the fin 302 is the same as the material of the substrate 300. In other embodiments, the material of the fin may be different from the material of the substrate.

[0069] The fin 302 is used to space the plurality of first channel layers 301 from the substrate 300.

[0070] An isolation layer 305 is located on the substrate 300 between the fins 302, and the isolation layer 305 covers the sidewalls of the fins 302.

[0071] The isolation layer 305 is formed on the substrate 300 between the fins 302 and is capable of electrically isolating adjacent fins 302.

[0072] In this embodiment, the material of the isolation layer 305 is an insulating material. Specifically, in this embodiment, the material of the isolation layer 305 is silicon oxide.

[0073] The semiconductor structure further includes a linear oxide layer 317 located between the fin 302 and the isolation layer 305, and between the substrate 300 and the isolation layer 305.

[0074] The linear oxide layer 317 is used to repair lattice damage on the surface of the fin 302 and the surface of the substrate 300, thereby improving the formation quality of the fin 302.

[0075] In this embodiment, the linear oxide layer 317 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the linear oxide layer 317.

[0076] The semiconductor structure further includes an isolation structure 306 located between the fin 302 and the first gate 307.

[0077] The isolation structure 306 is used to electrically isolate the first gate 307 and the fin 302, so that parasitic capacitance is not easily generated between the first gate 307 and the fin 302 when the semiconductor structure is working.

[0078] The semiconductor structure also includes adjacent third region III and fourth region IV. The transistors subsequently formed in third region III and fourth region IV have different conductivity types.

[0079] The substrates in the third region III and the fourth region IV include: a substrate 300; one or more second channel layers 601, suspended at intervals on the substrate 300 along the normal direction of the surface of the substrate 300; a first gate 307, which completely surrounds the second channel layers 601; and a dielectric wall 308, which penetrates the second channel layer 601 and the first gate 307 at the junction of the third region III and the fourth region IV.

[0080] It should be noted that the plurality of second channel layers 601 are spaced apart in the normal direction of the surface of the substrate 300.

[0081] Accordingly, the fin 302 is used to space the plurality of second channel layers 601 from the substrate 300.

[0082] refer to Figure 7 The diagram shows a schematic representation of a second embodiment of the semiconductor structure of the present invention.

[0083] The similarities between this embodiment and the first embodiment will not be repeated here. The differences between this embodiment and the first embodiment are as follows:

[0084] The semiconductor structure further includes a sidewall material layer 408 located on the sidewall of the blocking wall 403 near the first end e of the dielectric wall 410, and the bottom of the sidewall material layer 408 is in contact with the first gate 407.

[0085] The sidewall material layer 408 and the blocking wall 403 are used together to block the second gate 414, which has a better blocking effect compared with the case where only the blocking wall is used to block the second gate.

[0086] Specifically, the sidewall material layer 408 is made of materials including SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the sidewall material layer 408 is made of carbon-doped SiN or oxygen-doped SiN. The sidewall material layer 408 is made of the same material as the barrier wall 403, resulting in good adhesion between the sidewall material layer 408 and the barrier wall 403, which is beneficial for improving the process compatibility of the sidewall material layer 408.

[0087] It should be noted that the lateral dimension of the sidewall material layer 408 should not be too large or too small. If the lateral dimension of the sidewall material layer 408 is too large, it will require too much processing time to form, which is not conducive to improving the formation efficiency of the semiconductor structure. Furthermore, if the lateral dimension of the sidewall material layer 408 is too large, it will occupy too much of the area on top of the first gate 407 in the first region I, resulting in a smaller contact area between the second gate 414 and the first gate 407 in the first region, and a correspondingly larger contact resistance, leading to poor current characteristics of the semiconductor structure. If the sidewall material layer 408 is too thin, compared with using only a blocking wall to electrically isolate the second gates on both sides of the blocking wall, the effect of the sidewall material layer 408 and the blocking wall 403 electrically isolating the second gate 414 together is not significantly improved. The second gates 414 on both sides of the blocking wall 403 are still easily bridged, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral dimension of the sidewall material layer 408 is 1 nanometer to 5 nanometers.

[0088] It should be noted that the sidewall material layer 408 is also located on top of the dielectric wall 403. Therefore, the combination of the sidewall material layer 408 and the blocking wall 403 can electrically isolate the second gate 414, which has a larger thickness, compared with the case of only the blocking wall.

[0089] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the present application.

[0090] refer to Figure 8 A substrate is provided, the substrate including adjacent first region I and second region II, the substrate including: a substrate 100; one or more first channel layers 101, spaced apart and suspended on the substrate 100 along the normal direction of the surface of the substrate 100; a first gate structure 104, completely surrounding the first channel layers 101; and an initial dielectric wall 103, penetrating the first channel layers and the first gate structure 104 at the junction of the first region I and the second region II.

[0091] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conduction types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor).

[0092] Substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

[0093] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0094] When the semiconductor structure is in operation, the first channel layer 101 is used as a channel region.

[0095] In this embodiment, the material of the first channel layer 101 is silicon; in other embodiments, the material of the first channel layer may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials.

[0096] It should be noted that the plurality of first channel layers 101 are spaced apart in the normal direction of the surface of the substrate 100.

[0097] The first gate structure 104 is subsequently etched to a certain thickness to form a second gate structure. A third gate structure is then formed on the second gate structure. When the semiconductor structure is working, the second gate structure and the third gate structure jointly control the opening and closing of the channel.

[0098] In this embodiment, the first gate structure 104 includes a work function layer 110 formed on the surface of the first channel layer 101 and an initial metal gate layer 111 surrounding the work function layer 110.

[0099] When the semiconductor structure is in operation, the work function layer 110 is used to control the threshold voltage of the semiconductor structure, and the initial metal gate layer 111 is used to control the opening and closing of the channel.

[0100] It should be noted that in this embodiment, the work function layer 110 is relatively thick, filling the area between the first channel layer 101 and the first channel layer 101. During semiconductor structure operation, this allows the work function layer 310 to more precisely adjust the threshold voltage of the first-type transistor in the first region. In other embodiments, the work function layer is thinner, and an initial metal gate layer is formed between the work function layers along the normal direction of the substrate surface.

[0101] In the step of providing the substrate, the first gate structure 104 has source and drain doped layers (not shown in the figure) that penetrate the plurality of first channel layers 101 on both sides.

[0102] When the semiconductor structure is in operation, the source and drain doped layers are used to provide stress to the channel and improve the migration rate of charge carriers in the channel.

[0103] Specifically, the first source / drain doped layer is located in the first region I, and the second source / drain doped layer is located in the second region II.

[0104] Region I is used to form a PMOS, and the first source / drain doped layer serves as the source and drain of the PMOS. During operation, the first source / drain doped layer applies compressive stress to the channel, which increases hole mobility. Region II is used to form an NMOS, and the second source / drain doped layer serves as the source and drain of the NMOS. During operation, the second source / drain doped layer applies tensile stress to the channel, which increases electron mobility.

[0105] An initial dielectric wall 103 is used to electrically isolate the first channel layer 101 of the first region I and the first gate structure 104 of the second region II.

[0106] In this embodiment, the extension direction of the initial dielectric wall 103, which is parallel to the surface of the substrate 100 and perpendicular to the extension direction of the initial dielectric wall 103, is taken as the lateral direction. The initial dielectric wall 103 is formed on the substrate 100 at the junction of the first region I and the second region II. This means that there is no need to reserve too much lateral dimension between the first type transistor and the second type transistor, which can improve the utilization rate of the substrate 100 plane and the semiconductor structure has a high degree of integration, which is beneficial to reducing the energy consumption of the semiconductor structure.

[0107] In this embodiment, the initial dielectric wall 103 is made of a low-k dielectric material. (A low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9). Low-k dielectric materials have excellent insulation properties. When the semiconductor structure is working, the capacitive coupling effect between the second and third gate structures in the first type transistor and the second and third gate structures in the second type transistor is weak, which is beneficial to improving the electrical performance of the semiconductor structure.

[0108] Specifically, the material of the initial dielectric wall 103 includes one or more of SiON, SiBCN, SiCN, carbon-doped SiN, and oxygen-doped SiN. In this embodiment, the material of the initial dielectric wall 103 includes carbon-doped SiN and oxygen-doped SiN.

[0109] It should be noted that in the step of providing the initial dielectric wall 103, the lateral dimension of the initial dielectric wall 103 should not be too large or too small. If the lateral dimension of the initial dielectric wall 103 is too large, the surface area occupied by the initial dielectric wall 103 on the substrate 100 of the semiconductor structure will be too large, which is not conducive to improving the integration of the semiconductor structure. Consequently, the energy consumption of the semiconductor structure will not be easily reduced during operation. When the initial dielectric wall 103 is subsequently etched, the initial dielectric wall 103 located in the second gate structure serves as the dielectric wall. If the lateral dimension of the initial dielectric wall 103 is too small, the dielectric wall cannot effectively electrically isolate the second gate structure in the first type transistor and the second gate structure in the second type transistor. Leakage current is likely to exist between the second gate structure of the first type transistor and the second gate structure of the second type transistor, resulting in poor electrical performance of the semiconductor structure.

[0110] It should be noted that the initial dielectric wall 103 penetrates the first channel layer 101 and the first gate structure 104 at the junction of the first region I and the second region II. The corresponding initial dielectric wall 103 makes it difficult for the first source / drain doped layer and the second source / drain doped layer to bridge, which is beneficial to improving the electrical performance of the semiconductor structure.

[0111] It should be noted that, in the step of providing the substrate, the substrate further includes: a fin 102 located between the substrate 100 and the first channel layer 101.

[0112] In this embodiment, the material of the fin 102 is the same as the material of the substrate 100. In other embodiments, the material of the fin may be different from the material of the substrate.

[0113] The fin 102 is used to space the plurality of first channel layers 101 from the substrate 100.

[0114] An isolation layer 105 is located on the substrate 100 between the fins 102, and the isolation layer 105 covers the sidewalls of the fins 102.

[0115] The isolation layer 105 is formed on the substrate 100 between the fins 102 and is capable of electrically isolating the fins 102.

[0116] In this embodiment, the material of the isolation layer 105 is an insulating material. Specifically, in this embodiment, the material of the isolation layer 105 is silicon oxide.

[0117] In the step of providing the substrate, a liner oxide layer 117 is formed between the fin 102 and the isolation layer 105, and between the substrate 100 and the isolation layer 105.

[0118] The linear oxide layer 117 is used to repair lattice damage on the surface of the fin 102 and the surface of the substrate 100, thereby improving the formation quality of the fin 102.

[0119] In this embodiment, the linear oxide layer 117 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the linear oxide layer 117.

[0120] In the step of providing the substrate, an isolation structure 106 is formed between the fin 102 and the first gate 107.

[0121] The isolation structure 106 is used to electrically isolate the first gate 107 and the fin 102, so that parasitic capacitance is not easily generated between the first gate 107 and the fin 102 when the semiconductor structure is working.

[0122] In the step of providing the substrate, the substrate further includes adjacent third region III and fourth region IV. The transistors formed in the third region III and the fourth region IV have different conductivity types.

[0123] The substrates in the third region III and the fourth region IV include: a substrate 100; one or more second channel layers 501, spaced apart and suspended on the substrate 100 along the normal direction of the surface of the substrate 100; a first gate structure 104, which completely surrounds the second channel layers 501; and an initial dielectric wall 103, which penetrates the second channel layer 501 and the first gate structure 104 at the junction of the third region III and the fourth region IV.

[0124] It should be noted that the plurality of second channel layers 501 are spaced apart in the normal direction of the surface of the substrate 100.

[0125] refer to Figure 9 The first gate structure 104, with a portion of its thickness etched, forms a second gate structure 107. The second gate structure 107 completely surrounds the first channel layer 101 and exposes a portion of the sidewall of the initial dielectric wall 103.

[0126] The second gate structure 107 exposes a portion of the sidewall of the initial dielectric wall 103, in preparation for subsequent etching to expose one lateral end of the initial dielectric wall 103 of the second gate structure 107, forming a blocking wall and a dielectric wall.

[0127] In this embodiment, a dry etching process is used to etch a portion of the first gate structure 104 to form a second gate structure 107. Dry etching has anisotropic etching characteristics and good control over the etching profile, which helps ensure the morphology of the second gate structure 107 meets process requirements. Furthermore, using dry etching to remove a portion of the first gate structure 104 allows for precise control of the thickness of the removed first gate structure 104. In other embodiments, a wet etching process can also be used to etch a portion of the first gate structure to form a second gate structure. Wet etching is isotropic etching, resulting in better horizontality and flatness of the etched second gate structure surface. Wet etching has a high etching rate, and using a low-concentration wet etching solution further facilitates control over the thickness of the removed first gate structure 104.

[0128] Specifically, in the step of etching a portion of the thickness of the first gate structure 104 to form the second gate structure 107, the initial metal gate layer 111 is etched to form a metal gate layer 112. Accordingly, the second gate structure 107 includes a work function layer 110 and a metal gate layer 112.

[0129] It should be noted that in the step of etching the first gate structure 104 with a certain thickness to form the second gate structure 107, the etching rate of the first gate structure 104 is greater than the etching rate of the initial dielectric wall 103, so that the initial dielectric wall 103 is not easily damaged.

[0130] refer to Figure 10 and Figure 11 With the extension direction of the initial dielectric wall 103 parallel to the surface of the substrate 100 and perpendicular to the extension direction of the initial dielectric wall 103 as the lateral direction, the lateral end of the initial dielectric wall 103 of the second gate structure is etched to expose the remaining initial dielectric wall 103 of the second gate structure 107 as the blocking wall 109, and the remaining initial dielectric wall 103 in the second gate structure 107 as the dielectric wall 108.

[0131] The second gate structure 107 exposes a portion of the sidewall of the initial dielectric wall 103. A portion of the thickness of one lateral end of the initial dielectric wall 103 is etched to expose the remaining portion of the initial dielectric wall 103 of the second gate structure 107, serving as a blocking wall 109. Subsequently, a third gate structure is formed on the second gate structure 107, with the third gate structure exposing the top of the blocking wall 109. The blocking wall 109 is formed by etching the initial dielectric wall 103, and correspondingly, the blocking wall 109 is located only directly above the dielectric wall 108. While electrically isolating the third gate structure, the blocking wall 109 occupies a small area of ​​the semiconductor structure plane, resulting in a high integration density of the semiconductor structure. Furthermore, because the blocking wall 109 is formed by etching the initial dielectric wall 103 of the second gate structure 107, the second gate structure 107 is less susceptible to damage. During semiconductor structure operation, the second gate structure 107 and the third gate structure can effectively control the opening and closing of the channel, which is beneficial for improving the uniformity and electrical performance of the semiconductor structure. Furthermore, the blocking wall 109 is located on top of the dielectric wall 108. When the semiconductor structure is working, the blocking wall 109 is less likely to generate stress on the channel, making it easier for the migration rate of charge carriers in the channel to meet process requirements, which is beneficial to improving the electrical performance of the semiconductor structure.

[0132] The blocking wall 109 is formed by etching one lateral end of the initial dielectric wall 103 that exposes the second gate structure 107. Correspondingly, in the normal direction of the substrate 100 surface, one sidewall of the blocking wall 109 is flush with one sidewall of the dielectric wall 108 in the lateral direction. That is, the blocking wall 109 is biased at the top of the dielectric wall 108, and the other sidewall of the blocking wall 109 is not located directly above the first gate 107. In other words, the blocking wall 109 is biased at the top of the dielectric wall 108. Subsequently, a contact plug is formed on the third gate structure, which is beneficial to improving the connection process window between the contact plug and the third gate structure, and increases the contact area between the first gate 307 and the second gate 314, which is beneficial to improving the current characteristics of the semiconductor structure.

[0133] In this embodiment, the blocking wall 109 and the dielectric wall 108 can effectively electrically isolate the second gate structure 107 and the third gate structure.

[0134] In this embodiment, in the step of forming the dielectric wall 108, the dielectric wall 108 includes a first end e and a second end f that are laterally opposite, and the blocking wall 109 is located at the first end e of the dielectric wall 108.

[0135] In this embodiment, the first end e is located in the first region I, and the second end f is located in the second region II. Correspondingly, the blocking wall 109 is biased onto the first end e, which is laterally positioned on the dielectric wall 108. This increases the contact process window between the contact plug and the third gate structure of the second region II, optimizes the semiconductor structure formation process, and improves the electrical performance of the semiconductor structure. In other embodiments, the blocking wall may also be biased onto the second end, which is laterally positioned on the dielectric wall. This further increases the contact process window between the contact plug and the third gate structure of the first region I, optimizes the semiconductor structure formation process, and improves the electrical performance of the semiconductor structure.

[0136] In this embodiment, the blocking wall 109 and the dielectric wall 108 are formed by etching the initial dielectric wall 103, so the blocking wall 109 and the dielectric layer 108 are made of the same material.

[0137] Specifically, the step of etching to expose one lateral end of the initial dielectric wall 103 of the second gate structure 107 to form the blocking wall 109 includes: as follows Figure 10 As shown, a mask layer 113 is formed on the initial dielectric wall 103 and the second gate structure 107, the mask layer 113 exposing one lateral end of the initial dielectric wall 103; as Figure 11 As shown, the initial dielectric wall 103 of the second gate structure 107 is etched to expose one lateral end using the mask layer 113 as a mask, forming the blocking wall 109.

[0138] In this embodiment, using the mask layer 113 as a mask, an anisotropic dry etching process is employed to etch one lateral end of the initial dielectric wall 103 of the second gate structure 107, forming a blocking wall 109. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps ensure that the morphology of the blocking wall 109 meets process requirements. Furthermore, during the dry etching process of the exposed lateral portion of the initial dielectric wall 103 of the second gate structure 107, the top of the second gate structure 107 can be used as the etching stop position, resulting in less damage to the second gate structure 107. During semiconductor structure operation, the second gate structure 107 can effectively control the opening and closing of the channel.

[0139] In this embodiment, the mask layer 113 exposes one end of the initial dielectric wall 103 laterally. The mask layer 113 includes an organic material layer 1131, an anti-reflective coating 1132 on the organic material layer 1131, and a photoresist layer 1133 on the anti-reflective coating 1132.

[0140] In this embodiment, the organic material layer 1131 includes: SOC (spin on carbon), ODL (organic dielectric layer) material, photoresist, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.

[0141] In this embodiment, the anti-reflective coating 1132 includes: BARC (bottom anti-reflective coating) material and DARC (dielectric anti-reflective coating) material.

[0142] It should be noted that, in other embodiments, the step of forming the blocking wall further includes: after etching to expose one lateral end of the initial dielectric wall of the second gate structure, performing a lateral trimming process on the sidewall of the exposed initial dielectric wall of the second gate structure to expose the remaining initial dielectric wall of the second gate structure as the blocking wall.

[0143] The sidewalls of the initial dielectric wall exposed by the second gate structure are laterally trimmed to fine-tune the lateral dimensions of the blocking wall, so that the lateral dimensions of the blocking wall meet the design dimensions, thereby increasing the contact space between the subsequently formed contact plug and the third gate structure and reducing the difficulty of forming the contact plug.

[0144] In this embodiment, an isotropic dry etching process is used to laterally trim the sidewalls of the barrier wall exposed by the second gate structure in order to fine-tune the lateral dimensions of the barrier wall.

[0145] In this embodiment, the material of the blocking wall 109 is carbon-doped SiN and oxygen-doped SiN, and the corresponding etching gases include CHF3 and CH2F2.

[0146] It should be noted that in other embodiments, the step of forming the blocking wall may not include lateral trimming of the initial dielectric wall exposed by the second gate structure.

[0147] It should be noted that in the step of forming the blocking wall 109, the lateral dimension of the blocking wall 109 should not be too large or too small. Subsequently, a third gate structure is formed on the second gate structure 107 exposed by the blocking wall 109. If the lateral dimension of the blocking wall 109 is too large, the area occupied by the blocking wall 109 in the lateral direction will be too large, and the corresponding area occupied by the third gate structure in the lateral direction will be too small. This results in a smaller process window for the contact plug to contact the third gate structure in the second region II. During the formation of the contact plug, even a small overlay error can easily cause the contact plug to form on the blocking wall 109, leading to high contact resistance between the contact plug and the third gate structure, resulting in poor electrical performance of the semiconductor structure. If the lateral dimension of the blocking wall 109 is too small, the blocking wall 109 cannot effectively electrically isolate the third gate structure subsequently formed on both sides of the blocking wall 109 in the lateral direction, also resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral dimension of the blocking wall 109 is 14 nanometers to 20 nanometers.

[0148] It should be noted that in the step of etching the initial dielectric wall 103 of the exposed lateral dimension of the second gate structure 107 to form the dielectric wall 108, the initial dielectric wall 103 exposed in the third region III and the fourth region IV is removed.

[0149] In the step of etching to expose one lateral end of the initial dielectric wall 103 of the second gate structure 107 to form a blocking wall, the initial dielectric wall 103 exposing the second gate structure 107 in the third region III and the fourth region IV is removed. Correspondingly, in the step of forming a third gate structure on the second gate structure 107, the third gate structures formed in the third region III and the fourth region IV are connected.

[0150] It should be noted that the method for forming the semiconductor structure further includes: after forming the blocking wall 109, removing the mask layer 113.

[0151] In this embodiment, the mask layer 113 includes an organic material layer 1131, an anti-reflective coating 1132 on the organic material layer 1131, and a photoresist layer 1133 on the anti-reflective coating 1132. Accordingly, the mask layer 113 is removed by an ashing process.

[0152] refer to Figure 12 A third gate structure 114 is formed on the second gate structure 107, and the third gate structure 114 is exposed on the top of the blocking wall 109.

[0153] The third gate structure 114 and the second gate structure 107 together serve as the gate structure of the semiconductor structure. When the semiconductor structure is in operation, the third gate structure 114 and the second gate structure 107 are used to control the opening and closing of the channel.

[0154] Furthermore, the third gate structure 114 is exposed on the top of the blocking wall 109. When the semiconductor structure is in operation, the blocking wall 109 and the dielectric wall 108 can laterally block the second gate structure 107 and the third gate structure 114 in the first region I and the second region II, so that the electrical performance of the semiconductor structure meets the process requirements.

[0155] Specifically, the material of the third gate structure 114 includes one or more of W, Co, and Ru. In this embodiment, the material of the third gate structure 114 includes W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0156] The step of forming a third gate structure 114 on the second gate structure 107 includes: forming a gate material layer (not shown) on the second gate structure 107 and the blocking wall 109; removing the gate material layer above the blocking wall, and the remaining gate material layer serving as the third gate structure 114.

[0157] In this embodiment, an electroplating (ECP) process is used to form a gate material layer on the second gate structure 107 and the blocking wall 109. The electrochemical electroplating process has advantages such as simple operation, fast deposition speed, and low cost.

[0158] In this embodiment, chemical mechanical planarization (CMP) is used to remove the gate material layer above the barrier wall 109. CMP is a global surface planarization technique used to improve the flatness of the top of the third gate structure 114, and the planarization process can stop at the top of the barrier wall 109. In other embodiments, dry etching can also be used to remove the gate material layer above the barrier wall.

[0159] refer to Figure 13 and Figure 14 A contact plug 115 is formed on the top of the third gate structure 114 on the side of the second end f away from the first end.

[0160] Contact plug 115 is used to connect the third gate structure 114 to the subsequent interconnect structure, that is, to connect the third gate structure 114 and the second gate structure 107 together with the subsequent interconnect structure. The blocking wall 109 is formed by etching a portion of the thickness of the lateral end of the initial dielectric wall 103 of the second gate structure 114. Correspondingly, the blocking wall 109 is biased at the lateral end of the dielectric wall 108, which helps to increase the process space for the contact between the blocking wall 109, the third gate structure 114 and the contact plug 115, optimize the semiconductor structure formation process, and improve the electrical performance of the semiconductor structure.

[0161] Specifically, the steps of forming the contact plug 115 include: forming a dielectric layer 116 on the blocking wall 109 and the third gate structure 114; etching the dielectric layer 116 to form an opening that exposes the third gate structure 114 in the second region II; and forming the contact plug 115 in the opening.

[0162] The dielectric layer 116 is used to electrically isolate the contact plug 115.

[0163] In this embodiment, the dielectric layer 116 is an insulating material. Specifically, in this embodiment, the material of the dielectric layer 116 is silicon oxide.

[0164] In this embodiment, the contact plug 115 is made of a conductive material. Specifically, the contact plug 115 includes one or more of W, Co, and Ru. In this embodiment, the contact plug 115 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0165] Figures 15 to 17 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the method for forming a semiconductor structure according to the present application.

[0166] The similarities between this embodiment and the first embodiment will not be repeated here. The differences are as follows:

[0167] refer to Figure 15 The method for forming the semiconductor structure further includes: etching a portion of the thickness of the first gate structure, forming the second gate structure 207, and before etching one lateral end of the initial dielectric wall 203 exposing the second gate structure 207, conformally covering a sidewall material layer 208 on the initial dielectric wall 203 and the second gate structure 207 exposed by the initial dielectric wall 203.

[0168] During the subsequent etching process to expose one lateral end of the initial dielectric wall 203 of the second gate structure 207 and form a blocking wall, the sidewall material layer 208 on one lateral sidewall of the initial dielectric wall 203 is etched, while the sidewall material layer 208 on the other lateral sidewall of the initial dielectric wall 203 is retained. The sidewall material layer 208 on the other lateral sidewall of the initial dielectric wall 203 is used to increase the lateral dimension of the subsequently formed blocking wall.

[0169] In this embodiment, the sidewall material layer 208 of the initial dielectric wall 203 located on the sidewall of the second region II is etched, while the sidewall material layer 208 of the initial dielectric wall 203 located on the sidewall of the first region I is retained. In other embodiments, the sidewall material layer of the initial dielectric wall located on the sidewall of the first region I may also be etched, while the sidewall material layer of the initial dielectric wall located on the sidewall of the second region II is retained.

[0170] Specifically, the sidewall material layer 208 is made of materials including SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the sidewall material layer 208 is made of carbon-doped SiN or oxygen-doped SiN. The material of the sidewall material layer 208 is the same as that of the initial dielectric wall 203, and the sidewall material layer 208 and the initial dielectric wall 203 have good adhesion, which is beneficial to improving the process compatibility of the sidewall material layer 208.

[0171] In this embodiment, the sidewall material layer 208 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the sidewall material layer 208, enabling it to conformally cover the second gate structure 207 and the initial dielectric wall 203 exposing the second gate structure 207. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly enhancing the conformal coverage capability of the sidewall material layer 208.

[0172] It should be noted that during the step of forming the sidewall material layer 208, the sidewall material layer 208 should not be too thick or too thin. If the sidewall material layer 208 is too thick, it will require excessive processing time to form the sidewall material layer 208. During the subsequent etching of one lateral end of the initial dielectric wall 203, excessive processing time will be required to remove the sidewall material layer 208 on top of the initial dielectric wall 203 in the second region II, which is not conducive to improving the formation efficiency of the semiconductor structure. In addition, if the sidewall material layer 208 is too thick, it will occupy too much of the area on top of the second gate structure 207 in the first region I, resulting in a smaller contact area between the subsequently formed third gate structure and the second gate structure 207 in the first region, and a correspondingly larger contact resistance. Subsequent etching exposes one lateral end of the initial dielectric wall 203 of the second gate structure 207 and the sidewall material layer 203 on the second gate structure 207 in the second region II, exposing the remaining sidewall material layer 208 and the initial dielectric wall 203 of the second gate structure 207 as a blocking wall. A third gate structure is formed on both sides of the blocking wall, and the blocking wall 209 is used to electrically isolate the third gate structure. If the sidewall material layer 208 is too thin, its effect on increasing the lateral dimension of the blocking wall is not significant, which is not conducive to improving the electrical isolation of the third gate structure on both sides of the blocking wall 209. The third gate structures on both sides of the blocking wall are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the sidewall material layer 208 is 1 nanometer to 5 nanometers.

[0173] refer to Figure 16 and Figure 17 In the step of etching to expose one lateral end of the initial dielectric wall 203 of the second gate structure 207 to form the blocking wall 209, the sidewall material layer 208 on the surface of the second gate structure 207 and the sidewall material layer 208 on one lateral sidewall of the initial dielectric wall 203 are also etched to expose the remaining initial dielectric wall 203 and the sidewall material layer 208 of the second gate structure 207 as the blocking wall 209.

[0174] The step of etching to expose a portion of the thickness of the initial dielectric wall 203 at one lateral end of the second gate structure 207 to form a blocking wall 209 includes: forming a mask layer 213 on the initial dielectric wall 203 and the second gate structure 207, the mask layer 213 exposing one lateral end of the initial dielectric wall 203; etching the initial dielectric wall 203 and sidewall material layer 208 exposed by the mask layer 213, the remaining portion of the initial dielectric wall 203 and sidewall material layer 208 above the second gate structure 207 serving as the blocking wall 209.

[0175] In this embodiment, the mask layer 213 exposes one end of the initial dielectric wall 203 laterally. The mask layer 213 includes an organic material layer 2131, an anti-reflective coating 2132 on the organic material layer 2131, and a photoresist layer 2133 on the anti-reflective coating 2132.

[0176] The method for forming the semiconductor structure further includes: after forming the blocking wall 209, removing the mask layer 213.

[0177] It should be noted that, in this embodiment, the step of forming the blocking wall 209 involves removing the sidewall material layer 208 of the initial dielectric wall 203 located on the sidewall of the second region II. In other embodiments, when a contact plug is subsequently formed to connect with the third gate structure of the first region I, the step of forming the blocking wall may also involve removing the sidewall material layer of the initial dielectric wall located on the sidewall of the first region.

[0178] In this embodiment, after the blocking wall 209 is formed, the sidewall material layer 208 is still located on top of the remaining initial dielectric wall 203. Therefore, the sidewall material layer 208 also plays the role of increasing the height of the blocking wall 209, which can electrically isolate the third gate structure with a larger thickness.

[0179] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; One or more first channel layers are spaced apart on the substrate along the normal direction of the substrate surface; A first gate is located on the substrate, and the first gate completely surrounds the first channel layer; A dielectric wall extends through the first channel layer and the first gate at the junction of the first region and the second region, with its extension direction being lateral, parallel to the substrate surface and perpendicular to the extension direction of the dielectric wall. A blocking wall is located at one end of the top of the dielectric wall laterally, the blocking wall is offset at the top of the dielectric wall, and the projection of the blocking wall on the substrate is located in the projection of the dielectric wall on the substrate; The second gate is located on the side of the first gate and the dielectric wall of the blocking wall, and is exposed on the top of the blocking wall.

2. The semiconductor structure as described in claim 1, characterized in that, The dielectric wall includes a first end and a second end that are laterally opposite each other, and the blocking wall is located at the first end of the dielectric wall in the lateral direction. The semiconductor structure further includes a sidewall material layer located on the sidewall of the blocking wall near the first end of the dielectric wall, and the bottom of the sidewall material layer is in contact with the first gate.

3. The semiconductor structure as described in claim 2, characterized in that, The sidewall material layer is also located on top of the barrier wall.

4. The semiconductor structure as described in claim 2, characterized in that, The lateral dimensions of the sidewall material layer are 1 nanometer to 5 nanometers.

5. The semiconductor structure as described in claim 2, characterized in that, The materials of the sidewall material layer include: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN.

6. The semiconductor structure as described in claim 1 or 2, characterized in that, In a direction perpendicular to the normal to the substrate surface, one lateral sidewall of the blocking wall is flush with one lateral sidewall of the dielectric wall.

7. The semiconductor structure as described in claim 1 or 2, characterized in that, The lateral dimensions of the barrier wall are 14 to 20 nanometers.

8. The semiconductor structure as described in claim 1, characterized in that, The dielectric wall includes a first end and a second end that are laterally opposite each other, and the blocking wall is located at the first end of the dielectric wall in the lateral direction. The semiconductor structure further includes a contact plug located on top of the second gate on the side of the second end opposite to the first end.

9. The semiconductor structure as described in claim 1, characterized in that, The substrate also includes adjacent third and fourth regions; The semiconductor structure includes: one or more second channel layers, which are spaced apart and suspended on the substrate along the normal direction of the substrate surface, and the first gate also completely surrounds the second channel layers; The dielectric wall extends through the second channel layer and the first gate at the junction of the third and fourth regions.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including adjacent first and second regions, the substrate comprising: a substrate; one or more first channel layers, spaced apart and suspended on the substrate along the normal direction of the substrate surface; a first gate structure completely surrounding the first channel layers; and an initial dielectric wall penetrating the first channel layer and the first gate structure at the junction of the first and second regions; The first gate structure with a partial thickness is etched to form a second gate structure, the second gate structure completely surrounds the first channel layer and exposes a portion of the sidewall of the initial dielectric wall; With the extension direction parallel to the substrate surface and perpendicular to the initial dielectric wall as the lateral direction, one end of the initial dielectric wall of the second gate structure is etched to expose the remaining initial dielectric wall of the second gate structure as a blocking wall, and the remaining initial dielectric wall in the second gate structure as a dielectric wall. A third gate structure is formed on the second gate structure, the third gate structure being exposed at the top of the blocking wall.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the semiconductor structure further includes: etching a portion of the thickness of the first gate structure, forming the second gate structure, and before etching one lateral end of the initial dielectric wall exposing the second gate structure, conformally covering a sidewall material layer on the initial dielectric wall and the second gate structure exposed by the initial dielectric wall. In the step of etching to expose one lateral end of the initial dielectric wall of the second gate structure to form a blocking wall, the sidewall material layer on the surface of the second gate structure and the sidewall material layer on one lateral sidewall of the initial dielectric wall are also etched to expose the remaining initial dielectric wall and the sidewall material layer of the second gate structure as the blocking wall.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The sidewall material layer is formed using atomic layer deposition or chemical vapor deposition.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the sidewall material layer, the thickness of the sidewall material layer is 1 nanometer to 5 nanometers.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The materials of the sidewall material layer include: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN.

15. The method for forming a semiconductor structure as described in claim 10 or 11, characterized in that, The step of etching to expose one lateral end of the initial dielectric wall of the second gate structure to form a blocking wall includes: A mask layer is formed on the initial dielectric wall and the second gate structure, the mask layer exposing one lateral end of the initial dielectric wall; The initial dielectric wall is etched using the mask layer as a mask to expose the remaining initial dielectric wall of the second gate structure as the blocking wall; The method for forming the semiconductor structure further includes: after forming the barrier wall, removing the mask layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, Using the mask layer as a mask, an anisotropic dry etching process is used to etch and expose one lateral end of the initial dielectric wall of the second gate structure, exposing the remaining initial dielectric wall of the second gate structure as the blocking wall.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of forming the blocking wall further includes: after etching to expose one lateral end of the initial dielectric wall of the second gate structure, performing a lateral trimming process on the sidewall of the exposed initial dielectric wall of the second gate structure to expose the remaining initial dielectric wall of the second gate structure as the blocking wall.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The sidewalls of the initial dielectric wall exposed by the second gate structure are laterally trimmed using an isotropic dry etching process.

19. The method for forming a semiconductor structure as described in claim 10 or 11, characterized in that, In the step of forming the barrier wall, the lateral dimension of the barrier wall is 14 nanometers to 20 nanometers.

20. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of forming a third gate structure on the second gate structure includes: A gate material layer is formed in the second gate structure and the blocking wall; Remove the gate material layer that extends above the barrier wall, and the remaining gate material layer serves as the third gate structure.

21. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming the dielectric wall, the dielectric wall includes a first end and a second end that are laterally opposite, and the blocking wall is located at the first end of the dielectric wall in the lateral direction; The method for forming the semiconductor structure further includes: forming a contact plug on the top of the third gate structure on the side of the second end opposite to the first end.

22. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, the substrate further includes adjacent third and fourth regions; The substrates of the third and fourth regions include: a substrate; one or more second channel layers, spaced apart and suspended on the substrate along the normal direction of the substrate surface; a first gate structure, completely surrounding the second channel layers; and an initial dielectric wall penetrating the second channel layer and the first gate structure at the junction of the third and fourth regions. In the step of etching to expose one lateral end of the initial dielectric wall of the second gate structure to form a blocking wall, the initial dielectric wall exposing the second gate structure in the third and fourth regions is removed.

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