Semiconductor storage unit structure, semiconductor memory and its preparation method and application

Abstract

The present invention relates to a semiconductor memory cell structure, a semiconductor memory and a preparation method and application thereof. The semiconductor memory cell structure comprises: a substrate, a first transistor layer, an isolation layer and a second transistor layer; the first transistor layer comprises: a first stacking structure formed by stacking a first source, a first channel and a first drain from bottom to top, and a first gate located on the side wall of the first stacking structure; the second transistor layer comprises: a second stacking structure formed by stacking a second drain, a second channel and a second source from bottom to top, and a second gate located on the side wall of the second stacking structure, at least a part of the side wall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with improved structure, which has the advantages of vertical stacking integration, high integration, low leakage, short refresh time, etc., and has significant advantages over the existing 2T0C type DRAM.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor memory, and in particular to a semiconductor memory unit structure, a semiconductor memory and a preparation method and application thereof. Background Art

[0002] A higher integration of semiconductor devices may be desirable to meet consumer demand for excellent performance and low prices. For semiconductor devices, since their integration can be an important factor in determining product prices, it is particularly desirable to increase the integration. For two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by the unit memory cell, the integration is greatly affected by the level of fine pattern forming technology. However, extremely expensive process equipment for improving pattern fineness sets practical limitations on improving the integration of two-dimensional or planar semiconductor devices. In order to overcome this limitation, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell has been proposed. 3D integration is a breakthrough in DRAM scaling, but the demand for storage capacitors limits the scalability of 3D DRAM cells. Summary of the invention

[0003] The main purpose of the present invention is to provide a semiconductor storage unit structure and a semiconductor memory composed of the same, which is a 2T0C type DRAM unit with structural improvement, and has the advantages of vertical stacking integration, high integration, low leakage, short refresh time, etc., and has significant advantages over the existing 2T0C type DRAM.

[0004] Another object of the present invention is to provide a method for preparing a semiconductor memory cell structure, which provides a feasible and industrially mass-produced process for the above-mentioned semiconductor memory cell structure, and the prepared stacked structure has good mechanical stability and electrical stability.

[0005] In order to achieve the above objectives, the present invention provides the following technical solutions.

[0006] A first aspect of the present invention provides a semiconductor memory cell structure, comprising: a substrate, and a first transistor layer, an isolation layer, and a second transistor layer vertically stacked from bottom to top on the substrate;

[0007] The first transistor layer comprises: a first stacked structure formed by stacking a first source, a first channel, and a first drain from bottom to top, and a first gate located on a sidewall of the first stacked structure; and the first gate is isolated from the sidewall of the first stacked structure and from the substrate by a gate dielectric layer;

[0008] The second transistor layer includes: a second stacked structure formed by a second drain, a second channel, and a second source stacked from bottom to top, and a second gate located on the side wall of the second stacked structure, and the second gate is isolated from the side wall of the second stacked structure by a gate dielectric layer, at least a portion of the side wall of the second drain is in direct contact with the first gate, and the first gate and the second gate are isolated in the vertical direction by a dielectric material.

[0009] A second aspect of the present invention provides a semiconductor memory comprising a plurality of the semiconductor memory cell structures described above, wherein the plurality of semiconductor memory cell structures are electrically connected.

[0010] A third aspect of the present invention provides a method for preparing a semiconductor memory cell structure, which comprises the following steps:

[0011] providing a substrate;

[0012] Vertically stacking a first electrode material layer, a first sacrificial layer, a second electrode material layer, a second sacrificial layer, a third electrode material layer, a third sacrificial layer, a fourth electrode material layer, and a mask layer in sequence on the substrate;

[0013] patterning the mask layer to form an array containing a plurality of mask units;

[0014] forming a mask sidewall on a sidewall of each mask unit;

[0015] Etching and removing the structure not blocked by the mask unit and its sidewalls until the substrate is exposed, thereby forming a stacked structure on the substrate;

[0016] Then, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are etched in one step or in stages, so that a portion of the three layers are etched from the sidewall direction, thereby forming a plurality of grooves on the sidewall of the stacked structure;

[0017] Filling a dielectric material in the groove on the side wall of the second sacrificial layer to form an isolation layer for upper and lower devices, wherein the upper device is located above the isolation layer and the lower device is located below the isolation layer;

[0018] Filling the grooves on the sidewalls of the first sacrificial layer and the third sacrificial layer with channel materials to form a first channel layer and a second channel layer respectively;

[0019] Etching and removing the mask unit and the stacked structure covered by it until the substrate is exposed, and retaining the structure covered by the mask sidewall, thereby dividing it into two structural units covered by the mask sidewall;

[0020] Then remove the remaining first sacrificial layer, second sacrificial layer, third sacrificial layer and mask sidewalls;

[0021] forming a gate dielectric layer on the sidewall of each of the structural units;

[0022] Etching the gate dielectric layer to expose at least a portion of the sidewall of the third electrode material layer in each structural unit;

[0023] Then, a first gate layer is formed on the first electrode material layer, the first channel layer, the sidewalls of the second electrode material layer and all upper surfaces of the structural unit, and the first gate layer is in contact with the exposed sidewalls of the third electrode material layer;

[0024] forming one or more dielectric films on the upper surface of the first gate layer;

[0025] A second gate layer is formed on the dielectric film, wherein the second gate layer covers the sidewall of the second channel layer.

[0026] A fourth aspect of the present invention provides the above-mentioned semiconductor memory cell structure, semiconductor memory, or the use of the structure prepared by the above-mentioned preparation method in an electronic device.

[0027] Compared with the prior art, the present invention achieves the following technical effects:

[0028] (1) A new structure of a DRAM array with two vertically stacked devices, the 2T0C type, was developed, which eliminates the capacitor and has the advantages of high integration, low leakage, and short refresh time;

[0029] (2) The semiconductor memory cell structure of the present invention is applicable to a wide range of channel materials, which may be silicon, or large Eg bandgap materials or IGZO thin film transistor materials, etc.;

[0030] (3) A method for preparing the semiconductor memory cell structure has also been developed, which provides industrial feasibility for the promotion of the product, and the steps involved can all be carried out under conventional conditions, with low process difficulty;

[0031] (4) The word line and bit line arrangement of the device composed of the above-mentioned semiconductor memory cell structure and the implementation method of metal interconnection are also studied. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the following detailed description of the preferred embodiment.The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the invention.

[0033] Figure 1 A top view of the DRAM structure provided by the present invention;

[0034] Figure 2 A cross-sectional view of a DRAM structure provided by the present invention;

[0035] Figure 3 A schematic diagram of the storage principle of the DRAM structure of the present invention;

[0036] Figures 4 to 41 This is a schematic diagram of the structure obtained in each step of the preparation method provided by the present invention. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0038] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0039] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0040] The 2T0C DRAM unit in the prior art generally uses two horizontal channel TFTs connected on the same plane, which occupies a large area and is not conducive to improving the integration density.

[0041] To this end, the present invention provides Figure 1 and 2 The dual-device capacitor-free DRAM cell structure shown can be functionally divided into three regions from bottom to top: substrate 1, first transistor layer A and second transistor layer B, as follows.

[0042] The substrate 1 can be any substrate material known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide or germanium-on-insulator, etc. The corresponding top semiconductor material is silicon, germanium, silicon germanium or gallium arsenide, etc. At the same time, the semiconductor layer on the substrate determines the doping type according to the device type to form a P well (for nMOSFET) or an n well (for pMOSFET).

[0043] The isolation layer 5a is used as a boundary, and the first transistor layer A is located below. The transistor layer adopts a vertically stacked structure, which includes a first stacked structure formed by stacking a first source 2a, a first channel 10a, and a first drain 4a from bottom to top, and a first gate 17a located on the side wall of the first stacked structure. The first gate 17a is isolated from the side wall of the first stacked structure and from the substrate 1 by a gate dielectric layer 13.

[0044] In the first transistor layer A, the source, channel and drain are stacked vertically, and the gate is located at the side of the stack. This structure realizes the function of the readout tube. In addition, in order to save the capacitor, the first gate 17a in the first transistor layer is used as a storage node and is in direct contact with the second drain 6a of the second transistor layer, such as Figure 2 shown.

[0045] The second transistor layer B includes: a second stacked structure formed by stacking the second drain 6a, the second channel 10b, and the second source 8a from bottom to top, and a second gate 20 located on the side wall of the second stacked structure. The second gate 20 is isolated from the side wall of the second stacked structure by the gate dielectric layer 13, at least a portion of the side wall of the second drain 6a is in direct contact with the first gate 17a, and the first gate 17a and the second gate 20 are isolated in the vertical direction by the dielectric material. The second transistor layer can realize the function of a write tube.

[0046] In the first transistor layer A and the second transistor layer B, the channel is located between the source and the drain. In order to further reduce the leakage current, the channel preferably has a smaller width, that is, a "C"-shaped channel is designed between the source and the drain. The specific structure can be:

[0047] Two opposite side walls of the first stack structure are respectively in the shape of a groove, and the first channel 10a is located in the groove;

[0048] and / or,

[0049] Two opposite side walls of the second stack structure are respectively in the shape of a groove, and the second channel 10b is located in the groove.

[0050] In addition, in the vertical direction, the isolation between the first gate 17a and the substrate 1, and the isolation between the first gate 17a and the second gate 20 are preferably isolated by multilayer dielectric materials, such as a combination of oxide, nitride, and high-K materials, preferably including at least silicon oxide film and high-K dielectric film.

[0051] like Figure 2 The DRAM cell structure shown has the following two outstanding features:

[0052] First, double-layer transistors are stacked vertically and connected with zero capacitance, which solves the problem of large area occupation of planar channel 2T0C DRAM units and improves integration density.

[0053] Secondly, the channel is a concave C-shape when viewed horizontally, which can greatly reduce leakage problems.

[0054] The working principle of the DRAM cell structure described above in the present invention is as follows: Figure 3 As shown (the position of the transistors in the figure is only for the convenience of illustrating the working principle and does not represent the actual position layout), the first transistor layer A is used as a reading tube, and the second transistor layer B is used as a writing tube. The gate of the former is in direct contact with the drain of the latter. The charge in the gate capacitance of the reading tube is changed by the writing tube, thereby affecting the resistance state between the source and drain of the reading tube, thereby realizing the distinction between "0" and "1". The specific principle is as follows.

[0055] In the process of writing "1", a positive voltage (greater than the threshold voltage Vth) is applied to the gate electrode of the read tube (i.e. the write word line WWL) to turn on the write tube, and a positive voltage is applied to the source electrode of the write tube (i.e. the write bit line WBL) to inject charge into the gate capacitor of the read tube (i.e. the storage node). After the charge injection, the gate and source voltages of the write tube are removed to save the "1" state;

[0056] In the process of reading "1", a reading voltage is applied to the drain of the reading tube. Since there is a certain charge in the gate capacitor, the reading tube is in a lower resistance state and obtains a larger current. After amplification and recognition by the peripheral circuit, the reading process of "1" is completed;

[0057] In the process of writing "0", a positive voltage (greater than the threshold voltage Vth) is applied to the gate electrode of the read tube (i.e. the write word line WWL) to turn on the write tube, and a negative voltage is applied to the source electrode of the write tube (i.e. the write bit line WBL) to extract charge from the gate capacitor of the read tube (i.e. the storage node). After the charge is extracted, the gate and source voltages of the write tube are removed to save the "0" state;

[0058] In the process of reading "0", a reading voltage is applied to the drain of the reading tube. Since there is no charge in the gate capacitance, the reading tube is in a higher resistance state and obtains a smaller current. The reading "0" process is then completed after amplification and identification by the peripheral circuit.

[0059] In terms of material selection for the above unit structure, each layer can be made of any material that can achieve its basic function. However, in order to further improve the electrical performance and use effect of the memory, each layer has its preferred material.

[0060] For example, the first channel 10a and the second channel 10b may be made of IGZO material. Since the off-state leakage of the IGZO thin film transistor is very low, the information of the storage node can be retained for a long time.

[0061] The gate dielectric layer acts as an insulator between the gate and the channel. It is preferred to select a material with a wide bandgap and a high dielectric constant, or a material suitable for making extremely small devices, such as HfO 2 .

[0062] The first source 2a, the first drain 4a, the second source 8a, the second drain 6a, the first gate 17a and the second gate 20 are electrodes to be connected to the power supply, and preferably use metal materials with good conductive properties or doped semiconductor materials. Considering the feasibility of the process, the first gate 17a and the second gate 20 preferably use metal gates, which can be formed by sputtering, including but not limited to typical titanium nitride, tungsten, etc. In addition, considering the rapidity and stability of current transmission between electrodes, the two gates are preferably made of the same material. The first source 2a, the first drain 4a, the second source 8a, and the second drain 6a can be made of typical materials such as doped silicon, and it is also preferred to use the same material.

[0063] As for the isolation layer 5a for isolating the upper and lower devices, silicon oxide or silicon nitride is preferably used, which is convenient for large-area deposition, and silicon nitride is more preferred. Silicon nitride film is an amorphous film, which has strong sodium and water vapor resistance, can play a good passivation and protection role, and silicon nitride itself has good chemical stability, strong acid and alkali resistance, strong masking ability, and high dielectric constant.

[0064] After the above capacitor-free DRAM cell structure is used to form a memory, the arrangement of each cell (i.e., word line and bit line array) and the metal interconnection structure can be adaptively adjusted or determined by the process. There are many methods for preparing the above capacitor-free DRAM cell structure, and the process flow or the formation sequence of each structure of different methods are different. In this regard, the present invention provides one of the feasible methods, which has the characteristics of conventional 3D integrated processing, can more simply realize the arrangement of word lines and bit lines, and is combined with Figures 4 to 41 , the specific process is as follows.

[0065] First, in step S1, a first electrode material layer 2, a first sacrificial layer 3, a second electrode material layer 4, a second sacrificial layer 5, a third electrode material layer 6, a third sacrificial layer 7, a fourth electrode material layer 8, and a mask layer 9 are vertically stacked in sequence on a substrate 1 to obtain a Figure 4 The top view is shown in Figure 5 ( Figure 5 The arrow in the middle indicates Figure 4 direction of section).

[0066] Among them, the first sacrificial layer 3, the second sacrificial layer 5 and the third sacrificial layer 7 are pre-occupied in order to form the channel of the two devices and the isolation layer between the two devices later, so it is necessary to select a material with a large difference in etching performance from the electrode material, such as germanium silicon. At the same time, considering that the first sacrificial layer 3 and the third sacrificial layer 7 are located at the location of the channel, the second sacrificial layer 5 is the location of the isolation layer, and the widths required for the channel and the isolation layer are usually different, therefore, the first sacrificial layer 3 and the third sacrificial layer 7 are made of the same or similar materials, and the second sacrificial layer 5 is made of a material that is very different from the first two. For example, the first sacrificial layer 3, the second sacrificial layer 5 and the third sacrificial layer 7 are germanium silicon layers with different germanium contents, and the molar contents of germanium are: ≤15%, ≥30%, ≤15% respectively.

[0067] The four electrode layers, namely the first electrode material layer 2, the second electrode material layer 4, the third electrode material layer 6 and the fourth electrode material layer 8, are used to form the source and drain of the lower transistor and the drain and source of the upper transistor, respectively. The material selection range of these electrodes is as described above. The three sacrificial layers also support the four electrode layers.

[0068] The mask layer 9 is used to pattern the electrodes of each layer and to protect the top electrode during the subsequent lateral etching. A hard mask (HM) such as TiN, SiN, SiO 2 , amorphous silicon, etc., more preferably a silicon oxide layer 901, an amorphous silicon layer (α-Si) 902, and a silicon oxide layer 903 are stacked from bottom to top (such as Figure 4 example).

[0069] According to the material types of the above four electrode layers, three sacrificial layers and mask layer, an appropriate formation process is selected, which usually includes but is not limited to in-situ oxidation, PECVD, ALCVD, epitaxial growth, sputtering, etc.

[0070] Next, in step S2, the mask layer 9 is patterned to form an array containing a plurality of mask units, so as to obtain Figure 6 The top view morphology shown in the figure (only 5 parallel units are shown in the figure, but the actual array arrangement shape and number are not limited), the cross-sectional morphology is as follows Figure 7 (The cross-sectional view shows Figure 6 of one of the units).

[0071] The patterning in this step is usually achieved by combining photolithography and etching, and the etching can be determined as one-step or multi-step according to the etchant or etching method (dry etching, wet etching, etc.).

[0072] Then, in step S3, a mask sidewall 904 is formed on the sidewall of each mask unit. The mask sidewall 904 is usually made of silicon oxide, silicon nitride, etc., with a sidewall width of 30-100 nm, and stops on the surface of the fourth electrode material layer 8, so as to obtain Figure 8 The morphology shown in the figure (the figure takes the silicon oxide sidewall as an example). The formation means include but are not limited to in-situ oxidation method, PECVD, ALCVD, CVD, etc.

[0073] Next, in step S4, the structures not blocked by the mask unit and its sidewalls (ie, the stacked structures outside the array) are removed by etching until the substrate is exposed, thereby forming a stacked structure on the substrate. Fig. 9 and 10 As shown ( Fig.10 is a top view, Fig. 9 for Fig.10 Since this step etches the multilayer material, different etching methods and etchants can be used for step-by-step etching, and the present invention does not impose any particular limitation on this.

[0074] Then in step S5, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are etched in one step or in stages, so that all three layers are partially etched from the side wall direction, so that the side walls of the stacked structure form multiple grooves 701, 501, 301, and the depth of the grooves can be controlled in the range of 10~100nm. In this step of etching, the etching is performed laterally along the side walls, and the etching must be selective. Taking the example of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer using germanium silicon layers with different germanium contents (the molar contents of germanium are: ≤15%, ≥30%, ≤15% respectively), the etching can be completed simultaneously. And because the second sacrificial layer has a high germanium content and a high etching selectivity, the depth of the groove 501 formed on its side wall is deeper than the grooves 301, 701 of the other two sacrificial layers, such as Fig.11 The structure shown.

[0075] Step S6, filling the groove 501 on the sidewall of the second sacrificial layer with dielectric material to form an isolation layer for upper and lower devices, with the upper device being above the isolation layer and the lower device being below the isolation layer. As mentioned above, the isolation layer is preferably made of silicon nitride.

[0076] Since the dielectric material needs to be filled into the groove with the transverse opening, the situation is relatively complicated, so it is usually necessary to carry out in multiple steps. For example, the following method can be adopted.

[0077] Step S601, deposit dielectric materials such as silicon nitride to cover all outer surfaces, and the resulting structure is as follows Fig.12 shown.

[0078] Step S602, etching and removing the dielectric material located on all top surfaces and side walls, and the obtained structure is as follows: Fig.13shown.

[0079] Step S603, completely remove the dielectric material in the groove 301 on the side wall of the first sacrificial layer 3 and the groove 701 on the side wall of the third sacrificial layer 7. At this time, dielectric material still remains in the groove on the side wall of the second sacrificial layer 5, which is the isolation layer 5a. Fig.14 shown.

[0080] Then, step S7 is performed to fill the grooves on the sidewalls of the first sacrificial layer and the sidewalls of the third sacrificial layer with channel materials to form a first channel layer and a second channel layer respectively.

[0081] This step has the same situation as step S6, that is, dielectric material is filled in the groove with a transverse opening, and the situation is more complicated. Another problem is that the depth of the groove on the side wall of the first sacrificial layer and the groove on the side wall of the third sacrificial layer may not be deep enough to support the channel material or meet the width requirement of the channel. For the above two problems, the present invention provides the following feasible method. This method is applicable to the situation where the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer are all epitaxial semiconductors (such as epitaxially doped silicon), the three sacrificial layers are all formed by epitaxy, and the top of the mask layer is silicon oxide.

[0082] Step S701, selectively and dryly etch the first sacrificial layer and the third sacrificial layer laterally, and accurately control the depth of the germanium silicon lateral etching to make the grooves 301 and 701 deeper, such as Fig.15 shown.

[0083] Step S702, taking silicon as the channel material and epitaxially doped silicon as the electrode material as an example. Since this step and the four electrode material layers are all formed by epitaxy and are all silicon, the crystal growth direction determines that the epitaxially grown channel material 10 in this step is only distributed on the sidewalls, such as Fig.16 As shown (top view structure as shown Fig.17 ), and the isolation layer 5a at the second sacrificial layer is made of materials such as silicon nitride, and silicon material cannot be epitaxially grown here.

[0084] In addition, since the side walls of the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer in step S702 are also epitaxially grown with the channel material layer, in order to avoid greater leakage problems, the channel materials on the side walls of these four electrode material layers also need to be processed, for example, by converting them into doped materials or removing them, which is the following step S703.

[0085] Step S703, high temperature annealing is performed on the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer (high temperature annealing can transform the channel material on the side wall of the electrode material layer into a doping material, and since it is not easily doped by high temperature annealing in the vertical direction, the channel material on the side wall of the first sacrificial layer and the third sacrificial layer is not doped), or the epitaxial channel material on the side wall of the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer is removed. The latter means of this step can be performed immediately after step S702, but the former means can be completed in the subsequent process, that is, it does not need to be performed immediately after step S702 (this is also considering that the silicon oxide protection electrode structure needs to be filled during high temperature annealing).

[0086] If the channel is made of silicon carbide, gallium nitride, IGZO material or the like, it is different from the epitaxial silicon electrode, so all the outer surfaces are covered with the channel material, forming a Fig.18 Then, the channel material in the non-channel region (including all top surfaces, the side walls of the four electrode layers, the side walls of the isolation layer at the second sacrificial layer, and the side walls of the mask sidewalls) is selectively etched away to obtain the structure shown in FIG. Fig.19 This selective etching method can be carried out by the following process: firstly, a shielding layer such as silicon nitride is formed at the grooves of the first and second sacrificial layers for protection, then the channel material in the non-channel region is removed, and then the shielding layer such as silicon nitride is removed (the accompanying figure is not repeated).

[0087] The following steps are performed using silicon channel as an example.

[0088] Then, step S8 is performed to etch and remove the mask unit and the stacked structure covered by it until the substrate is exposed, and the structure covered by the mask sidewall is retained, thereby dividing it into two structural units F ( Fig. 20 as shown).

[0089] Before performing this step, it is necessary to deposit a layer of oxide protective film such as silicon oxide, as follows (taking silicon oxide protective film as an example).

[0090] Step S801 , depositing a layer of silicon oxide protection film 11 .

[0091] Step S802, removing the top silicon oxide layer by polishing, etching or other means, stopping at the amorphous silicon layer.

[0092] Step S803: removing the amorphous silicon layer by wet etching with a TMAH solution or other etching methods.

[0093] Step S804, dry-etching the stacked structure at the window formed after removing the amorphous silicon layer until the substrate is exposed, to obtain Fig. 20 and21 The structure shown ( Fig.21 Arrow direction Fig. 20 direction of section).

[0094] Next, step S9 is performed to remove the remaining first sacrificial layer, the second sacrificial layer and the third sacrificial layer (since the mask sidewalls in the example here are made of silicon oxide, they may not be removed temporarily), and the following is obtained: Fig. 22 This step can be completed by etching in steps or in one step.

[0095] Step S10 is performed to form a gate dielectric layer on the sidewalls and all upper surfaces of each of the structural units. When performing this step, it is necessary to ensure that the sidewalls of the four electrode layers, namely the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer, and the sidewalls of the first channel layer and the second channel layer are exposed. When the gate dielectric layer is formed in this step, the gate dielectric layer covers all exposed outer surfaces (including the sidewalls).

[0096] If there are no other processes in step S9 and step S10, the Fig. 22 As shown, a silicon oxide film is deposited on the exposed substrate surface, and then the silicon oxide on the top and sidewalls is etched until a silicon oxide film with a smaller thickness is formed at the bottom to serve as isolation.

[0097] In actual device production, since each storage unit is manufactured synchronously, there are other necessary processes between step S9 and step S10, such as patterning of upper layer devices, contact hole manufacturing of lower layer devices, trench isolation, etc., such as the following steps.

[0098] Step a1, obtained in step S9 Fig. 22 Based on the above, silicon oxide 12 is deposited on a large area by using a HARP process to cover all stacked structures, and the following is obtained: Fig.23 After this step, it is suitable to carry out the high temperature annealing process described in step S703 (such as Fig.23 As shown, the material of the channel region is separated from the channel material region of the sidewalls of other electrode materials, thereby forming a first channel 10a and a second channel 10b).

[0099] Step a2, etching silicon oxide 12, stopping between the upper and lower devices, to obtain Fig.24 The structure shown.

[0100] Step a3, patterning the upper layer device according to the predetermined layout of the upper layer device, for example, according to Fig.25 The schematic top view of the layout, the horizontal strip is the upper device area to be etched away, and the cross-sectional structure at the etched location is as follows: Fig.26 The purpose of this step is to cut the upper device into multiple independent units.

[0101] Step a4, continue etching the silicon oxide, leaving only the thinner isolation layer 12a at the bottom, to obtain Fig. 27 The structure shown ( Fig. 27 The cross-section view is taken at the area where both upper and lower devices exist).

[0102] Step a5, according to the layout designed in the top view direction 28, the ring device at the end is cut off on both sides, and the cross-sectional structure of the cut-off point after cutting is as follows Fig.29 .

[0103] Step a6, making contact holes for the lower layer devices. First, select a location close to the edge of the substrate (e.g. Fig.30 The area marked by the second horizontal strip in the top view C) The etching of the stacked structure stops at the first electrode material layer 2, which serves as the landing pad for the bit line contact hole of the read tube (lower layer device). The cross-sectional structure here is as follows Fig.31 Then at the other edge (for example, Fig.32 The etching of the stacked structure stops at the second electrode material layer 4, which serves as a landing pad for the read tube word line contact hole. The cross-sectional structure here is as follows Fig.33 .

[0104] After step a6, step S10 may be performed, that is, forming a gate dielectric layer 13 on the sidewalls and all upper surfaces of each of the structural units. Fig.34 shown.

[0105] Continuing with step S11 , the gate dielectric layer 13 is etched to expose at least a portion of the sidewall of the third electrode material layer in each structural unit.

[0106] This step is to etch a window on the drain sidewall of the upper device to contact the gate of the lower device, which can be achieved step by step in the following manner.

[0107] Step S1101 , depositing a silicon oxide layer 14 and a bottom anti-reflection coating 15 (such as commonly used silicon carbide) in sequence, and the bottom anti-reflection coating is located at a position having the same height as the third electrode material layer.

[0108] Step S1102, forming a silicon oxide sidewall 16 on the sidewall of the upper device above the bottom anti-reflection coating 15, the structure of which is as follows: Fig.35 shown.

[0109] Step S1103, removing the bottom anti-reflection coating 15, the structure is as follows Fig.36 shown.

[0110] Step S1104, etching the gate dielectric layer, thereby exposing the sidewall of the third electrode material layer to form an exposed portion 6b;

[0111] Step S1105, finally removing the silicon oxide layer and the silicon oxide sidewalls, obtaining Fig.37 The structure shown shows the exposed sidewall 6b of the third electrode material layer.

[0112] Continuing with step S12, a first gate layer is formed on the side walls of the first electrode material layer, the first channel layer, and the second electrode material layer, and the first gate layer is in contact with the exposed side walls of the third electrode material layer.

[0113] This step includes:

[0114] Step S1201, sputtering or depositing the first gate layer material 17 over a large area until its height is higher than the exposed sidewall of the third electrode material layer, to obtain Fig.38 The structure shown.

[0115] Step S1202, patterning the gate material 17 formed in the previous step (for example, generally including lateral and longitudinal etching, which is omitted in the figure) to match the arrangement of the upper and lower layer devices, and obtaining the following: Fig.39 The structure shown (this figure is only a cross-sectional view of a certain position, and the cross-sectional views of some positions can only show the substrate covered by the gate dielectric), obtains the first gate 17a.

[0116] Continuing to step S13, one or more dielectric films are formed on the upper surface of the first gate 17a, for example, the dielectric film may be Fig.40 The silicon oxide film 18 and the high-K dielectric film 19 are shown.

[0117] Continuing with step S14 , a second gate layer is formed on the high-K dielectric film 19 , wherein the second gate layer covers the sidewall of the second channel layer, and the second gate layer is patterned.

[0118] In the final step S15, silicon oxide 21 is filled, the surface is smoothed, and a contact hole 22 for the source of the upper device is formed by etching. The final structure is as follows: Fig.41 shown.

[0119] After the above steps S1 to S15, metal interconnection of each electrode is performed, and finally a DRAM memory without capacitors is formed with upper and lower layers stacked. Figure 1 The layout morphology of different structures in the top view of the device is shown.

[0120] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor memory cell structure, It is characterized in that include: A substrate, and a first transistor layer, an isolation layer, and a second transistor layer vertically stacked from bottom to top on the substrate; The first transistor layer comprises: a first stacked structure formed by stacking a first source, a first channel, and a first drain from bottom to top, and a first gate located on a sidewall of the first stacked structure; and the first gate is isolated from the sidewall of the first stacked structure and from the substrate by a gate dielectric layer; The second transistor layer comprises: a second stacked structure formed by stacking a second drain, a second channel, and a second source from bottom to top, and a second gate located on a sidewall of the second stacked structure, wherein the second gate is isolated from the sidewall of the second stacked structure by a gate dielectric layer, at least a portion of the sidewall of the second drain is in direct contact with the first gate, and the first gate and the second gate are isolated in a vertical direction by a dielectric material; In the first transistor layer, two opposite side walls of the first stacked structure are respectively in the shape of a groove, and the first channel is located in the groove; and / or, In the second transistor layer, two opposite side walls of the second stacked structure are respectively in the shape of a groove, and the second channel is located in the groove.

2. The semiconductor memory cell structure according to claim 1, It is characterized in that In the vertical direction, the first gate and the second gate are isolated from each other by multiple layers of dielectric materials.

3. The semiconductor memory cell structure according to claim 1, It is characterized in that In the vertical direction, the first gate and the second gate are isolated from each other by a stacked silicon oxide film and a high-K dielectric film.

4. The semiconductor memory cell structure according to claim 1, It is characterized in that The first gate layer is isolated from the substrate by multiple layers of dielectric material.

5. The semiconductor memory cell structure according to claim 1, It is characterized in that The first gate layer is isolated from the substrate by a stacked silicon oxide film and a high-K dielectric film.

6. The semiconductor memory cell structure according to any one of claims 1 to 5, It is characterized in that The materials of the first source, the first drain, the second source and the second drain are doped silicon, and / or, The materials of the first gate and the second gate are independently titanium nitride, tungsten, or a mixture of the two. and / or, The gate dielectric is hafnium oxide; and / or, The materials of the first channel and the second channel are independently at least one of silicon, silicon carbide, gallium nitride, and IGZO materials.

7. A semiconductor memory, It is characterized in that The invention comprises a plurality of semiconductor memory cell structures according to any one of claims 1 to 6, wherein the plurality of semiconductor memory cell structures are electrically connected.

8. A method for preparing a semiconductor memory cell structure, It is characterized in that The following steps are involved: providing a substrate; Vertically stacking a first electrode material layer, a first sacrificial layer, a second electrode material layer, a second sacrificial layer, a third electrode material layer, a third sacrificial layer, a fourth electrode material layer, and a mask layer in sequence on the substrate; patterning the mask layer to form an array containing a plurality of mask units; forming a mask sidewall on a sidewall of each mask unit; Etching and removing the structure not blocked by the mask unit and its sidewalls until the substrate is exposed, thereby forming a stacked structure on the substrate; Then, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are etched in one step or in stages, so that a portion of the three layers are etched from the sidewall direction, thereby forming a plurality of grooves on the sidewall of the stacked structure; Filling a dielectric material in the groove on the side wall of the second sacrificial layer to form an isolation layer for upper and lower devices, wherein the upper device is located above the isolation layer and the lower device is located below the isolation layer; Filling the grooves on the sidewalls of the first sacrificial layer and the third sacrificial layer with channel materials to form a first channel layer and a second channel layer respectively; Etching and removing the mask unit and the stacked structure covered by it until the substrate is exposed, and retaining the structure covered by the mask sidewall, thereby dividing it into two structural units covered by the mask sidewall; Then remove the remaining first sacrificial layer, the second sacrificial layer and the third sacrificial layer and the optional mask spacer; forming a gate dielectric layer on the sidewall of each of the structural units; Etching the gate dielectric layer to expose at least a portion of the sidewall of the third electrode material layer in each structural unit; Then, a first gate layer is formed on the first electrode material layer, the first channel layer, the sidewalls of the second electrode material layer and all upper surfaces of the structural unit, and the first gate layer is in contact with the exposed sidewalls of the third electrode material layer; forming one or more dielectric films on the upper surface of the first gate layer; A second gate layer is formed on the dielectric film, wherein the second gate layer covers the sidewall of the second channel layer.

9. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that The first sacrificial layer, the second sacrificial layer and the third sacrificial layer are germanium silicon layers with different germanium contents, and the molar contents of germanium are: ≤15%, ≥30%, and ≤15%, respectively.

10. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that The mask layer includes a silicon oxide layer, an amorphous silicon layer, and a silicon oxide layer stacked from bottom to top.

11. The method for preparing a semiconductor memory cell structure according to claim 10, It is characterized in that The mask sidewalls are made of silicon oxide or silicon nitride.

12. The method for preparing a semiconductor memory cell structure according to claim 9, It is characterized in that The first sacrificial layer, the second sacrificial layer and the third sacrificial layer are simultaneously etched by a selective etching method to form the plurality of grooves.

13. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that The method of forming the isolation layer is: Depositing dielectric material to cover all exterior surfaces; Then, the dielectric material on all top surfaces and side walls is removed by etching, so that the dielectric material in the groove on the side wall of the first sacrificial layer and the groove on the side wall of the third sacrificial layer are completely removed, and the dielectric material still remains in the groove on the side wall of the second sacrificial layer, which is the isolation layer.

14. The method for preparing a semiconductor memory cell structure according to claim 8 or 13, It is characterized in that Before filling the channel material, the method further comprises: The first sacrificial layer and the third sacrificial layer are laterally etched to increase the depth of the grooves on their side walls.

15. The method for preparing a semiconductor memory cell structure according to claim 11, It is characterized in that The first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer are all epitaxially doped silicon, the channel material is at least one of silicon, silicon carbide, gallium nitride, and IGZO materials, and the mask layer includes a silicon oxide layer located on the top.

16. The method for preparing a semiconductor memory cell structure according to claim 15, It is characterized in that The channel material is silicon, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer are all formed by epitaxy, and the method of filling the channel material is: epitaxially growing the channel material; After filling the channel material, the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer are subjected to high-temperature annealing, or the epitaxial channel material on the side walls of the first electrode material layer, the second electrode material layer, the third electrode material layer, and the fourth electrode material layer are removed.

17. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that Before the step of etching and removing the mask unit and the stacked structure covered by the mask unit, the method further includes: A spacer material is deposited to cover the outer surface.

18. The method for preparing a semiconductor memory cell structure according to claim 17, It is characterized in that After removing the remaining first sacrificial layer, the second sacrificial layer and the third sacrificial layer and before forming the gate dielectric layer, the method further includes: Performing patterning on the upper layer device, and etching the isolation material until the thickness reaches a portion of the side wall covering the first electrode material layer; and / or, A contact hole of the first electrode material layer and a contact hole of the second electrode material layer in the lower layer device are etched.

19. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that The method for exposing at least part of the sidewall of the third electrode material layer in each structural unit is: Depositing a silicon oxide layer and a bottom anti-reflection coating in sequence, wherein the bottom anti-reflection coating is located at a position having the same height as the third electrode material layer; Then forming silicon oxide sidewalls on the sidewalls of the upper device above the bottom anti-reflective coating; Then, removing the bottom anti-reflective coating, and etching the gate dielectric layer, so that the side wall of the third electrode material layer is exposed; Finally, the silicon oxide layer and the silicon oxide sidewalls are removed.

20. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that The method for forming the first gate layer includes: The gate material is deposited until its height is higher than the exposed sidewall of the third electrode material layer, and then the gate material is patterned.

21. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that The multilayer dielectric film formed on the upper surface of the first gate layer includes a silicon oxide film and a high-K dielectric film.

22. The method for preparing a semiconductor memory cell structure according to claim 8, It is characterized in that After forming the second gate layer, the method further includes: Depositing a dielectric film and etching contact holes for the upper layer device; and / or, The contact holes of the lower layer device and the upper layer device are respectively metal interconnected.

23. Application of a semiconductor memory cell structure or semiconductor memory in an electronic device, It is characterized in that The application includes using the semiconductor memory cell structure described in any one of claims 1-6 or using the semiconductor memory described in claim 7 or using the semiconductor memory cell structure prepared by the preparation method described in any one of claims 8-22.

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