Backside illuminated image sensor and manufacturing method thereof

Abstract

The invention relates to the field of semiconductors, and discloses a back-illuminated image sensor and a manufacturing method thereof, and the method comprises the steps: forming a groove in a bonding pad region of a substrate through employing photoetching and etching technologies; depositing an isolation layer on the surface of the substrate, wherein the isolation layer comprises two isolation unit layers formed by alternately stacking different materials; one isolation unit layer serves as a grinding barrier layer in the grinding process, and the grinding barrier layer is located in the isolation layer; manufacturing a through hole in the isolation layer in the groove and forming a conductive layer in the groove; depositing a dielectric layer on the surface of the processed substrate; grinding for multiple times to remove the dielectric layer and the isolation layer on the surface of the processed substrate; forming a substrate grounding structure in a logic circuit region corresponding to the substrate, and forming a metal grating structure in a pixel region of the substrate; and at least removing the dielectric layer in the groove to at least expose part of the conductive layer. And the dielectric layer and the isolation layer on the surface of the processed substrate are removed in a grinding manner, so that the publishing of one layer of photomask and one time of photoetching can be reduced, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and particularly to a back-illuminated image sensor and a manufacturing method thereof. Background Art

[0002] In a back-illuminated (BSI) image sensor, the metal wiring is located below the photodiode. Light passes through the microlens to reach the color filter, and then can directly irradiate the photodiode without being blocked and reflected by the metal wiring, with high light utilization rate. The back-illuminated image sensor has higher sensitivity.

[0003] The backside metal grid (BMG) of a back-illuminated image sensor forms a grid structure in the pixel area of the image sensor, which can reduce optical crosstalk. The metal grid can be buried under the color filter to obtain a normal back-illuminated image sensor (Normal BSI), or embedded between the color filters to obtain a buried color filter (BCF) image sensor. Compared with the normal back-illuminated image sensor, the embedded image sensor can further reduce crosstalk and improve image quality. However, the manufacturing process of the embedded image sensor requires two additional photomasks compared to the manufacturing process of the normal back-illuminated image sensor, resulting in an increase in production cost. The two additional photomasks in the manufacturing process of the embedded image sensor involve the following process steps: First, after fabricating a conductive structure in the groove of the pad (PAD) area and filling the groove, a specific photomask is required. Through photolithography and etching, most of the filling material in the area outside the groove is etched away, and then the remaining filling material on the substrate surface is completely removed by polishing. Second, after forming the metal grid, a specific photomask is required. Through photolithography and etching, a part of the conductive structure in the groove of the pad area is exposed, so as to facilitate subsequent testing.

[0004] Therefore, how to solve the above technical problems should be the focus of attention of those skilled in the art. Summary of the Invention

[0005] The purpose of the present application is to provide a back-illuminated image sensor and a manufacturing method thereof to reduce the manufacturing cost.

[0006] To solve the above technical problems, the present application provides a manufacturing method of a back-illuminated image sensor, including:

[0007] Forming a groove in the pad area of the substrate by using photolithography and etching techniques;

[0008] Deposit an isolation layer on the surface of the substrate. The isolation layer includes isolation unit layers stacked alternately with two different materials; one of the isolation unit layers serves as a polishing stop layer during the polishing process, and the polishing stop layer is located inside the isolation layer.

[0009] Make a through hole in the isolation layer within the groove and form a conductive layer within the groove to obtain a processed substrate.

[0010] Deposit a dielectric layer on the surface of the processed substrate.

[0011] Remove the dielectric layer and the isolation layer located on the surface of the processed substrate by polishing multiple times.

[0012] Form a substrate ground structure in the logic circuit region corresponding to the substrate and form a metal grid structure in the pixel region of the substrate.

[0013] Remove at least the dielectric layer within the groove to at least expose part of the conductive layer.

[0014] Optionally, removing at least the dielectric layer within the groove to at least expose part of the conductive layer includes:

[0015] Use a mask that forms a groove in the pad region of the substrate, and adopt photolithography and etching techniques to remove the dielectric layer within the groove and the isolation unit layer in direct contact with the dielectric layer that is above the conductive layer; among them, the isolation unit layer serving as a polishing stop layer also serves as an etching stop layer during the etching process.

[0016] Optionally, depositing an isolation layer on the surface of the substrate, where the isolation layer includes isolation unit layers stacked alternately with two different materials includes:

[0017] Deposit a first isolation unit layer on the surface of the substrate.

[0018] Deposit a second isolation unit layer on the surface of the first isolation unit layer.

[0019] Deposit a first isolation unit layer on the surface of the second isolation unit layer.

[0020] Optionally, removing the dielectric layer and the isolation layer located on the surface of the processed substrate by polishing multiple times includes:

[0021] Adopt chemical mechanical polishing to polish the dielectric layer located on the surface of the processed substrate and the first isolation unit layer located on the surface of the second isolation unit layer; the second isolation unit layer serves as a polishing stop layer.

[0022] Adopt chemical mechanical polishing and control the polishing time to polish and remove the second isolation unit layer and the first isolation unit layer located on the surface of the substrate.

[0023] Optionally, before forming a groove in the pad region of the substrate by using photolithography and etching techniques, it further includes:

[0024] Depositing a first protective layer on the surface of the substrate;

[0025] Correspondingly, before forming a substrate ground structure in the logic circuit region corresponding to the substrate and forming a metal grid structure in the pixel region of the substrate, it further includes:

[0026] Removing the first protective layer located in the logic circuit region.

[0027] Optionally, making a through hole in the isolation layer in the groove and forming a conductive layer in the groove, the processed substrate obtained includes:

[0028] Forming a through hole in the isolation layer located in the groove by using photolithography and etching techniques;

[0029] Depositing a conductive layer on the surface of the substrate having the through hole and the isolation layer; the conductive layer is distributed in the through hole, and the conductive layer located in the through hole is electrically connected to the metal structure in the pad region;

[0030] Using photolithography and etching techniques to remove the conductive layer located in the region outside the groove, and only retaining the conductive layer in a partial region inside the groove to obtain the processed substrate.

[0031] Optionally, forming a substrate ground structure in the logic circuit region corresponding to the substrate and forming a metal grid structure in the pixel region of the substrate includes:

[0032] Depositing a metal grid material layer on the surface of the polished substrate;

[0033] Using photolithography and etching techniques to etch the metal grid material layer, and retaining the metal grid material layer in the logic circuit region and the pixel region respectively as the substrate ground structure and the metal grid structure.

[0034] Optionally, depositing a metal grid material layer on the surface of the polished substrate includes:

[0035] Depositing a first adhesion layer on the surface of the polished substrate;

[0036] Depositing a metal layer on the surface of the first adhesion layer;

[0037] Depositing a second adhesion layer on the surface of the metal layer;

[0038] Depositing a second protective layer on the surface of the second adhesion layer.

[0039] Optionally, after forming a substrate ground structure in the logic circuit region corresponding to the substrate and forming a metal grid structure in the pixel region of the substrate, the method further includes:

[0040] Depositing a third protective layer on the surface of the substrate having the metal grid structure and the substrate ground structure;

[0041] Correspondingly, at least removing the dielectric layer in the groove to at least expose part of the conductive layer includes:

[0042] At least removing the dielectric layer and the third protective layer in the groove to at least expose part of the conductive layer.

[0043] The present application also provides a back-illuminated image sensor, which is manufactured by using the manufacturing method of any one of the above-mentioned back-illuminated image sensors.

[0044] A manufacturing method of a back-illuminated image sensor provided by the present application includes: forming a groove in a pad region of a substrate by using photolithography and etching techniques; depositing an isolation layer on the surface of the substrate, the isolation layer including isolation unit layers stacked alternately with two different materials; one of the isolation unit layers serves as a polishing barrier layer during the polishing process, and the polishing barrier layer is located inside the isolation layer; making a through hole in the isolation layer in the groove and forming a conductive layer in the groove to obtain a processed substrate; depositing a dielectric layer on the surface of the processed substrate; polishing multiple times to remove the dielectric layer and the isolation layer on the surface of the processed substrate; forming a substrate ground structure in the logic circuit region corresponding to the substrate and forming a metal grid structure in the pixel region of the substrate; at least removing the dielectric layer in the groove to at least expose part of the conductive layer.

[0045] It can be seen that in the manufacturing method of the present application, when depositing the isolation layer, the isolation layer includes isolation unit layers of two different materials, then making a through hole in the pad region and forming a conductive layer in the through hole, and then depositing a dielectric layer. When removing the dielectric layer and the isolation layer on the surface of the processed substrate, a polishing method is adopted. During polishing, one of the isolation unit layers in the isolation layer can serve as a polishing barrier layer, that is, the dielectric layer and the isolation unit layers above the polishing barrier layer are polished off, and then the remaining isolation unit layers are polished until all the isolation layers on the surface of the processed substrate are polished off. Subsequently, a substrate ground structure and a metal grid structure are fabricated, and the conductive layer is exposed to obtain a back-illuminated image sensor. In the present application, the polishing method is adopted to remove the dielectric layer and the isolation layer on the surface of the processed substrate, avoiding the use of photolithography and etching methods, that is, one mask plate publication and one photolithography process can be reduced, and the production cost can be reduced.

[0046] In addition, the present application also provides a back-illuminated image sensor having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 It is a flowchart of a manufacturing method of a back-illuminated image sensor provided by an embodiment of the present application;

[0049] Figures 2 to 12 It is a flowchart of a manufacturing process of a back-illuminated image sensor provided by an embodiment of the present application;

[0050] Figure 13 It is a schematic structural diagram of a back-illuminated image sensor in the prior art;

[0051] In the figure, 1. Substrate, 2. First protective layer, 3. Groove, 4. Isolation layer, 5. Through hole, 6. Conductive layer, 7. Dielectric layer, 8. Metal grating material layer, 9. Substrate grounding structure, 10. Metal grating structure, 11. Epitaxial silicon layer, 12. Opening, 13. Third protective layer, 41. First isolation unit layer, 42. Second isolation unit layer, 71. First depression, 72. Second depression, 81. Metal layer, 82. Second protective layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] In order to enable those skilled in the art to better understand the solutions of the present application, the following will further elaborate on the present application in conjunction with the drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0053] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0054] As described in the background art section, currently, the manufacturing process of embedded image sensors has two more photomasks than that of conventional back-illuminated image sensors, resulting in an increase in production costs.

[0055] In view of this, the present application provides a manufacturing method of a back-illuminated image sensor. Please refer to Figure 1, the method includes:

[0056] Step S101: Form a groove in the pad area of the substrate by using photolithography and etching techniques.

[0057] In this step, the substrate is the substrate after bonding thinning and includes an epitaxial silicon (EPI) layer. The substrate also includes a pixel area, a logic circuit area, and a pad area formed on the epitaxial silicon layer, and metal interconnect structures have been formed in each area.

[0058] In this step, a first photolithography and etching are performed on the substrate. To form the groove, the epitaxial silicon layer in the pad area needs to be completely etched away.

[0059] Step S102: Deposit an isolation layer on the surface of the substrate. The isolation layer includes isolation unit layers stacked alternately with two different materials; one of the isolation unit layers serves as a grinding barrier layer during the grinding process, and the grinding barrier layer is located inside the isolation layer.

[0060] The isolation layer is distributed in the area of the substrate except for the groove and inside the groove.

[0061] The hardness of the isolation unit layer serving as the grinding barrier layer is greater than that of the other isolation unit layer. In this embodiment, the materials of the two isolation unit layers are not limited and can be set by oneself. For example, the material of the isolation unit layer serving as the grinding barrier layer can be a silicon nitride containing nitrogen, including but not limited to any one of silicon nitride, silicon oxynitride, and silicon carbonitride; the material of the other isolation unit layer can be an oxide, such as silicon oxide, etc.

[0062] The number of isolation unit layers in the isolation layer is at least three to ensure that the isolation unit layer serving as the grinding barrier layer is located inside the isolation layer. It should be noted that in this embodiment, the specific number of isolation unit layers is not limited and can be set by oneself. For example, the number of isolation unit layers in the isolation layer can be three.

[0063] For the convenience of description, the isolation unit layer serving as the grinding barrier layer can be called the second isolation unit layer, and the other isolation unit layer can be called the first isolation unit layer.

[0064] For example, when the number of isolation unit layers in the isolation layer is three, in the direction away from the substrate, they are the first isolation unit layer, the second isolation unit layer, and the first isolation unit layer in sequence; when the number of isolation unit layers in the isolation layer is five, in the direction away from the substrate, they are the first isolation unit layer, the second isolation unit layer, the first isolation unit layer, the second isolation unit layer, and the first isolation unit layer in sequence.

[0065] Step S103: Make a through hole in the isolation layer in the groove and form a conductive layer in the groove to obtain a processed substrate.

[0066] The conductive layer located in the through hole is electrically connected to the metal structure in the pad area. The material of the conductive layer can be a metal material, such as aluminum, etc.

[0067] It should be noted that in this embodiment, the manufacturing methods of the through hole and the conductive layer are not limited and can be set by oneself.

[0068] As an implementable manner, a through hole is made in the isolation layer in the groove and a conductive layer is formed in the groove, and the processed substrate obtained includes:

[0069] Step S1031: Use photolithography and etching techniques to form a through hole in the isolation layer located in the groove.

[0070] In this step, the through hole needs to be etched to the metal structure of the substrate.

[0071] Step S1032: Deposit a conductive layer on the surface of the substrate having the through hole and the isolation layer; the conductive layer is distributed in the through hole, and the conductive layer located in the through hole is electrically connected to the metal structure in the pad area.

[0072] In this step, there are conductive layers both inside and outside the groove.

[0073] Step S1033: Use photolithography and etching techniques to remove the conductive layer in the area outside the groove, and only retain the conductive layer in the partial area within the groove to obtain the processed substrate.

[0074] Step S104: Deposit a dielectric layer on the surface of the processed substrate.

[0075] The dielectric layer needs to fill the groove, so a relatively thick dielectric layer needs to be deposited. Since the dielectric layer is conformally deposited, a depression will be formed in the part of the pad area corresponding to the groove.

[0076] The material of the dielectric layer can be silicon oxide.

[0077] Step S105: Grind multiple times to remove the dielectric layer and the isolation layer on the surface of the processed substrate.

[0078] Since the isolation layer includes isolation unit layers of different materials, the selectivity ratios of the grinding process for different materials are different. When grinding, start grinding from the dielectric layer towards the substrate direction, grind to the second isolation unit layer farthest from the substrate, and then remove the remaining isolation unit layers by setting an appropriate grinding time.

[0079] The grinding process can be a CMP (Chemical Mechanical Polishing) process.

[0080] The prior art uses photolithography and etching to remove most of the dielectric layer in the area outside the groove, and then uses a grinding process to remove the remaining dielectric layer and isolation layer on the surface of the substrate.

[0081] The isolation layer in the prior art is a single-layer structure, which is a layer of silicon oxide. If only the grinding process is used, due to the relatively thick dielectric layer, the grinding time is long, and since there is no grinding barrier layer, it is easy to grind to the epitaxial silicon layer, causing damage to the silicon surface.

[0082] This embodiment avoids using photolithography and etching, which can reduce the production of one photomask and one photolithography process, thus reducing production costs.

[0083] Step S106: Form a substrate ground structure in the logic circuit area corresponding to the substrate, and form a metal grid structure in the pixel area of the substrate.

[0084] Among them, the substrate ground structure is in direct contact with the surface of the substrate.

[0085] It should be noted that in this embodiment, the manufacturing processes of the metal grid structure and the substrate ground structure are not limited and can be set by oneself.

[0086] As an implementable manner, forming a substrate ground structure in the logic circuit area corresponding to the substrate and forming a metal grid structure in the pixel area of the substrate may include:

[0087] Step S1061: Deposit a metal grid material layer on the surface of the ground substrate.

[0088] Step S1062: Use photolithography and etching techniques to etch the metal grid material layer, and retain the metal grid material layer in the logic circuit area and the pixel area as the substrate ground structure and the metal grid structure respectively.

[0089] The metal grid structure includes metal. In order to improve the adhesion between the metal in the metal grid structure and the substrate, as an implementable manner, depositing a metal grid material layer on the surface of the ground substrate may include:

[0090] Deposit a first adhesion layer on the surface of the ground substrate;

[0091] Deposit a metal layer on the surface of the first adhesion layer;

[0092] Deposit a second adhesion layer on the surface of the metal layer;

[0093] Deposit a second protective layer on the surface of the second adhesion layer.

[0094] The material of the metal (i.e., the metal layer) in the metal grid structure can be aluminum or other metals. The materials of the first adhesion layer and the second adhesion layer can be titanium nitride, etc., which are not specifically limited in this embodiment.

[0095] The second protective layer can play a role in protecting the metal layer and preventing the metal layer from being damaged. The material of the second protective layer can be silicon oxide, etc., which is not specifically limited in this embodiment.

[0096] The first adhesion layer can enhance the bonding force between the metal layer and the substrate surface. The second adhesion layer can enhance the bonding force between the second protective layer and the metal layer, reducing the situation of the second protective layer peeling off.

[0097] Step S107: Remove at least the dielectric layer in the groove to expose at least part of the conductive layer.

[0098] The purpose of exposing part of the conductive layer is to facilitate subsequent testing.

[0099] It should be noted that in this embodiment, the method of removing at least the dielectric layer in the groove is not limited and depends on the situation. For example, a specific photomask can be used, and the lithography and etching techniques in the prior art can be adopted to etch and remove part of the dielectric layer on the conductive layer in the groove, forming an opening above the local part of the conductive layer in the groove; or, in order to further reduce the publication of one photomask, other methods can also be adopted, which will be elaborated in the following embodiments.

[0100] In the manufacturing method of this embodiment, when depositing the isolation layer, the isolation layer includes two isolation unit layers of different materials. Then, vias are made in the pad area and conductive layers are formed in the vias. Then, a dielectric layer is deposited. When removing the dielectric layer and the isolation layer on the processed substrate surface, a grinding method is adopted. During grinding, one of the isolation unit layers in the isolation layer can be used as a grinding barrier layer, that is, the dielectric layer and the isolation unit layer above the grinding barrier layer are ground off, and then the remaining isolation unit layer is ground until all the isolation layers on the processed substrate surface are ground off. Subsequently, a metal grid structure and a substrate grounding structure are made, and the conductive layer is exposed to obtain a back-illuminated image sensor. In this embodiment, the grinding method is adopted to remove the dielectric layer and the isolation layer on the processed substrate surface, avoiding the use of lithography and etching methods, that is, it can reduce the publication of one photomask and one lithography process, and reduce the production cost.

[0101] Based on the above embodiments, in an embodiment of the present application, removing at least the dielectric layer in the groove to expose at least part of the conductive layer may include:

[0102] Use a photomask that forms a groove in the pad area of the substrate, and adopt photolithography and etching techniques to remove the dielectric layer within the groove and above the conductive layer and the isolation unit layer in direct contact with the dielectric layer; wherein, the isolation unit layer serving as a polishing barrier also serves as an etching barrier during the etching process.

[0103] The isolation unit layer in direct contact with the dielectric layer and the dielectric layer can be made of the same material, which can both be silicon oxide, so they can be etched away together.

[0104] Due to the different selectivity ratios of the etching process for oxides and silicon nitrides, the second isolation unit layer deposited on the sidewall of the groove in the above step can serve as an etching barrier for this step of etching, avoiding etching the epitaxial silicon layer on the sidewall of the groove area and preventing subsequent water vapor from entering, which affects reliability. In the manufacturing method of the prior art, the photomask used when making a groove in the pad area cannot be used in this step because there is no film layer that plays an etching barrier role in the groove in the prior art, which will etch the epitaxial silicon layer on the sidewall of the pad area, and subsequent water vapor enters the epitaxial silicon, resulting in reliability failure.

[0105] In this embodiment, photolithography and etching techniques are also adopted, but the photomask used is the photomask used when making a groove in the pad area, which can reduce the publication of one layer of photomask, that is, the manufacturing method in this embodiment can reduce the publication of two layers of photomasks and reduce one photolithography process, further reducing the production cost.

[0106] Based on any of the above embodiments, in an embodiment of the present application, when the number of isolation unit layers in the isolation layer is three, deposit an isolation layer on the surface of the substrate, and the isolation layer includes isolation unit layers with two different materials alternately stacked, including:

[0107] Deposit a first isolation unit layer on the surface of the substrate;

[0108] Deposit a second isolation unit layer on the surface of the first isolation unit layer;

[0109] Deposit a first isolation unit layer on the surface of the second isolation unit layer.

[0110] As an implementable manner, multiple times of polishing to remove the dielectric layer and the isolation layer on the surface of the processed substrate may include:

[0111] Adopt chemical mechanical polishing to polish the dielectric layer on the surface of the processed substrate and the first isolation unit layer on the surface of the second isolation unit layer; the second isolation unit layer serves as a polishing barrier;

[0112] Adopt chemical mechanical polishing method, and polish and remove the second isolation unit layer and the first isolation unit layer located on the surface of the substrate by controlling the polishing time.

[0113] Based on any of the above embodiments, in an embodiment of the present application, before forming a groove in the pad area of the substrate by using lithography and etching techniques, it may further include:

[0114] Deposit a first protective layer on the surface of the substrate;

[0115] Correspondingly, before forming a substrate ground structure in the logic circuit area corresponding to the substrate and forming a metal grid structure in the pixel area of the substrate, it further includes:

[0116] Remove the first protective layer located in the logic circuit area.

[0117] The first protective layer can play a role in protecting the epitaxial silicon layer, and the first protective layer includes but is not limited to a silicon oxide layer, etc.

[0118] Since the substrate ground structure needs to be in direct contact with the surface of the substrate, it is necessary to remove the first protective layer in the logic circuit area. The removal of the first protective layer can adopt lithography and etching techniques.

[0119] Based on any of the above embodiments, in an embodiment of the present application, after forming a substrate ground structure in the logic circuit area corresponding to the substrate and forming a metal grid structure in the pixel area of the substrate, it further includes:

[0120] Deposit a third protective layer on the surface of the substrate having the metal grid structure and the substrate ground structure;

[0121] Correspondingly, at least remove the dielectric layer in the groove to at least expose part of the conductive layer, including:

[0122] At least remove the dielectric layer and the third protective layer in the groove to at least expose part of the conductive layer.

[0123] The third protective layer can play a role in protecting the metal grid structure and the substrate ground structure, and avoid the exposure of the metal sidewalls in the metal grid structure and the substrate ground structure.

[0124] The material of the third protective layer includes but is not limited to silicon oxide, etc.

[0125] Next, a specific situation is used to elaborate on the manufacturing method of the back-illuminated image sensor in the present application.

[0126] Step 1: As Figure 2As shown, a first protective layer 2 is deposited on the surface of the substrate 1. The substrate 1 includes a pixel region, a logic circuit region, and a pad region formed on an epitaxial silicon layer 11, and metal interconnect structures have been formed in each region.

[0127] Step 2: As Figure 3 shown, the substrate 1 is subjected to a first photolithography and etching to form a groove 3 in the pad region. Then, an isolation layer 4 is deposited. The isolation layer 4 includes a first isolation unit layer 41, a second isolation unit layer 42, and a first isolation unit layer 41 stacked in sequence in a direction away from the substrate 1. The first isolation unit layer 41 is a silicon oxide layer, and the second isolation unit layer 42 is a nitride layer.

[0128] Step 3: As Figure 4 shown, the substrate 1 is subjected to a second photolithography and etching to form a via hole 5 in the pad region. The via hole 5 needs to be etched to the metal structure of the substrate 1, and then a conductive layer 6 is deposited for metal connection.

[0129] Step 4: As Figure 5 shown, the substrate 1 is subjected to a third photolithography and etching to retain only the conductive layer 6 in the pad region, and the conductive layer 6 in other regions is etched away.

[0130] Step 5: As Figure 6 shown, a silicon oxide dielectric layer 7 is deposited. In order to fill the groove 3 in the pad region, a relatively thick dielectric layer 7 is deposited. Since the dielectric layer 7 is conformally deposited, a first depression 71 is formed in the pad region.

[0131] Step 6: As Figure 7 shown, multiple CMP processes are performed to optimize the flatness of the surface of the substrate 1 after polishing. The second isolation unit layer 42 in Step 2 can be used as a polishing stop layer, and the second isolation unit single layer and the first isolation unit layer 41 on the substrate 1 are further removed by setting an appropriate polishing time. Among them, before the CMP process starts, since the height of the dielectric layer 7 in the pad region is lower than that in other regions, after CMP polishing, there will be a slightly second depression 72 in the dielectric layer 7 in the large pad region, as Figure 7 shown in

[0132] Step 7: As Figure 8 shown, the substrate 1 is subjected to a fourth photolithography and etching to expose the epitaxial silicon layer 11 in the logic circuit region.

[0133] Step 8: As Figure 9 shown, a metal grid material layer 8 is deposited on the substrate 1. The metal grid material layer 8 is a composite material layer, which are a first adhesion layer, a metal layer 81, a second adhesion layer, and a second protective layer 82 respectively.

[0134] Step 9: As Figure 10As shown, the fifth photolithography and etching are performed on the substrate 1 to form a substrate grounding structure 9 and a metal grid structure 10;

[0135] Step 10: As Figure 11 shown, a third protective layer 13 is deposited on the substrate 1 to protect the substrate grounding structure 9 and the metal grid structure 10, avoiding the exposure of sidewall metals;

[0136] Step 11: As Figure 12 shown, using the photomask in Step 2, the conductive layer 6 in the pad area is completely exposed through photolithography and etching techniques, and an opening 12 is formed on the conductive layer 6.

[0137] Figure 12 Compared with the back-illuminated image sensor fabricated in the prior art as Figure 13 described, in this embodiment, the isolation layer in the groove 3 in the pad area is a multi-layer structure, and after the last etching step, the upper surface of the conductive layer in the groove 3 is completely exposed.

[0138] From Figure 12 and Figure 13 it can be seen that due to the change in the number of photomask layers, the opening 12 above the conductive layer in the pad area in this embodiment is larger than the opening 12 above the conductive layer in the prior art. The electrical properties and yield of the process in this embodiment have been verified by actual tape-out and there are no problems in the probing test.

[0139] This application also provides a back-illuminated image sensor, which is fabricated by using the manufacturing method of the back-illuminated image sensor described in any one of the above embodiments.

[0140] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0141] The back-illuminated image sensor and its manufacturing method provided by this application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the solution and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A manufacturing method of a back-illuminated image sensor, characterized in that, Comprising: Using photolithography and etching techniques to form a groove in the pad region of the substrate; Depositing an isolation layer on the surface of the substrate, the isolation layer comprising an isolation unit layer formed by alternately laminating two different materials; one of the isolation unit layers serves as a polishing stop layer during the polishing process, and the polishing stop layer is located inside the isolation layer; Fabricating a through hole in the isolation layer within the groove and forming a conductive layer within the groove to obtain a processed substrate; Depositing a dielectric layer on the surface of the processed substrate; Repeatedly polishing to remove the dielectric layer and the isolation layer located on the surface of the processed substrate; Forming a substrate ground structure in the logic circuit region corresponding to the substrate and forming a metal grid structure in the pixel region of the substrate; At least removing the dielectric layer within the groove to at least expose a part of the conductive layer.

2. The manufacturing method of the back-illuminated image sensor according to claim 1, characterized in that, At least removing the dielectric layer within the groove to at least expose a part of the conductive layer includes: Using a mask for forming a groove in the pad region of the substrate, and adopting photolithography and etching techniques to remove the dielectric layer within the groove and above the conductive layer and the isolation unit layer in direct contact with the dielectric layer; wherein, the isolation unit layer serving as the polishing stop layer also serves as an etching stop layer during the etching process.

3. The manufacturing method of the back-illuminated image sensor according to claim 1, wherein, When the number of isolation unit layers in the isolation layer is three, depositing an isolation layer on the surface of the substrate, the isolation layer comprising an isolation unit layer formed by alternately laminating two different materials includes: Depositing a first isolation unit layer on the surface of the substrate; Depositing a second isolation unit layer on the surface of the first isolation unit layer; Depositing a first isolation unit layer on the surface of the second isolation unit layer.

4. The manufacturing method of the back-illuminated image sensor according to claim 3, characterized in that, Repeatedly polishing to remove the dielectric layer and the isolation layer located on the surface of the processed substrate includes: Adopting chemical mechanical polishing to polish the dielectric layer located on the surface of the processed substrate and the first isolation unit layer located on the surface of the second isolation unit layer; the second isolation unit layer serves as a polishing stop layer; Adopting chemical mechanical polishing, and controlling the polishing time to polish and remove the second isolation unit layer and the first isolation unit layer located on the surface of the substrate.

5. The manufacturing method of the back-illuminated image sensor according to claim 1, characterized in that, Before using photolithography and etching techniques to form a groove in the pad region of the substrate, it further includes: Depositing a first protective layer on the surface of the substrate; Correspondingly, before forming a substrate ground structure in the logic circuit region corresponding to the substrate and forming a metal grid structure in the pixel region of the substrate, it further includes: Removing the first protective layer located in the logic circuit region.

6. The manufacturing method of the back-illuminated image sensor according to claim 1, characterized in that, Fabricating a through hole in the isolation layer within the groove and forming a conductive layer within the groove to obtain a processed substrate includes: Adopting photolithography and etching techniques to form a through hole in the isolation layer within the groove; Depositing a conductive layer on the surface of the substrate having the through hole and the isolation layer; the conductive layer is distributed within the through hole, and the conductive layer within the through hole is electrically connected to the metal structure in the pad region; Adopting photolithography and etching techniques to remove the conductive layer in the region outside the groove, and only retaining the conductive layer in a partial region within the groove to obtain a processed substrate.

7. The manufacturing method of the back-illuminated image sensor according to claim 1, characterized in that, Forming a substrate ground structure in a logic circuit region corresponding to the substrate and forming a metal grid structure in a pixel region of the substrate includes: Depositing a metal grid material layer on the surface of the polished substrate; Using photolithography and etching techniques to etch the metal grid material layer, and retaining the metal grid material layers in the logic circuit region and the pixel region of the substrate as the substrate ground structure and the metal grid structure respectively.

8. The manufacturing method of the back-illuminated image sensor according to claim 7, wherein, Depositing a metal grid material layer on the surface of the polished substrate includes: Depositing a first adhesion layer on the surface of the polished substrate; Depositing a metal layer on the surface of the first adhesion layer; Depositing a second adhesion layer on the surface of the metal layer; Depositing a second protective layer on the surface of the second adhesion layer.

9. The manufacturing method of the back-illuminated image sensor according to any one of claims 1 to 8, characterized in that, After forming a substrate ground structure in a logic circuit region corresponding to the substrate and forming a metal grid structure in a pixel region of the substrate, it further includes: Depositing a third protective layer on the surface of the substrate having the metal grid structure and the substrate ground structure; Correspondingly, at least removing the dielectric layer in the groove to at least expose part of the conductive layer includes: At least removing the dielectric layer and the third protective layer in the groove to at least expose part of the conductive layer.

10. A back-illuminated image sensor, characterized in that, The back-illuminated image sensor is manufactured by using the manufacturing method of the back-illuminated image sensor according to any one of claims 1 to 9.

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