Memory structure, method of making the same, three-dimensional memory and storage system

Abstract

The present disclosure provides a memory structure, a manufacturing method thereof, a three-dimensional memory and a storage system. The memory structure comprises: a first substrate having a memory array on a surface thereof, the surface of the first substrate having a core region and a peripheral circuit region, the peripheral circuit region surrounding the core region, and the memory array being located in the core region; a plurality of spaced dielectric isolation structures, each of the dielectric isolation structures penetrating the first substrate between the core region and the peripheral circuit region, and each of the dielectric isolation structures surrounding the core region; and a dielectric connection portion penetrating the first substrate and connecting adjacent dielectric isolation structures. The memory structure has a plurality of spaced dielectric isolation structures and is connected by the dielectric connection portion, so that in the case of a disconnection defect in the dielectric isolation structure, the core region and the peripheral circuit region can be completely isolated by the dielectric connection portion, thereby reducing the problem of leakage caused by defects and improving the reliability of the product.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a memory structure, a manufacturing method thereof, a three-dimensional memory and a storage system. BACKGROUND

[0002] With the increasing demand for integration and storage capacity, 3D NAND memory emerges as the times require. The 3D NAND memory greatly saves the silicon area, reduces the manufacturing cost, and increases the storage capacity.

[0003] In the 3D NAND memory structure, a vertical stacked multi-layer data storage unit is adopted to realize a stacked 3D NAND memory structure. However, other circuits such as decoders, page buffers and latches are formed by CMOS devices, and the process of CMOS devices cannot be integrated with 3D NAND devices. At present, different processes are used to form 3D NAND memory arrays and logic circuits respectively, and the two are bonded together through bonding technology. Then, through backside processing, the substrate forming the 3D NAND memory array is thinned or removed, so that the channel structure in the 3D NAND memory structure has an exposed end portion. Then, doped amorphous silicon is covered, and laser anneal process is used for crystallization to form a doped polysilicon layer. Then, a lead portion is formed in the doped polysilicon layer to lead out the channel structure from the back of the substrate.

[0004] In the above-mentioned backside process of forming the lead portion, a backside deep trench isolation (BDTI) can also be formed in the doped polysilicon layer at the same time. The BDTI surrounds the 3D NAND memory array, and is filled with dielectric material, which is used to isolate the 3D NAND memory array from peripheral circuits such as through silicon contacts (TSC) and conductive channels (CT) connected to the TSC, so as to effectively alleviate the leakage problem. However, as the number of layers in the NAND memory structure iterates, it is difficult to completely isolate the peripheral circuit from the core area with the 3D NAND memory array, thereby causing leakage and reducing the reliability of the product. SUMMARY

[0005] The embodiments of the present disclosure provide a memory structure, a manufacturing method thereof, a three-dimensional memory and a storage system to at least partially solve the problem of leakage and low reliability of the memory structure in the prior art.

[0006] According to one aspect of the present disclosure, a memory structure is provided, comprising: a first substrate having a memory array on a surface thereof, the first substrate having a core region and a peripheral circuit region on the surface thereof, the peripheral circuit region surrounding the core region, the memory array being located in the core region; a plurality of dielectric isolation structures spaced apart from each other, each of the dielectric isolation structures penetrating the first substrate between the core region and the peripheral circuit region, and each of the dielectric isolation structures surrounding the core region; and a dielectric connection portion penetrating the first substrate and connecting adjacent dielectric isolation structures.

[0007] Further, the adjacent dielectric isolation structures are connected by a plurality of dielectric connection portions.

[0008] Further, the core region has dielectric connection portions on opposite sides thereof.

[0009] Further, the core region has dielectric connection portions on opposite sides thereof.

[0010] Further, the core region has dielectric connection portions on opposite sides thereof.

[0011] Further, the adjacent dielectric isolation structures have a spacing region therebetween, and the spacing region between the adjacent dielectric connection portions has the same area in the orthographic projection on the surface of the first substrate.

[0012] Further, the dielectric isolation structures are 2-3 in number.

[0013] Further, the memory structure further comprises: a conductive channel provided in the peripheral circuit region; and / or a lead-out portion penetrating the first substrate and connected to the conductive channel.

[0014] Further, the memory structure further comprises: a buffer layer provided on a side of the first substrate away from the memory array, and the dielectric isolation structures penetrating the first substrate and the buffer layer.

[0015] According to another aspect of the present disclosure, a manufacturing method of the above memory structure is provided, comprising the following steps: providing a first substrate having a memory array on a surface thereof, the first substrate having a core region and a peripheral circuit region on the surface thereof, the peripheral circuit region surrounding the core region, the memory array being located in the core region; penetrating a plurality of dielectric isolation structures in the first substrate between the core region and the peripheral circuit region, so that each of the dielectric isolation structures is spaced apart from each other and surrounds the core region; and penetrating a dielectric connection portion in the first substrate, so that the dielectric connection portion connects adjacent dielectric isolation structures.

[0016] Further, a first substrate having a surface with a memory array is provided, comprising: providing a third substrate having a surface with a memory array, the memory array having a plurality of channel structures penetrating through the third substrate; removing at least part of the third substrate to expose a side end of the channel structures; forming a doped polysilicon layer wrapping the exposed end of the channel structures.

[0017] According to another aspect of the present disclosure, a three-dimensional memory is also provided, comprising: the above-mentioned memory structure; a peripheral circuit electrically connected with the memory structure.

[0018] According to another aspect of the present disclosure, a storage system is also provided, comprising a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and being configured to control the three-dimensional memory, the three-dimensional memory comprising the above-mentioned memory structure, or the three-dimensional memory being the above-mentioned three-dimensional memory.

[0019] The technical solution of the present disclosure provides a memory structure, comprising a first substrate having a surface with a memory array, a dielectric isolation structure and a dielectric connection portion, the surface of the first substrate having a core region and a peripheral circuit region, the peripheral circuit region surrounding the core region, the memory array being located in the core region, the dielectric isolation structure being a plurality of dielectric isolation structures spaced apart, each dielectric isolation structure penetrating through the first substrate between the core region and the peripheral circuit region, and each dielectric isolation structure surrounding the core region, the dielectric connection portion penetrating through the first substrate, and each dielectric connection portion connecting adjacent dielectric isolation structures. Since the above-mentioned memory structure has a plurality of dielectric isolation structures spaced apart, and is connected through the dielectric connection portion, in the case of a disconnection defect of the dielectric isolation structure, the plurality of dielectric isolation structures are connected through the above-mentioned dielectric connection portion, which can achieve complete isolation of the core region and the peripheral circuit region, thereby reducing the problem of electric leakage caused by defects and improving the reliability of the product. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which form a part of the present disclosure, are used to provide further understanding of the present disclosure, and the illustrative embodiments of the present disclosure and their description serve the purpose of explaining the present disclosure. In the drawings:

[0021] Figure 1 A cross-sectional structure schematic diagram of a memory structure provided in an embodiment of the present disclosure is shown;

[0022] Figure 2 A cross-sectional structure schematic diagram of a memory structure provided in an embodiment of the present disclosure is shown; Figure 1 A top view structure schematic diagram of the dielectric isolation structure and the dielectric connection portion in the memory structure shown;

[0023] Figure 3A schematic diagram of a substrate cross-sectional structure after providing a third substrate with a surface having a memory array and a conductive channel is shown in a method of fabricating a memory structure according to embodiments of the present disclosure.

[0024] Figure 4 A schematic diagram of a substrate cross-sectional structure after removing Figure 3 A schematic diagram of a substrate cross-sectional structure after exposing the end of the channel structure in the memory array is shown.

[0025] Figure 5 A schematic diagram of a substrate cross-sectional structure after forming a first substrate covering Figure 4 A schematic diagram of a substrate cross-sectional structure after forming a dielectric isolation structure and a dielectric connection portion through

[0026] Figure 6 A schematic diagram of a substrate cross-sectional structure after forming a dielectric isolation structure and a dielectric connection portion through Figure 5 A schematic diagram of a substrate cross-sectional structure after forming a dielectric isolation structure and a dielectric connection portion through

[0027] Figure 7 A schematic diagram of a substrate cross-sectional structure after forming a dielectric isolation structure and a dielectric connection portion through Figure 6 A schematic diagram of a substrate cross-sectional structure after forming a dielectric isolation structure and a dielectric connection portion through

[0028] Figure 8 A schematic diagram of a three-dimensional memory structure according to embodiments of the present disclosure is shown.

[0029] Figure 9 A schematic diagram of a storage system according to embodiments of the present disclosure is shown.

[0030] Figure 10 A schematic diagram of a mobile phone according to embodiments of the present disclosure is shown.

[0031] Wherein, the above drawings include the following reference signs:

[0032] 10, third substrate; 20, gate stack structure; 210, gate structure; 220, isolation layer; 30, channel structure; 40, conductive channel; 50, first substrate; 60, buffer layer; 70, lead-out portion; 80, dielectric isolation structure; 90, dielectric connection portion; 100, interlayer dielectric layer; 300, three-dimensional memory; 301, memory structure; 302, peripheral circuit; 400, storage system; 401, three-dimensional memory; 402, controller; 500, mobile phone; 600, chip. DETAILED DESCRIPTION

[0033] It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the drawings and in combination with embodiments.

[0034] In order to enable a person skilled in the art to better understand the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in combination with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person skilled in the art without creative labor should fall within the scope of protection of the present disclosure.

[0035] It should be noted that the terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0036] In some embodiments, in the back surface process of forming the lead part, a back deep trench isolation (BDTI) can also be formed in the doped polysilicon layer at the same time, which surrounds the 3D NAND memory array, and is filled with a dielectric material, which is used to isolate the 3D NAND memory array from the peripheral circuit such as the through silicon contact (TSC) and the conductive channel (CT) connected to the TSC, so as to effectively alleviate the leakage problem. However, as the number of layers in the NAND memory structure is iterated, it is difficult to completely isolate the peripheral circuit from the core area with the 3D NAND memory array, thereby causing leakage, resulting in reduced reliability of the product.

[0037] The inventors of the present disclosure have researched the above-mentioned problems and proposed a memory structure, as shown in Figure 1 and Figure 2 comprising:

[0038] a first substrate 50 having a memory array on a surface thereof, the first substrate 50 having a core area and a peripheral circuit area on the surface thereof, the peripheral circuit area surrounding the core area, and the memory array being located in the core area, wherein the core area is as shown in the A area in Figure 1 , and the peripheral circuit area is as shown in the B area in Figure 1 ;

[0039] a plurality of spaced dielectric isolation structures 80, each of the dielectric isolation structures 80 penetrating the first substrate 50 between the core area and the peripheral circuit area, and each of the dielectric isolation structures 80 surrounding the core area;

[0040] The dielectric connection portion 90 penetrates the first substrate 50, and the dielectric connection portion 90 connects adjacent dielectric isolation structures 80.

[0041] The inventors found through research that defects existing in the backside process can cause defects in the photolithography of the BDTI and eventually cause the peripheral circuit to not be completely isolated from the core region having the 3D NAND memory array, thereby causing leakage. However, by using the above memory structure of the present disclosure, since the above memory structure has a plurality of dielectric isolation structures arranged at intervals and connected by dielectric connection portions, in the case where the dielectric isolation structures have defects in disconnection due to the photolithography process, the plurality of dielectric isolation structures are connected by the dielectric connection portions, which can achieve complete isolation of the core region and the peripheral circuit region, thereby reducing the leakage problem caused by defects and improving the reliability of the product.

[0042] In the above memory structure of the present disclosure, each dielectric isolation structure 80 surrounds the core region, which can be understood as each dielectric isolation structure 80 forming a separate ring around the core region, and a plurality of dielectric isolation structures 80 respectively forming a plurality of independent rings around the core region. For example, as shown in Figure 2 , two dielectric isolation structures 80 each form an independent ring around the core region (A region), thereby being arranged around the A region.

[0043] In the above memory structure of the present disclosure, the dielectric material forming the dielectric isolation structure 80 and the dielectric connection portion 90 can be independently selected from conventional dielectric materials in the prior art, such as SiO2, SiN, etc.

[0044] In some embodiments, the above dielectric isolation structure 80 is 2-3. The above number of dielectric isolation structures 80 can ensure complete isolation of the core region and the peripheral circuit region while avoiding excessive process steps, process time and process cost.

[0045] In some embodiments, a plurality of dielectric connection portions 90 are provided between adjacent dielectric isolation structures 80, as shown in Figure 2 . By providing a plurality of dielectric connection portions 90 between adjacent dielectric isolation structures 80, in the case where the dielectric isolation structure 80 has a plurality of defects at different positions due to the preparation process, the complete isolation of the core region and the peripheral circuit region by the dielectric isolation structure 80 can be further ensured.

[0046] For example, as shown in Figure 2As shown, the dielectric isolation structures 80 are arranged in a plurality of intervals, each of the dielectric isolation structures 80 includes a first interval section extending along the x-axis direction and a second interval section extending along the y-axis direction, the first interval section and the second interval section are alternately connected to form the dielectric isolation structure 80 surrounding the core region, the dielectric isolation structures 80 are arranged in a plurality of intervals, a part of the dielectric isolation structures 80 extend along the y-axis direction to connect adjacent first interval sections, and another part of the dielectric isolation structures 80 extend along the x-axis direction to connect adjacent second interval sections.

[0047] More preferably, the core region has dielectric connection portions 90 on both sides, as shown. Figure 2 In the case that the dielectric isolation structures 80 have defects on both sides of the core region due to the preparation process, the above arrangement of the dielectric connection portions 90 can ensure that the core region and the peripheral circuit region are completely isolated by the dielectric isolation structures 80.

[0048] In the case that the defects on the dielectric isolation structures 80 are not uniformly distributed, in order to further ensure that the core region and the peripheral circuit region are completely isolated by the dielectric isolation structures 80, in some embodiments, the number of dielectric connection portions 90 on both sides of the core region is equal; more preferably, the shortest distance between adjacent dielectric connection portions 90 on both sides of the core region is equal, as shown. Figure 2 In another embodiment, the adjacent dielectric isolation structures 80 have an interval region, and the interval region between the adjacent dielectric connection portions 90 has the same area on the orthographic projection of the surface of the first substrate 50. By arranging the adjacent dielectric connection portions 90 to satisfy the above relationship, the core region and the peripheral circuit region can be completely isolated by the plurality of dielectric isolation structures 80 in the case that there are multiple defects at different positions of the dielectric isolation structures 80, thereby effectively reducing the problem of electric leakage caused by defects; in addition, since the dielectric connection portions 90 and the plurality of dielectric isolation structures 80 connected thereto can be formed by setting a mask plate and through a photolithography process, the arrangement of the adjacent dielectric connection portions 90 satisfying the above relationship is conducive to the design and manufacture of the mask plate.

[0049] The above memory structure of the present disclosure can further include a buffer layer 60, the buffer layer 60 is arranged on the side of the first substrate away from the memory array and the conductive channel, at this time, the above dielectric isolation structures 80 and the above dielectric connection portions 90 also penetrate the buffer layer 60, as shown. Figure 1 The above buffer layer 60 is used to prevent over-etching in the process of etching the isolation groove of the dielectric isolation structure 80 and the connection groove of the dielectric connection portion 90.

[0050] The above memory structure of the present disclosure can further include a second substrate and a bonding portion, the second substrate has a CMOS circuit, and the bonding portion connects the memory array and the CMOS circuit.

[0051] In the above memory structure of the present disclosure, the conductive channel 40 can be provided in the peripheral circuit region, and / or the lead-out portion 70 can be provided in the peripheral circuit region, the lead-out portion 70 penetrating the first substrate 50 and being connected with the conductive channel 40, as shown in Figure 1 .

[0052] The above lead-out portion 70 can be formed by TSC technology, specifically, the silicon wafer (the first substrate 50) with the 3D NAND memory array and the second substrate with the logic circuit can be formed by different processes respectively, and then the two are bonded together by bonding technology, and after bonding, the backside wiring of the silicon wafer is realized by TSC technology, which is a vertical electrical connection through the silicon wafer, by directly forming a contact point (usually referred to as a through-silicon contact) penetrating the silicon wafer, and making it electrically connected with the contact point of the bonded CMOS device through the conductive channel 40, thereby providing the interconnection of the vertically aligned devices by internal wiring which significantly reduces the complexity and overall size of the chip.

[0053] In the above memory structure of the present disclosure, the memory array can include a gate stack structure 20 formed on the first substrate 50, the gate stack structure 20 including gate layers and isolation layers 220 arranged in an alternating stack, the gate stack structure 20 having a channel structure 30 penetrating to the first substrate 50, as shown in Figure 1 .

[0054] The number of layers of the above gate layers and the above isolation layers 220 can be reasonably set by those skilled in the art according to actual needs, the above isolation layers 220 can be SiO2, and the above gate layers are usually formed of metal, which can be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0055] The above channel structure 30 can be a charge-trap type channel structure 30, in which case the channel structure 30 can include, in order on the sidewall of the channel via hole, a charge blocking layer, a charge trapping layer and a tunneling layer. Those skilled in the art can reasonably select the materials of the above functional layers in the above channel structure 30, such as the material of the charge blocking layer can be SiO2, the material of the charge trapping layer can be SiN, the material of the tunneling layer can be SiO2, the material of the channel layer can be polysilicon, and the material of the dielectric filling layer can be SiO2.

[0056] This disclosure also provides a method for fabricating the above-described memory structure, comprising the following steps: providing a first substrate having a memory array on its surface, the first substrate having a core region and a peripheral circuit region on its surface, the peripheral circuit region surrounding the core region, and the memory array located in the core region; providing a plurality of dielectric isolation structures through the first substrate located between the core region and the peripheral circuit region, such that each dielectric isolation structure is spaced apart from each other and surrounds the core region; and providing dielectric connection portions through the first substrate, such that the dielectric connection portions connect adjacent dielectric isolation structures.

[0057] For example, the method for manufacturing the memory structure described above may include the following process:

[0058] A third substrate 10 is provided with a surface having a memory array and conductive channels 40, wherein the memory array and conductive channels 40 are located on the same side surface of the third substrate 10, and the conductive channels 40 are located on one side of the memory array, such as... Figure 3 As shown;

[0059] At least a portion of the third substrate 10 is removed to expose the ends of the channel structure 30 in the memory array, such as... Figure 4 As shown;

[0060] A first substrate 50 is formed to enclose the exposed end of the aforementioned channel structure 30, such as Figure 5 As shown;

[0061] A dielectric isolation structure 80 and a dielectric connection portion 90 are formed that penetrate the first substrate 50, such as Figure 6 and Figure 7 As shown, where, Figure 6 and Figure 7 These are schematic diagrams of the cross-sectional and top views of the substrate after the dielectric isolation structure 80 and the dielectric connection portion 90 are formed.

[0062] By employing the method for fabricating the memory structure described above, since multiple spaced dielectric isolation structures 80 are formed and dielectric connection portions 90 are formed to connect adjacent dielectric isolation structures 80, even if the dielectric isolation structures 80 have defects due to the photolithography process, the multiple dielectric isolation structures 80 connected by the dielectric connection portions 90 can completely isolate the core area and the peripheral circuit area, thereby avoiding leakage problems caused by defects and improving the reliability of the product.

[0063] The following will be combined with the appendix Figures 3 to 7More specific embodiments of the method of fabricating a memory structure according to the present disclosure are described in detail. These specific embodiments may, however, be implemented in many different forms and should not be construed as limiting. It will be understood that the embodiments are set forth by way of example and that the scope of the disclosure is not limited to the embodiments described herein.

[0064] First, a third substrate 10 having a surface with a memory array and a conductive channel 40 is provided, the conductive channel 40 being located at one side of the memory array, as shown in Figure 3 .

[0065] In some embodiments, the step of providing the third substrate 10 having a surface with a memory array and a conductive channel 40 includes: forming a stack on the third substrate 10, the stack including alternatingly stacked sacrificial layers and isolation layers 220 in a direction away from the third substrate 10, forming an interlayer dielectric layer 100 covering the stack; forming a channel structure 30 through the stack to the third substrate 10 and forming a conductive channel 40 through the interlayer dielectric layer 100 to the third substrate 10; replacing the sacrificial layers with gate structures 210 to form a gate stack structure 20, as shown in Figure 3 .

[0066] In the above embodiments, the isolation layers 220 and the sacrificial layers can be prepared by deposition processes, such as chemical vapor deposition processes. The number of layers of the sacrificial layers and the isolation layers 220 can be reasonably set by those skilled in the art according to actual needs, and the types of the sacrificial layers and the isolation layers 220 can also be reasonably selected by those skilled in the art, such as the isolation layers 220 can be SiO2and the sacrificial layers can be SiN.

[0067] The material of the third substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or can also be other materials, such as gallium arsenide and other group III-V compounds.

[0068] The step of forming the channel structure 30 in the stack can include: forming a channel via through the stack to the third substrate 10; sequentially forming a functional layer and a channel layer arranged in layers on the inner surface of the channel via; and forming a dielectric filling layer in the channel via so that the channel layer wraps the dielectric filling layer.

[0069] The step of replacing the sacrificial layer with the gate structure 210 can include forming a gate trench in the stack that extends through the third substrate 10 to expose an end surface of the sacrificial layer, and then wet-etching the sacrificial layer from the exposed end surface to remove the sacrificial layer and form the gate structure 210 in place of the sacrificial layer.

[0070] After the step of providing the third substrate 10 having a surface with a memory array and conductive channels 40, the method of fabricating the memory structure of the present disclosure can further include the step of providing a second substrate having a CMOS circuit and bonding the gate stack structure 20 of the third substrate 10 to the CMOS circuit. In an example, the side of the gate stack structure 20 distal to the first substrate 50 is electrically connected to the CMOS circuit by the bond.

[0071] After the step of providing the third substrate 10 having a surface with a memory array and conductive channels 40, the third substrate 10 is removed to expose an end of the channel structure 30 in the memory array, as shown in FIG. 2B, and a first substrate 50 is formed to encapsulate the exposed end of the channel structure 30, as shown in FIG. 2C. Figure 4 Figure 5

[0072] In some embodiments, the step of removing the third substrate 10 can include back-thinning the third substrate 10 to expose an end surface of the channel structure 30 in the channel via that extends through the third substrate 10, and etching the end surface of the channel structure 30 to expose an end of the channel structure 30, as shown in FIG. 2B. Figure 4

[0073] In the above embodiments, the thinning process can be a chemical mechanical polishing (CMP) process, and the process conditions can be appropriately set according to the material of the third substrate 10, which will not be described herein.

[0074] In the above embodiments, a suitable etchant can be selected for wet etching according to the material of the third substrate 10 to expose an end of the channel structure 30.

[0075] In some embodiments, the step of forming the first substrate 50 includes covering the exposed surface of the gate stack structure 20 after removing the third substrate 10 with doped amorphous silicon to encapsulate the exposed end of the channel structure 30, and crystallizing the doped amorphous silicon using a laser anneal process to form a doped polysilicon layer, as shown in FIG. 2C. The process conditions of the laser anneal can be appropriately set according to the doping concentration of the amorphous silicon. Figure 5

[0076] ​​​​In some embodiments, after the step of forming the first substrate 50, the manufacturing method of the present disclosure can further include the step of: covering a buffer layer 60 on the surface of the first substrate 50, as shown in Figure 5 . The buffer layer 60 is used to prevent over-etching in the process of etching the isolation groove of the dielectric isolation structure 80 and the connection groove of the dielectric connection 90.

[0077] After the step of forming the first substrate 50 covering the end of the channel structure 30 and the conductive channel 40, the dielectric isolation structure 80 and the dielectric connection 90 are formed through the first substrate 50, as shown in Figure 6 and Figure 7 . Among them, Figure 6 shows a schematic diagram of the cross-sectional structure of the substrate after the above steps, Figure 7 is Figure 6 a schematic diagram of the top structure of the substrate, which exemplarily shows the connection relationship between the dielectric isolation structure 80 and the dielectric connection 90.

[0078] In some embodiments, the isolation groove and the connection groove are formed through the first substrate 50 at the same time, so that the isolation groove and the connection groove are located between the core area and the peripheral circuit area; the dielectric material is filled in the isolation groove and the connection groove to form the dielectric isolation structure 80 located in the isolation groove and the dielectric connection 90 located in the connection groove, as shown in Figure 6 and Figure 7 .

[0079] In the above embodiments, the contact hole can also be formed through the first substrate 50 at the position corresponding to the conductive channel 40 at the same time when the isolation groove and the connection groove are formed; the lead-out part 70 is formed in the contact hole, as shown in Figure 6 . Before the step of forming the lead-out part 70, an insulating material can also be covered on the sidewall of the contact hole to prevent the lead-out part from leaking.

[0080] The embodiment of the present disclosure also provides a three-dimensional memory 300, as shown in Figure 8 , which includes the above-mentioned memory structure 301 and a peripheral circuit 302 electrically connected to the above-mentioned memory structure 301.

[0081] The embodiment of the present disclosure also provides a storage system 400, as shown in Figure 9 , which includes a three-dimensional memory 401 configured to store data and a controller 402 coupled to the three-dimensional memory 401 and configured to control the three-dimensional memory 401, the three-dimensional memory 401 includes the above-mentioned memory structure, as shown in Figure 1 and Figure 2 , or the three-dimensional memory 401 is the above-mentioned three-dimensional memory 300, asFigure 8 as shown.

[0082] The embodiments of the present disclosure also provide an electronic device, comprising the memory structure described above.

[0083] In the embodiments of the present disclosure, the electronic device comprises at least one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, and a mobile power supply. In the embodiments, the memory structure of the present disclosure can be applied to any electronic device. Since the memory structure of the present disclosure reduces the defect-induced leakage problem and improves the reliability of the product, the performance of the electronic device using the memory structure is further improved. Figure 10 A structural schematic diagram of a mobile phone according to an embodiment of the present disclosure is shown in FIG. 5, which comprises a chip 600 using the memory structure of the present disclosure. Figure 10 As shown in FIG. 5, the mobile phone 500 comprises the chip 600 using the memory structure of the present disclosure.

[0084] From the above description, it can be seen that the embodiments of the present disclosure achieve the following technical effects:

[0085] Since the memory structure described above has a plurality of dielectric isolation structures arranged at intervals and connected through dielectric connection parts, in the case that the dielectric isolation structures are disconnected due to the photolithography process, the plurality of dielectric isolation structures are connected through the dielectric connection parts, which can achieve complete isolation of the core region and the peripheral circuit region, thereby reducing the defect-induced leakage problem and improving the reliability of the product.

[0086] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A memory structure, comprising: The memory structure comprises: a first substrate having a memory array on a surface thereof, the first substrate having a core region and a peripheral circuit region, the peripheral circuit region surrounding the core region, the memory array being located in the core region; a plurality of dielectric isolation structures spaced apart from each other, each of the dielectric isolation structures penetrating the first substrate between the core region and the peripheral circuit region, and each of the dielectric isolation structures surrounding the core region; a dielectric connection portion penetrating the first substrate, and the dielectric connection portion connecting adjacent dielectric isolation structures.

2. The memory structure of claim 1, wherein, The adjacent dielectric isolation structures are connected by a plurality of the dielectric connection portions.

3. The memory structure of claim 2, wherein, The core region has the dielectric connection portions on opposite sides thereof.

4. The memory structure of claim 2, wherein, The number of the dielectric connection portions on opposite sides of the core region is equal.

5. The memory structure of claim 2, wherein, The dielectric connection portions on opposite sides of the core region are symmetrically arranged.

6. The memory structure of claim 3, wherein, Adjacent dielectric isolation structures have a spacing region between the adjacent dielectric connection portions, and the spacing region has the same area in the orthographic projection on the surface of the first substrate.

7. The memory structure of claim 1, wherein, The number of the dielectric isolation structures is 2-3.

8. The memory structure of any one of claims 1-7, wherein, The memory structure further comprises: a conductive via arranged in the peripheral circuit region; and / or a lead-out portion penetrating the first substrate and connected with the conductive via.

9. The memory structure of any one of claims 1-7, wherein, The memory structure further comprises: a buffer layer arranged on a side of the first substrate away from the memory array, and the dielectric isolation structures penetrating the first substrate and the buffer layer.

10. A method of fabricating the memory structure of any one of claims 1 to 9, wherein, The memory structure comprises the following steps: providing a first substrate having a memory array on a surface thereof, the first substrate having a core region and a peripheral circuit region, the peripheral circuit region surrounding the core region, the memory array being located in the core region; penetrating a plurality of dielectric isolation structures in the first substrate between the core region and the peripheral circuit region, so that each of the dielectric isolation structures is spaced apart from each other and surrounds the core region; penetrating a dielectric connection portion in the first substrate, so that the dielectric connection portion connects adjacent dielectric isolation structures.

11. The method of manufacturing according to claim 10, wherein, The providing of the first substrate having a memory array on a surface thereof comprises: providing a third substrate having a memory array on a surface thereof, the memory array having a plurality of channel structures penetrating the third substrate; removing at least part of the third substrate, so that a side end of the channel structure is exposed; forming a doped polysilicon layer wrapping the exposed end of the channel structure.

12. A three-dimensional memory, comprising: The memory structure comprises: any one of claims 1-9; a peripheral circuit electrically connected with the memory structure.

13. A storage system comprising a controller and a three-dimensional memory configured to store data, the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory, characterized in that, The three-dimensional memory comprises the memory structure of any one of claims 1-9, or the three-dimensional memory is the three-dimensional memory of claim 12.

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