Transistor and method for manufacturing the same, display panel

Abstract

The embodiment of the present application provides a transistor and a preparation method thereof and a display panel, wherein the semiconductor thin film layer in the transistor is made of mixed materials of indium oxide and molybdenum oxide, compared with the prior art, the molybdenum oxide material is additionally added, the additional molybdenum oxide material increases the holes in the whole transistor, reduces the moving potential barrier of the holes, and further improves the electrical properties of the semiconductor thin film layer. And the semiconductor thin film layer in the transistor prepared by the transistor preparation method provided by the embodiment of the present application has high film density and few channel defects, further improving the electrical properties of the semiconductor thin film layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a transistor, a preparation method thereof and a display panel. BACKGROUND

[0002] Metal oxide semiconductor is an excellent channel material of thin film transistor (TFT), which has important applications in liquid crystal display (LCD), active-matrix organic light-emitting diode (AMOLED) and other emerging electronic applications (such as complementary metal oxide semiconductor (CMOS) and logic gate devices). Compared with traditional silicon-based thin film transistors, metal oxide thin film transistors are widely studied due to their high mobility, low-temperature synthesis process, good stability and high optical transmittance.

[0003] Most oxide semiconductors used in TFTs are prepared by using a vacuum deposition process, but there is a problem of low electrical performance due to the difficulty in preparing a dense film during preparation. SUMMARY

[0004] The embodiments of the present application provide a transistor, a preparation method thereof and a display panel, and aim to solve the problem of low electrical performance of the transistor in the prior art.

[0005] In a first aspect, the embodiments of the present application provide a transistor, which comprises:

[0006] a gate layer;

[0007] a semiconductor thin film layer, which is arranged above the gate layer, and a preparation material of the semiconductor thin film layer comprises indium oxide and molybdenum oxide.

[0008] In a possible embodiment, the transistor is a multi-film layer structure, the multi-film layer structure comprises a first sub-film layer made of indium oxide material and a second sub-film layer made of molybdenum oxide material, and the first sub-film layer and the second sub-film layer are arranged alternately.

[0009] In a possible embodiment, the multi-film layer structure in the transistor is a film layer with adjustable thickness.

[0010] In a possible embodiment, the thickness of the semiconductor thin film layer is 12-15 nanometers.

[0011] In a possible embodiment, the transistor further includes a source-drain layer disposed above the semiconductor thin film layer.

[0012] In a second aspect, the embodiments of the present application further provide a transistor preparation method, which includes:

[0013] providing a gate layer;

[0014] coating a mixed solution of indium oxide and molybdenum oxide above the gate layer to obtain the semiconductor thin film layer;

[0015] preparing a source-drain layer above the semiconductor thin film layer.

[0016] In a possible embodiment, the coating of the mixed solution of indium oxide and molybdenum oxide above the gate layer to obtain the semiconductor thin film layer includes:

[0017] spinning the mixed solution of indium oxide and molybdenum oxide above the gate layer to obtain a first semiconductor thin film layer;

[0018] performing a first annealing on the first semiconductor thin film layer to obtain a second semiconductor thin film layer;

[0019] performing a second annealing on the second semiconductor thin film layer by using a plasma gas to obtain the semiconductor thin film layer.

[0020] In a possible embodiment, before the spinning of the mixed solution of indium oxide and molybdenum oxide above the gate layer to obtain the first semiconductor thin film layer, the method further includes:

[0021] obtaining a first concentration of indium oxide solution and a second concentration of molybdenum oxide solution;

[0022] mixing the indium oxide solution and the molybdenum oxide solution according to a molar mass ratio of 2:1 to obtain the mixed solution of indium oxide and molybdenum oxide.

[0023] In a possible embodiment, the performing of the second annealing on the second semiconductor thin film layer by using the plasma gas to obtain the semiconductor thin film layer includes:

[0024] performing a plasma gas annealing on the second semiconductor thin film by using oxygen under a vacuum condition to obtain the semiconductor thin film.

[0025] In a third aspect, the embodiments of the present application further provide a display panel, which includes the transistor prepared by the transistor preparation method according to any one of the above.

[0026] The embodiment of the present application provides a transistor and a preparation method and a display panel, the semiconductor thin film layer in the transistor is made of mixed materials of indium oxide and molybdenum oxide, compared with the prior art, the molybdenum oxide material is added, the additional molybdenum oxide material increases the holes in the whole transistor, reduces the moving potential barrier of the holes, and further improves the electrical properties of the semiconductor thin film layer. And the semiconductor thin film layer of the transistor prepared by the transistor preparation method provided by the embodiment of the present application has high film density and few channel defects, further improving the electrical properties of the semiconductor thin film layer. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Figure 1 An embodiment structure schematic diagram of the transistor provided by the present application is provided.

[0029] Figure 2 Another embodiment structure schematic diagram of the transistor provided by the present application is provided.

[0030] Figure 3 Another embodiment structure schematic diagram of the transistor provided by the present application is provided.

[0031] Figure 4 Another embodiment structure schematic diagram of the transistor provided by the present application is provided.

[0032] Figure 5 An embodiment flow schematic diagram of the transistor preparation method provided by the present application is provided.

[0033] Figure 6 An embodiment flow schematic diagram of the preparation of the semiconductor thin film layer provided by the present application is provided. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0035] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0036] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0037] This application provides a transistor and its fabrication method, as well as a display panel, which will be described below.

[0038] like Figure 1 The diagram shown is a schematic representation of a transistor structure according to an embodiment of this application. Figure 1 In this application embodiment, the transistor includes a gate layer 10 and a semiconductor thin film layer 20 stacked together; wherein, the semiconductor thin film layer 20 is disposed above the gate layer 10, and normally the semiconductor thin film layer 20 completely covers the gate layer 10.

[0039] In the embodiments of this application, the gate layer is mainly made of silicon oxide material (SiOx), specifically silicon dioxide (SiOx). In other embodiments, other silicon oxide materials or a mixture of multiple silicon oxide materials can be used to prepare the gate layer 10 in the embodiments of this application.

[0040] The semiconductor thin film layer 20 is arranged above the gate layer 10, and the semiconductor thin film layer 20 is prepared from molybdenum oxide and indium oxide; that is, the semiconductor thin film layer is prepared from molybdenum oxide and indium oxide. The semiconductor thin film layer 20 in the prior art usually only includes indium oxide, which leads to poor electrical performance of the semiconductor thin film layer 20.

[0041] The semiconductor thin film layer in the transistor is made of a mixed material of indium oxide and molybdenum oxide, compared with the prior art, the molybdenum oxide material is added, the additional molybdenum oxide material increases the holes in the whole transistor, reduces the moving potential barrier of the holes, and further improves the electrical properties of the semiconductor thin film layer. The semiconductor thin film layer in the transistor prepared by the transistor preparation method provided in the embodiment has high film density and few channel defects, and the electrical properties of the semiconductor thin film layer are further improved.

[0042] The transistor in the embodiment adds the molybdenum oxide material to the semiconductor thin film layer 20 on the basis of the prior art, and the material for preparing the semiconductor thin film layer 20 is the indium oxide plus the molybdenum oxide material. The characteristics of the molybdenum oxide material increase the holes in the semiconductor thin film layer 20 and reduce the moving potential barrier of the holes, thereby improving the electrical properties of the semiconductor thin film layer 20.

[0043] Meanwhile, the transistor provided in the embodiment further includes a source-drain layer 30 arranged above the semiconductor thin film layer. The method and material for preparing the source-drain layer in the embodiment can refer to the prior art, which is not limited herein.

[0044] In one specific embodiment, the source-drain layer 30 can be prepared from aluminum (AL).

[0045] In the embodiment, the thickness of the semiconductor thin film layer 20 prepared from the indium oxide and the molybdenum oxide material can be 12 nanometers (um)-15 nanometers (um). The thickness of the gate layer 10 is much greater than the thickness of the semiconductor thin film layer 20.

[0046] In the above embodiment, the thickness of the source-drain layer 30 is usually greater than the thickness of the semiconductor thin film layer 20, and the thickness of the source-drain layer 30 is less than the thickness of the gate layer 10. However, the thicknesses of the gate layer 10, the semiconductor thin film layer 20 and the source-drain layer 30 can be changed according to actual needs.

[0047] In one specific embodiment, the thickness of the gate layer can be 580 micrometers (um)-650 micrometers (um), the thickness of the semiconductor thin film layer can be 12 nanometers (um)-15 nanometers (um), and the thickness of the source-drain layer can be 80 micrometers-120 micrometers.

[0048] As shown in Figure 2 FIG. 2, another embodiment structure of a transistor provided by the present application is shown. In the embodiment shown in Figure 2 the transistor also includes a gate layer 10, a semiconductor thin film layer 20 disposed above the gate layer 10, and a source-drain layer 30 disposed above the semiconductor thin film layer 20.

[0049] However Figure 2 the semiconductor thin film layer 20 in the embodiment shown in FIG. 2 has a multi-film layer structure from top to bottom, i.e., the semiconductor thin film layer 20 includes a plurality of film layers made of different materials and stacked one on another. Specifically, the semiconductor thin film layer 20 can include a first sub-film layer 201 made of indium oxide material and a second sub-film layer 202 made of molybdenum oxide material; and the first sub-film layer 201 and the second sub-film layer 202 in the semiconductor thin film layer 20 are alternately arranged along the vertical direction.

[0050] In some embodiments, the second sub-film layer 202 made of molybdenum oxide material can be multiple, and the multiple second sub-film layers are respectively disposed on both sides of the first sub-film layer 201. Some of the second sub-film layers 202 can be connected with the gate layer 10, while some of the second sub-film layers 202 can be connected with the source-drain layer 30, and the first sub-film layer 201 is disposed between the multiple second sub-film layers 202.

[0051] Please refer to Figure 2 , Figure 2 which includes one first sub-film layer 201 and two second sub-film layers 202, the first sub-film layer 201 is disposed between the two second sub-film layers 202, and the first sub-film layer 201 and the two second sub-film layers 202 are stacked one on another from top to bottom. The semiconductor thin film layer 20 thus arranged has the material changed to the molybdenum oxide material with better electrical performance at the interface with other film layer structures, thereby reducing the hole movement potential barrier between different film layer structures.

[0052] Of course, in other embodiments, the semiconductor thin film layer 20 can also include multiple first sub-film layers 201 and multiple second sub-film layers 202, and the arrangement order of the multiple first sub-film layers 201 and the multiple second sub-film layers 202 can be adjusted according to actual conditions, which is not limited in the embodiments of the present application.

[0053] As shown in Figure 3 FIG. 3, another embodiment structure of a transistor provided by the present application is shown. In the embodiment shown in Figure 3 the transistor also includes a gate layer 10, a semiconductor thin film layer 20 disposed above the gate layer 10, and a source-drain layer 30 disposed above the semiconductor thin film layer 20.

[0054] However Figure 3In the embodiment shown, the semiconductor thin film layer 20 is still a multi-film layer structure, i.e., the semiconductor thin film layer 20 still includes multiple film layers made of different materials. Figure 3 The multi-film layer structure in the embodiment shown is arranged in the order from left to right. At this time, the thickness of the multi-film layer structure constituting the semiconductor thin film 20 is the same in the vertical direction, but the width can be adjusted in the horizontal direction.

[0055] In Figure 3 In the embodiment shown, the semiconductor thin film layer 20 can also include a first sub-film layer 201 made of indium oxide material and a second sub-film layer 202 made of molybdenum oxide material; and the first sub-film layer 201 and the second sub-film layer 202 in the semiconductor thin film layer 20 are arranged alternately in the horizontal direction.

[0056] In one specific embodiment, the semiconductor thin film layer 20 can include two first sub-film layers 201 made of indium oxide material and one second sub-film layer 202 made of molybdenum oxide material; at this time, the second sub-film layer 202 is sandwiched between the two first sub-film layers 201 in the horizontal direction, and in the horizontal direction, the width of the second sub-film layer 202 is greater than the distance between the source level and the drain level in the source-drain layer 30 (including the width of the source level and the drain level in the horizontal direction). In this way, the part of the semiconductor thin film layer corresponding to the source level and the drain level is made of indium oxide material, which improves the concentration of holes between the source level, the drain level and the semiconductor thin film layer, and reduces the moving potential barrier of the holes.

[0057] As Figure 4 The embodiment shown provides another embodiment structure of the transistor. In Figure 4 In the embodiment shown, the semiconductor thin film layer 20 can also include three first sub-film layers 201 and two second sub-film layers 202, and the three first sub-film layers 201 and the two second sub-film layers 202 are also arranged in the horizontal direction.

[0058] Among them, the two second sub-film layers 202 are arranged corresponding to the source level and the drain level in the source-drain layer 30 respectively; a first sub-film layer 201 is also sandwiched between the two second sub-film layers 202, and the remaining two first sub-film layers are located at the leftmost side and the rightmost side of the entire semiconductor thin film layer 20 respectively.

[0059] In Figure 4 In the embodiment shown, the semiconductor thin film layer 20 corresponding to the source level and the drain level in the source-drain layer 30 is the second sub-film layer 202 made of molybdenum oxide material, which improves the concentration of holes between the source level, the drain level and the semiconductor thin film layer, and reduces the moving potential barrier of the holes.

[0060] It should be noted that when the semiconductor thin film layer 20 includes a multi-film layer structure, the thickness of the multiple film layers in the semiconductor thin film layer in the vertical direction or the width in the horizontal direction can be adjusted according to actual conditions. Generally, the larger the volume occupied by the molybdenum oxide material, the better the electrical performance of the semiconductor thin film layer. When multiple film layers are provided, the second sub-film layer 202 made of the molybdenum oxide material is generally required to correspond to the source level and the drain level in the source and drain layer 30.

[0061] It should be noted that the indium oxide and molybdenum oxide materials provided in the embodiments of the present application can also be replaced by other materials that can improve the electrical performance, which is not limited herein.

[0062] The embodiments of the present application also provide a preparation method of a transistor, as shown in Figure 5 The preparation method of the transistor provided in the embodiments of the present application can include the following steps, as shown in the flowchart of an embodiment of the preparation method of the transistor provided in the embodiments of the present application.

[0063] 51. Providing a gate layer.

[0064] The gate layer is mainly made of silicon oxide material (SiOx), and can be made of silicon dioxide (SiOx) material. In other embodiments, other silicon oxide materials or a mixture of multiple silicon oxide materials can be used to prepare the gate layer 10 in the embodiments of the present application. The specific method for preparing the gate layer 10 can refer to the prior art, which is not limited herein.

[0065] 52. Coating a mixed solution of indium oxide and molybdenum oxide on the gate layer to prepare a semiconductor thin film layer.

[0066] In the embodiments of the present application, the semiconductor thin film layer 20 is prepared from indium oxide and molybdenum oxide materials, and the molybdenum oxide material is added. The added molybdenum oxide material increases the concentration of holes in the semiconductor thin film layer 20 and reduces the moving potential barrier of the holes between different film layers.

[0067] 53. Preparing a source and drain layer on the semiconductor thin film layer.

[0068] The preparation method of the transistor provided in the embodiments of the present application is made of a mixture of indium oxide and molybdenum oxide in the semiconductor thin film layer of the transistor. Compared with the prior art, the molybdenum oxide material is additionally added, the additional molybdenum oxide material increases the holes in the entire transistor, reduces the moving potential barrier of the holes, and further improves the electrical properties of the semiconductor thin film layer. The semiconductor thin film layer of the transistor prepared by the preparation method of the transistor provided in the embodiments of the present application has high film density and few channel defects, which further improves the electrical properties of the semiconductor thin film layer.

[0069] As shown in Figure 6The diagram shown is a schematic flowchart of an embodiment of the preparation of a semiconductor thin film layer provided in this application. The semiconductor thin film layer is prepared by coating a mixed solution of different materials over a gate layer, and may include:

[0070] 61. A mixed solution of indium oxide and molybdenum oxide is spin-coated over the gate layer to obtain the first semiconductor thin film layer.

[0071] In the embodiments of this application, before spin-coating the mixed solution of indium oxide and molybdenum oxide over the gate layer, it is necessary to prepare the mixed solution of indium oxide and molybdenum oxide.

[0072] Specifically, an indium oxide solution of a first concentration and a molybdenum oxide solution of a second concentration can be obtained; the indium oxide solution of the first concentration and the molybdenum oxide solution of the second concentration are mixed at a molar mass ratio of 2:1 to obtain a mixed solution of indium oxide and molybdenum oxide.

[0073] In the above embodiments, an indium oxide solution of the first concentration and a molar molybdenum oxide solution of the second concentration are mixed at a molar mass ratio of 2:1. In other embodiments, indium oxide and molybdenum oxide solutions of different molar mass ratios can be mixed according to the different transistor fabrication requirements; and the concentrations of the indium oxide and molybdenum oxide solutions themselves can also be adjusted. This application does not impose any limitations on these embodiments.

[0074] After preparing the mixed solution of indium oxide and molybdenum oxide, the mixed solution of indium oxide and molybdenum oxide needs to be spin-coated onto the gate layer 10 to prepare the semiconductor thin film layer 20. At this time, the semiconductor thin film layer 20 is a whole, and the materials in the semiconductor thin film layer include indium oxide and molybdenum oxide.

[0075] Of course, in some other embodiments, the indium oxide solution and molybdenum oxide solution may not be mixed. Instead, the indium oxide solution and molybdenum oxide solution may be directly used for multiple spin coatings to obtain multiple film layer structures made of different materials. In this case, the semiconductor thin film layer 20 is a multi-film layer structure, and the semiconductor thin film layer 20 also includes a first sub-film layer 201 made of indium oxide material and a second sub-film layer 202 made of molybdenum oxide material.

[0076] Please refer to the details. Figure 2 ,exist Figure 2 The semiconductor thin film layer 20 includes multiple film layer structures stacked from top to bottom. Specifically, it can be a first sub-film layer 201 made of indium oxide and two second sub-film layers 202 made of molybdenum oxide; and the first sub-film layer 201 is sandwiched between the two second sub-film layers 202, and the two second sub-film layers are respectively connected to the source / drain layer 30 and the gate layer 10.

[0077] At this time, the semiconductor thin film layer can be prepared by spin coating the first concentration of indium oxide solution on the gate layer 10 to obtain a second sub-film layer 202; spin coating the second concentration of molybdenum oxide solution on the second sub-film layer 202 to obtain a first sub-film layer 201; and spin coating the first concentration of indium oxide solution on the first sub-film layer 201 to obtain a second sub-film layer 202. At this time, the second sub-film layer has a three-layer structure, and the second sub-film layer comprises the second sub-film layer, the first sub-film layer, and the second sub-film layer arranged in a stack from top to bottom.

[0078] In this way, the source and drain layer 30 and the gate layer 10 are still in contact with the indium oxide material with better electrical performance, thereby improving the overall electrical performance of the transistor.

[0079] In the above embodiment, the thickness of the entire semiconductor thin film layer 20 is 12-15 nm; even if the semiconductor thin film layer 20 comprises a multi-film layer structure, the thickness of each sub-film layer can be adjusted so that the thickness of the entire semiconductor thin film layer 20 is within the range of 12-15 nm.

[0080] In the embodiments of the present application, the rotation speed during spin coating is generally 1500-3000 rpm; and the thickness of the coated film layer can be adjusted by adjusting the rotation speed.

[0081] 62. Primary annealing the first semiconductor thin film layer to obtain a second semiconductor thin film layer.

[0082] 63. Secondary annealing the second semiconductor thin film layer by using plasma gas to obtain a semiconductor thin film layer.

[0083] After the mixed solution is spin coated on the gate layer 10 to obtain the semiconductor thin film layer 20, the annealing treatment of the spin-coated film layer is also needed. In the embodiments of the present application, two annealing treatments are needed to obtain the final semiconductor thin film layer 20.

[0084] Specifically, the spin-coated first semiconductor thin film layer can be annealed at a temperature of 230-260°C for 2-4 hours to obtain a second semiconductor thin film layer after primary annealing; and the second semiconductor thin film layer is subjected to secondary annealing treatment by plasma gas.

[0085] Among them, the secondary annealing treatment of the second semiconductor thin film layer can be performed by using oxygen (O2) plasma method. It should be noted that the secondary annealing treatment needs to be performed in a vacuum environment.

[0086] In the embodiments of the present application, the specific process steps of spin coating the mixed solution of indium oxide and molybdenum oxide and annealing can refer to the prior art, which is not limited here.

[0087] The embodiment of the present application further provides a display panel, which comprises the transistor prepared by the preparation method of the transistor.

[0088] As shown in Figure 1 , it is a structural schematic diagram of an embodiment of the transistor provided by the embodiment of the present application. In Figure 1 , the transistor provided by the embodiment of the present application comprises a gate layer 10 and a semiconductor thin film layer 20 which are arranged in a stack; wherein the semiconductor thin film layer 20 is arranged above the gate layer 10, and in general, the semiconductor thin film layer 20 completely covers the gate layer 10.

[0089] In the embodiment of the present application, the gate layer is mainly made of silicon oxide material (SiOx), and specifically, can be made of silicon dioxide (SiOx) material. In other embodiments, other silicon oxide materials or a plurality of silicon oxide materials can be mixed to prepare the gate layer 10 in the embodiment of the present application.

[0090] The semiconductor thin film layer 20 is arranged above the gate layer 10, and the preparation material of the semiconductor thin film layer 20 comprises molybdenum oxide and indium oxide; that is, the semiconductor thin film layer is prepared by molybdenum oxide material and indium oxide material. The semiconductor thin film layer 20 in the prior art usually only comprises indium oxide material, which leads to poor electrical performance of the semiconductor thin film layer 20.

[0091] The transistor in the embodiment of the present application adds molybdenum oxide material to the semiconductor thin film layer 20 on the basis of the prior art, and the material for preparing the semiconductor thin film layer 20 is indium oxide plus molybdenum oxide material. The characteristics of the molybdenum oxide material increase the holes in the semiconductor thin film layer 20, reduce the moving potential barrier of the holes, and thus improve the electrical characteristics of the semiconductor thin film layer 20.

[0092] Meanwhile, the transistor provided by the embodiment of the present application further comprises a source-drain layer 30, which is arranged above the semiconductor thin film layer. The method and material for preparing the source-drain layer in the embodiment of the present application can refer to the prior art, which is not limited here.

[0093] In a specific embodiment, aluminum (AL) can be used to prepare the source-drain layer 30.

[0094] In the embodiment of the present application, the thickness of the semiconductor thin film layer 20 prepared by the indium oxide and molybdenum oxide material can be 12 nanometers (um)-15 nanometers (um). The thickness of the gate layer 10 is much greater than the thickness of the semiconductor thin film layer 20.

[0095] In the above embodiments, the thickness of the source-drain layer 30 is also generally greater than the thickness of the semiconductor thin film layer 20, and the thickness of the source-drain layer 30 is less than the thickness of the gate layer 10. However, the thicknesses of the gate layer 10, the semiconductor thin film layer 20 and the source-drain layer 30 can be changed according to actual requirements.

[0096] In one specific embodiment, the thickness of the gate layer can be 580 micrometers (um) - 650 micrometers (um), the thickness of the semiconductor thin film layer can be 12 nanometers (um) - 15 nanometers (um), and the thickness of the source-drain layer can be 80 micrometers - 120 micrometers.

[0097] As shown in FIG. 1, a schematic diagram of another embodiment structure of a transistor provided by the present application is shown. In the embodiment shown in FIG. 1, the transistor also includes a gate layer 10, a semiconductor thin film layer 20 disposed above the gate layer 10, and a source-drain layer 30 disposed above the semiconductor thin film layer 20. Figure 2 As shown in FIG. 1, a schematic diagram of another embodiment structure of a transistor provided by the present application is shown. In the embodiment shown in FIG. 1, the transistor also includes a gate layer 10, a semiconductor thin film layer 20 disposed above the gate layer 10, and a source-drain layer 30 disposed above the semiconductor thin film layer 20. Figure 2 However, as shown in FIG. 2, the semiconductor thin film layer 20 in the embodiment shown in FIG. 2 is a multi-film layer structure from top to bottom, i.e., the semiconductor thin film layer 20 includes a plurality of film layers made of different materials that are stacked. Specifically, the semiconductor thin film layer 20 can include a first sub-film layer 201 made of indium oxide material and a second sub-film layer 202 made of molybdenum oxide material; and the first sub-film layer 201 and the second sub-film layer 202 in the semiconductor thin film layer 20 are alternately arranged along the vertical direction.

[0098] Figure 2 However, as shown in FIG. 2, the semiconductor thin film layer 20 in the embodiment shown in FIG. 2 is a multi-film layer structure from top to bottom, i.e., the semiconductor thin film layer 20 includes a plurality of film layers made of different materials that are stacked. Specifically, the semiconductor thin film layer 20 can include a first sub-film layer 201 made of indium oxide material and a second sub-film layer 202 made of molybdenum oxide material; and the first sub-film layer 201 and the second sub-film layer 202 in the semiconductor thin film layer 20 are alternately arranged along the vertical direction.

[0099] In some embodiments, the second sub-film layer 202 made of molybdenum oxide material can be multiple, and the multiple second sub-film layers are respectively disposed on both sides of the first sub-film layer 201. Some of the second sub-film layers 202 can be connected with the gate layer 10, and some of the second sub-film layers 202 can be connected with the source-drain layer 30, and the first sub-film layer 201 is disposed between the multiple second sub-film layers 202.

[0100] As shown in FIG. 2, the semiconductor thin film layer 20 includes a first sub-film layer 201 and two second sub-film layers 202, the first sub-film layer 201 is disposed between the two second sub-film layers 202, and the first sub-film layer 201 and the two second sub-film layers 202 are stacked from top to bottom. The semiconductor thin film layer 20 thus arranged has the material at the junction with other film layer structures changed to molybdenum oxide material with better electrical performance, reducing the hole moving potential barrier between different film layer structures. Figure 2 Figure 2 As shown in FIG. 2, the semiconductor thin film layer 20 includes a first sub-film layer 201 and two second sub-film layers 202, the first sub-film layer 201 is disposed between the two second sub-film layers 202, and the first sub-film layer 201 and the two second sub-film layers 202 are stacked from top to bottom. The semiconductor thin film layer 20 thus arranged has the material at the junction with other film layer structures changed to molybdenum oxide material with better electrical performance, reducing the hole moving potential barrier between different film layer structures.

[0101] ​​Of course, in other embodiments, the semiconductor thin film layer 20 can also include a plurality of first sub-film layers 201 and a plurality of second sub-film layers 202, and the arrangement order of the plurality of first sub-film layers 201 and the plurality of second sub-film layers 202 can be adjusted according to actual conditions, which is not limited in the embodiments of the present application.

[0102] As shown in FIG. 2, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 3 As shown in FIG. 2, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 3 As shown in FIG. 2, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided.

[0103] However, as shown in FIG. 3, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 3 However, as shown in FIG. 3, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 3 As shown in FIG. 3, the multi-film layer structure in the embodiment is arranged in the order from left to right. At this time, the thickness of the multi-film layer structure constituting the semiconductor thin film 20 in the vertical direction is the same, but the width in the horizontal direction can be adjusted.

[0104] As shown in FIG. 4, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 3 As shown in FIG. 4, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided.

[0105] In a specific embodiment, the semiconductor thin film layer 20 can include two first sub-film layers 201 made of indium oxide material, and one second sub-film layer 202 made of molybdenum oxide material; at this time, the second sub-film layer 202 is sandwiched between the two first sub-film layers 201 along the horizontal direction, and along the horizontal direction, the width of the second sub-film layer 202 is greater than the distance between the source level and the drain level in the source-drain layer 30 (including the width of the source level and the drain level in the horizontal direction). In this way, the part of the semiconductor thin film layer corresponding to the source level and the drain level is made of indium oxide material, which improves the concentration of holes between the source level, the drain level and the semiconductor thin film layer, and reduces the moving potential barrier of the holes.

[0106] As shown in FIG. 5, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 4 As shown in FIG. 5, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided. Figure 4 As shown in FIG. 5, another embodiment structure schematic diagram of the transistor provided by the embodiments of the present application is provided.

[0107] Two second sub-film layers 202 are respectively disposed corresponding to the source and drain electrodes in the source-drain layer 30; a first sub-film layer 201 is also sandwiched between the two second sub-film layers 202, and the remaining two first sub-film layers are located at the leftmost and rightmost edges of the entire semiconductor thin film layer 20.

[0108] exist Figure 4 In the embodiment shown, the semiconductor thin film layer 20 corresponding to the source and drain in the source-drain layer 30 is a second sub-film layer 202 made of molybdenum oxide material, which increases the hole concentration between the source, drain and semiconductor thin film layers and reduces the hole movement barrier.

[0109] It should be noted that when the semiconductor thin film layer 20 comprises a multi-layer structure, the thickness of the multiple layers in the vertical direction or the width in the horizontal direction can be adjusted according to the actual situation. Generally, the larger the volume occupied by the molybdenum oxide material, the better the electrical performance of the semiconductor thin film layer. Furthermore, when multiple layers are set, it is usually necessary to correspond the second sub-film layer 202 made of molybdenum oxide material to the source and drain electrodes in the source and drain layers 30.

[0110] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0111] In practice, each of the above units or structures can be implemented as an independent entity or can be arbitrarily combined to be implemented as the same or several entities. For the specific implementation of each of the above units or structures, please refer to the previous method embodiments, which will not be repeated here.

[0112] The present invention has provided a detailed description of a transistor, its fabrication method, and a display panel. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A transistor, comprising: The transistor comprises: a gate layer; a semiconductor thin film layer disposed above the gate layer, and a material of the semiconductor thin film layer comprising indium oxide and molybdenum oxide, the semiconductor thin film layer comprising a first sub-film layer made of indium oxide material and a second sub-film layer made of molybdenum oxide material, the first sub-film layer and the second sub-film layer being alternately arranged in a horizontal direction, and the semiconductor thin film layer corresponding to the source and the drain in the source-drain layer being the second sub-film layer made of molybdenum oxide material.

2. The transistor of claim 1, wherein The multi-film layer structure in the transistor is a film layer with adjustable thickness.

3. The transistor of claim 1, wherein The thickness of the semiconductor thin film layer is 12-15 nm.

4. The transistor of claim 1, wherein The transistor further comprises a source-drain layer disposed above the semiconductor thin film layer.

5. A method of fabricating a transistor, comprising: The method comprises: providing a gate layer; coating an indium oxide solution and a molybdenum oxide solution above the gate layer to prepare a semiconductor thin film layer, the semiconductor thin film layer comprising a first sub-film layer made of indium oxide material and a second sub-film layer made of molybdenum oxide material, the first sub-film layer and the second sub-film layer being alternately arranged in a horizontal direction, and the semiconductor thin film layer corresponding to the source and the drain in the source-drain layer being the second sub-film layer made of molybdenum oxide material; preparing a source-drain layer above the semiconductor thin film layer.

6. The method of claim 5, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a metal oxide. The coating of the mixed solution of indium oxide and molybdenum oxide above the gate layer to prepare the semiconductor thin film layer comprises: spin-coating the mixed solution of indium oxide and molybdenum oxide above the gate layer to obtain a first semiconductor thin film layer; primary annealing the first semiconductor thin film layer to obtain a second semiconductor thin film layer; secondary annealing the second semiconductor thin film layer by using plasma gas to obtain the semiconductor thin film layer.

7. The method of claim 6, wherein the step of forming the gate electrode is performed by a method selected from the group consisting of sputtering, vacuum deposition, and ion plating. Before the spin-coating of the mixed solution of indium oxide and molybdenum oxide above the gate layer to obtain a first semiconductor thin film layer, the method further comprises: obtaining an indium oxide solution with a first concentration and a molybdenum oxide solution with a second concentration; mixing the indium oxide solution and the molybdenum oxide solution according to a molar mass ratio of 2:1 to obtain the mixed solution of indium oxide and molybdenum oxide.

8. The method of claim 7, wherein the step of forming the gate electrode is performed by a method comprising: The secondary annealing of the second semiconductor thin film layer by using plasma gas to obtain the semiconductor thin film layer comprises: annealing the second semiconductor thin film by using oxygen plasma gas under vacuum conditions to obtain the semiconductor thin film.

9. A display panel, characterized by, The display panel comprises the transistor prepared by the transistor preparation method according to any one of claims 5-8.

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