Current regulating circuit and DC-DC converter

Abstract

The application provides a current regulating circuit and a DC-DC converter, the DC-DC converter comprising: an input unit, an output unit, an output feedback unit, an error amplification unit and the current regulating circuit; one end of a monitoring module in the current regulating circuit is connected with an output end of the input unit, the other end is connected with an input end of the output feedback unit, and an output end of the current regulating circuit is connected with one input end of the error amplification unit; and an output end of the output feedback unit is connected with an input end of the output unit and the other input end of the error amplification unit respectively. A current regulating circuit is added in the circuit of the DC-DC converter, the stability of the output of the error amplification unit is accelerated through the current feedback of the current regulating circuit, so that the purpose of improving the output efficiency of the DC-DC is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit, in particular to a current regulating circuit and a DC-DC converter. BACKGROUND

[0002] DC-DC (Direct Current to Direct Current) is widely used in various electronic products as a power module, providing stable working voltage for its subsequent circuit and high efficiency. In the application link, users care more about the stability of DC-DC and its output efficiency. When the output load of DC-DC changes, the output switch of DC-DC needs to adjust the size of the output current. In this process, the output of DC-DC needs a settling time for this adjustment.

[0003] The current DC-DC converter has a long settling time of DC-DC output, so it is necessary to provide a more effective and reliable technical solution. SUMMARY

[0004] The present application provides a current regulating circuit and a DC-DC converter. A current regulating circuit is added in the circuit of the DC-DC converter. The current feedback of the current regulating circuit accelerates the stability of the output of the error amplifier unit, thereby achieving the purpose of improving the output efficiency of DC-DC.

[0005] One aspect of the present application provides a current regulating circuit, comprising: a monitoring module connected to a to-be-monitored circuit; an amplifier, an input end of the amplifier being connected to an output end of the monitoring module, capable of amplifying an output voltage of the monitoring module and outputting an amplified voltage; a comparator, an input end of the comparator being connected to an output end of the amplifier, capable of outputting according to the amplified voltage; a control module, an input end of the control module being connected to an output end of the comparator, capable of outputting a control voltage according to the output of the comparator; and an output module, an input end of the output module being connected to an output end of the control module, capable of outputting according to the control voltage.

[0006] In some embodiments of the present application, the monitoring module comprises a monitoring resistor and a voltage dividing resistor.

[0007] In some embodiments of the present application, the amplifier comprises: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube; the source of the first PMOS tube is connected to AVDD, the drain of the first PMOS tube is respectively connected to the source of the second PMOS tube and the source of the third PMOS tube; the gates of the second PMOS tube and the third PMOS tube are respectively two input terminals of the amplifier, the drain of the third PMOS tube is an output terminal of the amplifier; the drain of the second PMOS tube is connected to the gate and the drain of the first NMOS tube and the gate of the second NMOS tube, the source of the first NMOS tube is connected to ground; the drain of the third PMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is connected to ground.

[0008] In some embodiments of the present application, the comparator comprises: an input module, one input terminal of the input module is connected to the output terminal of the amplifier, and the other input terminal is connected to a reference voltage; a shaping module, the input terminal of the shaping module is connected to the output terminal of the input module, and the output terminal of the shaping module is an output terminal of the comparator.

[0009] In some embodiments of the present application, the input module comprises: a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube; the gate of the fourth PMOS tube is connected to the output terminal of the amplifier, and the gate of the fifth PMOS tube is connected to a reference voltage; the drain of the fourth PMOS tube is connected to the gate and the drain of the third NMOS tube and the gate of the fourth NMOS tube, and the source of the third NMOS tube is connected to ground; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is connected to ground.

[0010] In some embodiments of the present application, the shaping module comprises: a sixth PMOS tube, a seventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube; the source of the sixth PMOS tube is connected to AVDD, and the drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube and the gates of the seventh PMOS tube and the sixth NMOS tube; the source of the seventh PMOS tube is connected to AVDD, and the drain of the seventh PMOS tube is connected to the drain of the sixth NMOS tube; the source of the fifth NMOS tube is connected to ground, and the source of the sixth NMOS tube is connected to ground.

[0011] In some embodiments of the present application, the control module comprises at least one control circuit, the control circuit comprising: an eighth PMOS tube, a seventh NMOS tube; the gate of the eighth PMOS tube and the seventh NMOS tube is connected to the output terminal of the comparator; the source of the eighth PMOS tube is connected to AVDD, and the drain of the eighth PMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is connected to AVSS.

[0012] In some embodiments of the present application, the output module comprises at least one PMOS output switch, which is controlled by the control voltage output by the control module.

[0013] Another aspect of the present application provides a DC-DC converter, comprising: an input unit, an output unit, an output feedback unit, an error amplification unit, and a current regulating circuit as described above; one end of the monitoring module in the current regulating circuit is connected to the output terminal of the input unit, and the other end is connected to the input terminal of the output feedback unit, and the output terminal of the current regulating circuit is connected to one input terminal of the error amplification unit; the output terminal of the output feedback unit is respectively connected to the input terminal of the output unit and the other input terminal of the error amplification unit.

[0014] In some embodiments of the present application, the DC-DC converter further comprises: a comparison unit, a PWM unit, and a feedback circuit; one input terminal of the comparison unit is connected to the output terminal of the feedback circuit, and the second input terminal is connected to the output terminal of the error amplification unit; the input terminal of the PWM unit is connected to the output terminal of the comparison unit, and the output terminal of the PWM is connected to the input unit; the input terminal of the feedback circuit is connected to the output terminal of the input unit.

[0015] The current regulating circuit and the DC-DC converter disclosed in the present application add a current regulating circuit in the circuit of the DC-DC converter, accelerate the stabilization of the output of the error amplification unit through the current feedback of the current regulating circuit, so as to achieve the purpose of improving the output efficiency of the DC-DC. BRIEF DESCRIPTION OF DRAWINGS

[0016] The following drawings describe the exemplary embodiments disclosed in the present application in detail. The same reference signs in the several views of the drawings represent similar structures. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other ways of embodiments can also achieve the same purpose of the invention in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0017] Figure 1 is a schematic diagram of a DC-DC converter;

[0018] Figure 2 This is a graph showing the voltage change at the output terminal of a DC-DC converter when the current load changes by 50mA.

[0019] Figure 3 This is a circuit diagram of the first part of the current regulation circuit described in the embodiments of this application;

[0020] Figure 4 This is a second part of the circuit diagram of the current regulation circuit described in the embodiments of this application;

[0021] Figure 5 This is a third part of the circuit diagram of the current regulation circuit described in the embodiments of this application;

[0022] Figure 6 This is a schematic diagram of a DC-DC converter according to an embodiment of this application;

[0023] Figure 7 The waveforms of Vsam and V0 in the current regulation circuit described in the embodiments of this application are shown.

[0024] Figure 8 This is a waveform diagram of Vsense in the current regulation circuit described in the embodiments of this application;

[0025] Figure 9 This is a waveform diagram of Vsam in the current regulation circuit described in the embodiments of this application;

[0026] Figure 10 This is a waveform diagram of the output of the DC-DC converter described in the embodiments of this application;

[0027] Figure 11 This is a waveform diagram of the DC-DC converter described in the embodiments of this application, showing the output waveform of the converter reducing the current from a large current to a small current.

[0028] Figure 12 This is a waveform diagram of the DC-DC converter described in the embodiments of this application, showing the output waveform of the converter from small current to large current.

[0029] Figure 13 This is another output waveform diagram of the DC-DC converter described in the embodiments of this application, where the large current is reduced to a small current.

[0030] Figure 14 This refers to the bias current of the error amplification unit after doubling the current of the DC-DC converter described in the embodiments of this application. Detailed Implementation

[0031] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0032] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0033] Figure 1 This is a schematic diagram of a DC-DC converter.

[0034] refer to Figure 1 The diagram shown is a current-mode DC-DC converter circuit. A current-mode DC-DC converter is a dual-loop system. Current flows from input 100 through inductor L1, then through output feedback unit 110 to output 120, from output feedback unit 110 to error amplifier 130, and from error amplifier 130 to comparator 140. It then passes through PWM module 150 back to input 100, forming an outer loop. The current feedback module 160, comparator 140, PWM module 150, and input 100 together form the inner loop.

[0035] One characteristic of current-mode DC-DC converters is their relatively fast speed. This is due to their dual-loop circuit structure, which allows the circuit to establish a stable connection more quickly. A traditional method to accelerate the establishment speed of a current-mode DC-DC converter is to adjust the loop bandwidth at the output of the error amplifier 130 by adjusting resistor R5, capacitor C4, and compensation capacitor C3, thus achieving a faster speed. Another method is to add capacitor C2 between the output terminal 120 and the output feedback unit 110. The function of capacitor C2 is to accelerate the DC-DC converter through the action of the feedforward zero.

[0036] However, regardless of the method, both methods increase the speed of current-type DC-DC converters by adding energy storage components. If internal components are used, the required capacitance values ​​are relatively large, even in the nF range, resulting in a large required area. Using discrete components, on the other hand, easily increases costs.

[0037] To address the aforementioned problems, this application provides a current regulation circuit and a DC-DC converter. By adding a current regulation circuit to the circuit of the DC-DC converter, the current feedback of the current regulation circuit accelerates the stabilization of the output of the error amplification unit, thereby improving the DC-DC output efficiency.

[0038] Figure 2This is a graph showing the voltage change at the output terminal of a DC-DC converter when the current load changes by 50mA.

[0039] refer to Figure 2 As shown, Figure 2 This is a graph showing the output voltage change of a current-mode DC-DC converter as the output current changes from the μA level to the 50mA level. As can be seen from the graph, the change in current causes a drop in the 4.2V output voltage before it stabilizes, with a voltage change of approximately 14mV. The stabilization time is approximately 90µs. This can be seen from the system model of a current-mode DC-DC converter (reference...). Figure 1 As can be seen, the output feedback signal is fed from the output feedback unit 110 through the error amplifier 130 to adjust the comparator 140. The output stabilization voltage of the error amplifier 130 is different for different output currents. If a faster stabilization voltage can be obtained for the error amplifier 130, the DC-DC output can reach a stable value more quickly. For the error amplifier 130, directly increasing its bias current can speed up its output stabilization time. However, directly increasing the bias current has a direct problem: increased power consumption. For some circuit applications, especially those related to the Internet of Things (IoT), power consumption is a major concern. Considering that the DC-DC output has the slowest stabilization time during the transition from heavy load to light load, this is because the DC-DC output generates an overshoot voltage during this transition. Under light load conditions, this overshoot voltage can only be discharged with a small current, so the smaller this overshoot voltage, the better. Taking all these factors into consideration, the technical solution of this application employs a current adjustment (CAD) circuit that monitors the output current and feeds back an adjustable bias current to the error amplifier 130. The CAD circuit monitors the output current; when a large output current is detected, it provides a small bias current to the error amplifier; when a small output current is detected, it provides a large bias current to the error amplifier. Detailed descriptions are provided below in conjunction with the accompanying drawings.

[0040] Figure 3 This is a circuit diagram of the first part of the current regulation circuit described in the embodiments of this application; Figure 4 This is a second part of the circuit diagram of the current regulation circuit described in the embodiments of this application; Figure 5 This is the third part of the circuit diagram of the current regulation circuit described in the embodiments of this application. Because the current regulation circuit described in the embodiments of this application is relatively complex, it is explained in three parts.

[0041] Embodiments of this application provide a current regulation circuit, referencing Figure 3 , Figure 4 andFigure 5 The system includes: a monitoring module 210 connected to the circuit to be monitored; an amplifier 220, the input of which is connected to the output of the monitoring module 210, capable of amplifying the output voltage of the monitoring module 210 and outputting an amplified voltage; a comparator 230, the input of which is connected to the output of the amplifier 220, capable of outputting according to the amplified voltage; a control module 240, the input of which is connected to the output of the comparator 230, capable of outputting a control voltage according to the output of the comparator 230; and an output module 250, the input of which is connected to the output of the control module 240, capable of outputting according to the control voltage.

[0042] refer to Figure 3 The current regulation circuit includes a monitoring module 210, which is connected to the circuit to be monitored.

[0043] In some embodiments of this application, the monitoring module 210 includes a monitoring resistor R1 and voltage divider resistors R2, R3, R4, and R5. The monitoring module 210 is connected to the circuit to be monitored by connecting the monitoring resistor R1 in series with the circuit. The monitoring resistor R1 is used to detect the output current of the circuit to be monitored, while R2, R3, R4, and R5 are used as voltage divider resistors.

[0044] Continue to refer to Figure 3 The current regulation circuit also includes an amplifier 220, the input terminal of which is connected to the output terminal of the monitoring module 210, which can amplify the output voltage of the monitoring module 210 and output an amplified voltage.

[0045] Let Vsense represent the voltage across the monitoring resistor R1. Let V1 be the voltage across the left end of R1 and V2 be the voltage across the right end. Then:

[0046] Vsense=V1-V2 (1)

[0047] With the input terminals of amplifier 220 having equal potentials, and assuming the output of amplifier 220 is Vsam, we can obtain:

[0048] V1*R2 / (R1+R2)=Vsam+(V2-Vsam)*R4 / (R3+R4) (2)

[0049] Simplifying formula (2) yields:

[0050] (Vsense*R2*R4+V1*R2*R3-V2*R1*R4) / (R1+R2)=R3*Vsam (3)

[0051] Let R1 = R3, R2 = R4, then we get:

[0052] (Vsense*R2*R4+Vsense*R1*R4) / (R1+R2)=R3*Vsam; (4)

[0053] Further simplification of formula (4) yields the following relationship between Vsense and Vsam:

[0054] Vsense*R4=R3*Vsam; (5)

[0055] We set R4 to 200K, R3 to 20K, and Vsam to 10 * Vsense. This means that the monitored voltage is amplified 10 times before being output by the amplifier.

[0056] The magnitude of the amplification factor determines how many levels the operating current of the error amplifier can be divided into. The larger the amplification factor, the larger the voltage obtained. In the subsequent comparator, it can be compared with multiple different reference voltages (Vref) to obtain multiple levels of control voltage. These control voltages can turn more error amplifier operating currents on or off.

[0057] In some embodiments of this application, the amplifier 220 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, and a second NMOS transistor NM2.

[0058] In this configuration, the source of the first PMOS transistor PM1 is connected to AVDD, and the drain of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2 and the source of the third PMOS transistor PM3. The gate of the first PMOS transistor PM1 is connected to the bias current BIAS. The gates of the second PMOS transistor PM2 and the third PMOS transistor PM3 are the two input terminals of the amplifier 220 (the input terminals are connected to the output terminal of the monitoring module 210, the gate of the second PMOS transistor PM2 is connected to R2, and the gate of the third PMOS transistor PM3 is connected to R4). The drain of the third PMOS transistor PM3 is the output terminal of the amplifier 220. The drain of the second PMOS transistor PM2 is connected to the gate and drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2. The source of the first NMOS transistor NM1 is grounded. The drain of the third PMOS transistor PM3 is connected to the drain of the second NMOS transistor NM2. The source of the second NMOS transistor NM2 is grounded.

[0059] Continue to refer to Figure 3The current regulation circuit further includes a comparator 230, the input of which is connected to the output of the amplifier 220, and can output according to the amplified voltage. The output of the amplifier 220 is compared with Vref (reference voltage) by the comparator 230. The output V0 controls the bias current branch of the error amplification unit.

[0060] In some embodiments of this application, the comparator 230 includes: an input module 231, one input terminal of which is connected to the output terminal of the amplifier 220 (to connect the comparator 230 and the amplifier 220), and the other input terminal is connected to the reference voltage Vref; and a shaping module 232, the input terminal of which is connected to the output terminal of the input module 231, and the output terminal of the shaping module 232 is the output terminal of the comparator 230, outputting V0.

[0061] In some embodiments of this application, the input module 231 includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, and a fourth NMOS transistor NM4.

[0062] The gate of the fourth PMOS transistor PM4 is connected to the output terminal of the amplifier 220 (connected to the drain of the third PMOS transistor PM3), and the gate of the fifth PMOS transistor PM5 is connected to the reference voltage Vref; the drain of the fourth PMOS transistor PM4 is connected to the gate and drain of the third NMOS transistor NM3, and the source of the third NMOS transistor NM3 is grounded; the drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4, and the source of the fourth NMOS transistor NM4 is grounded.

[0063] In some embodiments of this application, the shaping module 232 includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6.

[0064] Specifically, the source of the sixth PMOS transistor PM6 is connected to AVDD, and the drain of the sixth PMOS transistor PM6 is connected to the drain of the fifth NMOS transistor NM5 and the gates of the seventh PMOS transistor PM7 and the sixth NMOS transistor NM6; the source of the seventh PMOS transistor PM7 is connected to AVDD, and the drain of the seventh PMOS transistor PM7 is connected to the drain of the sixth NMOS transistor NM6; the source of the fifth NMOS transistor NM5 is grounded, and the source of the sixth NMOS transistor NM6 is grounded.

[0065] In some embodiments of this application, the comparator 230 further includes: a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, and an eighth NMOS transistor NM8.

[0066] Specifically, the gate of the ninth PMOS transistor PM9 is connected to the bias current BIAS, the source of the ninth PMOS transistor PM9 is connected to AVDD, and the drain of the ninth PMOS transistor PM9 is connected to the source of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5; the source of the tenth PMOS transistor PM10 is connected to AVDD, the gate of the tenth PMOS transistor PM10 is connected to the bias current BIAS, and the drain of the tenth PMOS transistor PM10 is connected to the gate of the sixth PMOS transistor PM6, the fifth NMOS transistor NM5, and the drain of the eighth NMOS transistor NM8; the source of the eighth NMOS transistor NM8 is grounded, and the gate of the eighth NMOS transistor NM8 is connected to the drain of the fifth PMOS transistor PM5.

[0067] Figure 7 The waveforms of Vsam and V0 in the current regulation circuit described in the embodiments of this application are shown. Figure 8 This is a waveform diagram of Vsense in the current regulation circuit described in the embodiments of this application; Figure 9 This is a waveform diagram of Vsam in the current regulation circuit described in the embodiments of this application. Figure 7 It demonstrates the logical relationship between Vsam and V0; when Vsam increases, V0 decreases. Figure 8 and Figure 9 This demonstrates the relationship between Vsam and Vsense, where Vsam is 10 * Vsense.

[0068] refer to Figure 4 The current regulation circuit shown also includes a control module 240. The input terminal of the control module 240 is connected to the output terminal of the comparator 230, and it can output a control voltage Vctrl according to the output of the comparator 230.

[0069] In some embodiments of this application, the control module 240 includes at least one control circuit, which includes an eighth PMOS transistor PM8 and a seventh NMOS transistor NM7.

[0070] The gates of the eighth PMOS transistor PM8 and the seventh NMOS transistor NM7 are connected to the output terminal of the comparator 230 (i.e., Figure 3 The output V0); the source of the eighth PMOS transistor PM8 is connected to AVDD; the drain of the eighth PMOS transistor PM8 is connected to the drain of the seventh NMOS transistor NM7 and the output control voltage Vctrl; the source of the seventh NMOS transistor NM7 is connected to AVSS.

[0071] refer to Figure 5The current regulation circuit shown also includes an output module 250. The input terminal of the output module 250 is connected to the output terminal of the control module 240 (i.e., connected to the control voltage Vctrl), and can output according to the control voltage Vctrl.

[0072] In some embodiments of this application, the output module 250 includes at least one PMOS output switch PM11, which is controlled by a control voltage Vctrl output by the control module 240. The output module 250 also includes an output unit PM12 connected to the output switch PM11. The control voltage Vctrl controls whether the output switch PM11 is turned on to provide a bias voltage to the output unit PM12, thereby determining the final output Vout of the current control circuit.

[0073] In some embodiments of this application, only one output switch PM11 and one corresponding output unit PM12 may be provided. In other embodiments of this application, multiple output switches 11 and multiple corresponding output units 12 may be provided.

[0074] Continue to refer to Figure 5 As shown, the output module 250 also includes a fixed output unit PM13. When the control voltage Vctrl controls the output switch PM11 to open and provide a bias voltage to the output unit PM12, the output unit PM12 and the fixed output unit PM13 output Vout together; conversely, when the control voltage Vctrl controls the output switch PM11 to close and does not provide a bias voltage to the output unit PM12, only the fixed output unit PM13 outputs Vout alone.

[0075] In some embodiments of this application, multiple fixed output units PM13 can be configured to provide output together.

[0076] Continue to refer to Figure 5 As shown, the output module 250 also includes a fourteenth PMOS transistor PM14. The gate of the fourteenth PMOS transistor PM14 is connected to the power-down power supply PDn, which can control the power-off of the output unit and the fixed output unit. The source of the fourteenth PMOS transistor PM14 is connected to AVDD, and the drain of the fourteenth PMOS transistor PM14 is connected to the bias current IB, the gate of the fixed output unit PM13, and the source of the output switch PM11.

[0077] Combination Figure 4 and Figure 5The output V0 of comparator 230 is output as a control signal Vctrl by the inverter composed of PM8 and NM7 in control module 240. Vctrl controls whether PM11 is turned on to provide bias voltage to PM12, thereby determining the current capability of the error amplifier unit. When the current detected by the monitoring resistor is relatively small (here, 10mA is taken as the comparison point, but the comparison point can be arbitrarily selected), V0 output is high. After passing through the inverter, Vctrl is low, PM11 is turned on, and PM12 and PM13 together provide current to the error amplifier unit. Conversely, only PM13 provides current to the error amplifier unit. When there are more comparison levels, multiple bias currents (i.e., multiple control modules 240 and output units) can be selected to provide current to the error amplifier unit.

[0078] The current regulation circuit described in this application embodiment can be used in the circuit of a DC-DC converter. The monitoring module of the current regulation circuit monitors the output of the DC-DC converter and generates a control voltage based on the output of the DC-DC converter to control the output Vout of the current regulation circuit. Through the current feedback of the current regulation circuit, the stability of the error amplifier output in the DC-DC converter is accelerated, thereby achieving the purpose of improving the DC-DC output efficiency.

[0079] Embodiments of this application also provide a current-mode DC-DC converter, see reference. Figure 6 , Figure 6 This is a schematic diagram of a DC-DC converter according to an embodiment of this application, including: an input unit 300, an output unit 320, an output feedback unit 310, an error amplification unit 330, and a current regulation circuit 370 as described above. One end of the monitoring module in the current regulation circuit 370 is connected to the output terminal of the input unit 300, and the other end is connected to the input terminal of the output feedback unit 310. The output terminal of the current regulation circuit 370 is connected to one input terminal of the error amplification unit 330. The output terminal of the output feedback unit 310 is connected to the input terminal of the output unit 320 and the other input terminal of the error amplification unit 330.

[0080] In some embodiments of this application, the DC-DC converter further includes: a comparison unit 340, a PWM unit 350, and a feedback circuit 360; one input terminal of the comparison unit 340 is connected to the output terminal of the feedback circuit 360, and the second input terminal is connected to the output terminal of the error amplification unit 330; the input terminal of the PWM unit 350 is connected to the output terminal of the comparison unit 340, and the output terminal of the PWM unit 350 is connected to the input unit 300; the input terminal of the feedback circuit 360 is connected to the output terminal of the input unit 300.

[0081] The current flows from the input unit 300 through inductor L1, then through the output feedback unit 310 to the output unit 320, from the output feedback unit 310 to the error amplification unit 330, and from the error amplification unit 330 to the comparator unit 340. It then passes through the PWM unit 350 back to the input unit 300, forming an outer loop. The feedback circuit 360, together with the comparator unit 340, the PWM unit 350, and the input unit 300, form the inner loop.

[0082] The monitoring resistor R6 in the monitoring module of the current regulation circuit 370 (i.e. Figure 3 One end of R1 is connected to the inductor L1, and the other end is connected to the output feedback unit 310. The output terminal of the current regulation circuit 370 is connected to the error amplification unit 330, and outputs Vout to the error amplification unit 330. The current regulation circuit 370 can control the output Vout according to the voltage monitored by the monitoring resistor R6, thereby accelerating the stabilization of the output of the error amplification unit 330 and improving the efficiency of the DC-DC output.

[0083] Figure 10 This is a waveform diagram of the output of the DC-DC converter described in the embodiments of this application; Figure 11 This is a waveform diagram of the DC-DC converter described in the embodiments of this application, showing the output waveform of the converter reducing the current from a large current to a small current. Figure 12 This is a waveform diagram of the DC-DC converter described in the embodiments of this application, showing the output waveform of the converter from small current to large current. Figure 13 This is another output waveform diagram of the DC-DC converter described in the embodiments of this application, where the large current is reduced to a small current.

[0084] from Figure 10 and Figure 13 It can be seen that the current regulation circuit can accelerate the stabilization of the DC-DC output. For the undershoot signal, the current is reduced from 14mV to 9mV, and the stabilization time is shortened by 20µs to 30µs; for the overshoot signal, the current is reduced by nearly 20mV.

[0085] Figure 14 This refers to the bias current of the error amplifier unit after the current of the DC-DC converter described in this application embodiment is doubled. After the current is doubled, the bias current of the error amplifier will also increase due to the effect of the current adjustment circuit.

[0086] The embodiment of this application describes a current regulation circuit and a DC-DC converter. By adding a current regulation circuit to the circuit of the DC-DC converter, the current feedback of the current regulation circuit accelerates the stabilization of the output of the error amplification unit, thereby achieving the purpose of improving the DC-DC output efficiency.

[0087] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0088] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0089] It should be understood that the terms "comprising," "containing," "including," or "including" as used in this application document indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0090] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0091] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A current regulating circuit, characterized in that, include: The monitoring module is connected to the circuit to be monitored; An amplifier is provided, the input terminal of which is connected to the monitoring module. The amplifier amplifies the output voltage of the monitoring module and outputs an amplified voltage. The amplifier includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to AVDD, and its gate is connected to the bias current BIAS. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the source of the third PMOS transistor. The gates of the second and third PMOS transistors are the two input terminals of the amplifier, and the drain of the third PMOS transistor is the output terminal of the amplifier. The drain of the second PMOS transistor is connected to the gate and drain of the first NMOS transistor and the gate of the second NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the third PMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded. The monitoring module includes a monitoring resistor R5 and voltage divider resistors R1, R2, R3, and R4. The monitoring module is connected to the circuit to be monitored by connecting the monitoring resistor R5 in series with the circuit. One end of the monitoring resistor R5 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the resistor R2 and the gate of the second PMOS transistor, the other end of the resistor R2 is grounded, the other end of the monitoring resistor R5 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to one end of the resistor R4 and the gate of the third PMOS transistor, and the other end of the resistor R4 is connected to the drain of the third PMOS transistor. A comparator, the input of which is connected to the output of the amplifier, is capable of outputting according to the amplified voltage; The control module has its input terminal connected to the output terminal of the comparator and is able to output a control voltage based on the output of the comparator. An output module, the input terminal of which is connected to the output terminal of the control module, is capable of outputting according to the control voltage.

2. The current regulating circuit as described in claim 1, characterized in that, The comparator includes: The input module has one input terminal connected to the output terminal of the amplifier and the other input terminal connected to a reference voltage. A connection module, wherein one input terminal of the connection module is connected to the output terminal of the input module; A shaping module, wherein the input of the shaping module is connected to the output of the connection module, and the output of the shaping module is the output of the comparator.

3. The current regulating circuit as described in claim 2, characterized in that, The input module includes: a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The gate of the fourth PMOS transistor is connected to the output terminal of the amplifier, and the gate of the fifth PMOS transistor is connected to the reference voltage. The drain of the fourth PMOS transistor is connected to the gate and drain of the third NMOS transistor and the gate of the fourth NMOS transistor, and the source of the third NMOS transistor is grounded. The drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is grounded; the drain of the fifth PMOS transistor serves as the output terminal of the input module. The connection module includes a ninth PMOS transistor, a tenth PMOS transistor, and an eighth NMOS transistor. The gates of the ninth and tenth PMOS transistors are connected to a bias current BIAS. The sources of the ninth and tenth PMOS transistors are connected to AVDD. The drain of the ninth PMOS transistor is connected to the sources of the fourth and fifth PMOS transistors. The drain of the tenth PMOS transistor is connected to the drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is connected to the drain of the fifth PMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the tenth PMOS transistor serves as the output terminal of the connection module.

4. The current regulating circuit as described in claim 3, characterized in that, The shaping module includes: a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The source of the sixth PMOS transistor is connected to AVDD, and the drain of the sixth PMOS transistor is connected to the drain of the fifth NMOS transistor and the gates of the seventh PMOS transistor and the sixth NMOS transistor; the gates of the sixth PMOS transistor and the fifth NMOS transistor are connected to the drain of the tenth PMOS transistor. The source of the seventh PMOS transistor is connected to AVDD, and the drain of the seventh PMOS transistor is connected to the drain of the sixth NMOS transistor; the drain of the seventh PMOS transistor serves as the output terminal of the shaping module. The source of the fifth NMOS transistor is grounded, and the source of the sixth NMOS transistor is grounded.

5. The current regulating circuit as described in claim 1, characterized in that, The control module includes at least one control circuit, the control circuit comprising: Eighth PMOS transistor, seventh NMOS transistor; The gates of the eighth PMOS transistor and the seventh NMOS transistor are connected to the output of the comparator. The source of the eighth PMOS transistor is connected to AVDD, and the drain of the eighth PMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is connected to AVSS, and the drain of the eighth PMOS transistor serves as the output terminal of the control module.

6. The current regulating circuit as described in claim 1, characterized in that, The output module includes at least one PMOS output switch, which is controlled by the control voltage output by the control module.

7. A DC-DC converter, characterized in that, include: The input unit, the output unit, the output feedback unit, the error amplification unit, and the current regulation circuit as described in any one of claims 1 to 6; One end of the monitoring module in the current regulation circuit is connected to the output terminal of the input unit, and the other end is connected to the input terminal of the output feedback unit. The output terminal of the current regulation circuit is connected to one input terminal of the error amplification unit. The output terminal of the output feedback unit is connected to the input terminal of the output unit and another input terminal of the error amplification unit.

8. The DC-DC converter as described in claim 7, characterized in that, Also includes: Comparator unit, PWM unit, feedback circuit; One input terminal of the comparison unit is connected to the output terminal of the feedback circuit, and the second input terminal is connected to the output terminal of the error amplification unit. The input terminal of the PWM unit is connected to the output terminal of the comparator unit, and the output terminal of the PWM is connected to the input unit. The input terminal of the feedback circuit is connected to the output terminal of the input unit.

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